target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch

   1 From fcfa66de8a2f0631a65a2cec0f6149dafd36ec81 Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Mon, 5 Aug 2013 11:50:25 +0100
   4 Subject: [PATCH] MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0
   5
   6 The hardware interrupt routing for boot CPU != 0 is wrong because it
   7 will route all the hardware interrupts to TP0 which is not the one we
   8 booted from. Fix this by properly checking which boot CPU we are booting
   9 from and updating the right interrupt mask for the boot CPU. This fixes
  10 booting on BCM3368 with bmips_smp_emabled = 0.
  11
  12 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  13 Cc: linux-mips@linux-mips.org
  14 Cc: blogic@openwrt.org
  15 Cc: jogo@openwrt.org
  16 Cc: cernekee@gmail.com
  17 Patchwork: https://patchwork.linux-mips.org/patch/5650/
  18 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  19 ---
  20  arch/mips/kernel/smp-bmips.c | 10 ++++++++--
  21  1 file changed, 8 insertions(+), 2 deletions(-)
  22
  23 --- a/arch/mips/kernel/smp-bmips.c
  24 +++ b/arch/mips/kernel/smp-bmips.c
  25 @@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
  26         int i, cpu = 1, boot_cpu = 0;
  27
  28  #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
  29 +       int cpu_hw_intr;
  30 +
  31         /* arbitration priority */
  32         clear_c0_brcm_cmt_ctrl(0x30);
  33
  34 @@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void)
  35          * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  36          * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  37          */
  38 -       change_c0_brcm_cmt_intr(0xf8018000,
  39 -                                       (0x02 << 27) | (0x03 << 15));
  40 +       if (boot_cpu == 0)
  41 +               cpu_hw_intr = 0x02;
  42 +       else
  43 +               cpu_hw_intr = 0x1d;
  44 +
  45 +       change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
  46
  47         /* single core, 2 threads (2 pipelines) */
  48         max_cpus = 2;