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brcm63xx: Add profile and build image for Sagemcom F@ST2704V2 ADSL router
[openwrt/openwrt.git] / target / linux / brcm63xx / patches-3.10 / 339-MIPS-BCM63XX-add-support-for-BCM63268.patch
1 From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sat, 7 Dec 2013 17:14:17 +0100
4 Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
5
6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
7 ---
8 arch/mips/bcm63xx/Kconfig | 5 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
10 arch/mips/bcm63xx/clk.c | 25 ++++-
11 arch/mips/bcm63xx/cpu.c | 59 +++++++++-
12 arch/mips/bcm63xx/dev-flash.c | 6 +
13 arch/mips/bcm63xx/dev-spi.c | 4 +-
14 arch/mips/bcm63xx/irq.c | 20 +++-
15 arch/mips/bcm63xx/reset.c | 21 ++++
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 12 files changed, 342 insertions(+), 12 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -60,6 +60,11 @@ config BCM63XX_CPU_6368
25 select HW_HAS_PCI
26 select BCM63XX_OHCI
27 select BCM63XX_EHCI
28 +
29 +config BCM63XX_CPU_63268
30 + bool "support 63268 CPU"
31 + select SYS_HAS_CPU_BMIPS4350
32 + select HW_HAS_PCI
33 endmenu
34
35 source "arch/mips/bcm63xx/boards/Kconfig"
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -825,7 +825,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
43 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk,
50 CKCTL_6368_SWPKT_USB_EN |
51 CKCTL_6368_SWPKT_SAR_EN,
52 enable);
53 + else if (BCMCPU_IS_63268())
54 + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
55 else
56 return;
57
58 @@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in
59 bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
60 else if (BCMCPU_IS_6368())
61 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
62 + else if (BCMCPU_IS_63268())
63 + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
64 else
65 return;
66
67 @@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in
68 bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
69 else if (BCMCPU_IS_6368())
70 bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
71 + else if (BCMCPU_IS_63268())
72 + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
73 else
74 return;
75
76 @@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int
77 mask = CKCTL_6358_SPI_EN;
78 else if (BCMCPU_IS_6362())
79 mask = CKCTL_6362_SPI_EN;
80 - else
81 - /* BCMCPU_IS_6368 */
82 + else if (BCMCPU_IS_6368())
83 mask = CKCTL_6368_SPI_EN;
84 + else if (BCMCPU_IS_63268())
85 + mask = CKCTL_63268_SPI_EN;
86 + else
87 + return;
88 +
89 bcm_hwclock_set(mask, enable);
90 }
91
92 @@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i
93 mask = CKCTL_6328_HSSPI_EN;
94 else if (BCMCPU_IS_6362())
95 mask = CKCTL_6362_HSSPI_EN;
96 + else if (BCMCPU_IS_63268())
97 + mask = CKCTL_63268_HSSPI_EN;
98 else
99 return;
100
101 @@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in
102 bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
103 else if (BCMCPU_IS_6362())
104 bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
105 + else if (BCMCPU_IS_63268())
106 + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
107 }
108
109 static struct clk clk_pcie = {
110 @@ -374,9 +388,11 @@ struct clk *clk_get(struct device *dev,
111 return &clk_periph;
112 if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
113 return &clk_pcm;
114 - if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
115 + if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) &&
116 + !strcmp(id, "ipsec"))
117 return &clk_ipsec;
118 - if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
119 + if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) &&
120 + !strcmp(id, "pcie"))
121 return &clk_pcie;
122 return ERR_PTR(-ENOENT);
123 }
124 @@ -399,6 +415,7 @@ static int __init bcm63xx_clk_init(void)
125 clk_hsspi.rate = HSSPI_PLL_HZ_6328;
126 break;
127 case BCM6362_CPU_ID:
128 + case BCM63268_CPU_ID:
129 clk_hsspi.rate = HSSPI_PLL_HZ_6362;
130 break;
131 }
132 --- a/arch/mips/bcm63xx/cpu.c
133 +++ b/arch/mips/bcm63xx/cpu.c
134 @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
135
136 };
137
138 +static const unsigned long bcm63268_regs_base[] = {
139 + __GEN_CPU_REGS_TABLE(63268)
140 +};
141 +
142 +static const int bcm63268_irqs[] = {
143 + __GEN_CPU_IRQ_TABLE(63268)
144 +
145 +};
146 +
147 u32 bcm63xx_get_cpu_variant(void)
148 {
149 return bcm63xx_cpu_variant;
150 @@ -251,6 +260,27 @@ static unsigned int detect_cpu_clock(voi
151
152 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
153 }
154 + case BCM63268_CPU_ID:
155 + {
156 + unsigned int tmp, mips_pll_fcvo;
157 +
158 + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
159 + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
160 + STRAPBUS_63268_FCVO_SHIFT;
161 + switch (mips_pll_fcvo) {
162 + case 0x3:
163 + case 0xe:
164 + return 320000000;
165 + case 0xa:
166 + return 333000000;
167 + case 0x2:
168 + case 0xb:
169 + case 0xf:
170 + return 400000000;
171 + default:
172 + return 0;
173 + }
174 + }
175
176 default:
177 BUG();
178 @@ -265,7 +295,7 @@ static unsigned int detect_memory_size(v
179 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
180 u32 val;
181
182 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
183 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
184 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
185
186 if (BCMCPU_IS_6345()) {
187 @@ -304,6 +334,7 @@ void __init bcm63xx_cpu_init(void)
188 struct cpuinfo_mips *c = &current_cpu_data;
189 unsigned int cpu = smp_processor_id();
190 u32 chipid_reg;
191 + bool long_chipid = false;
192 u8 __maybe_unused varid = 0;
193
194 /* soc registers location depends on cpu type */
195 @@ -325,6 +356,9 @@ void __init bcm63xx_cpu_init(void)
196 case 0x10:
197 chipid_reg = BCM_6345_PERF_BASE;
198 break;
199 + case 0x80:
200 + long_chipid = true;
201 + /* fall-through */
202 default:
203 chipid_reg = BCM_6368_PERF_BASE;
204 break;
205 @@ -332,6 +366,7 @@ void __init bcm63xx_cpu_init(void)
206 break;
207 }
208
209 +
210 /*
211 * really early to panic, but delaying panic would not help since we
212 * will never get any working console
213 @@ -341,10 +376,17 @@ void __init bcm63xx_cpu_init(void)
214
215 /* read out CPU type */
216 tmp = bcm_readl(chipid_reg);
217 - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
218 - bcm63xx_cpu_variant = bcm63xx_cpu_id;
219 +
220 + if (long_chipid) {
221 + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
222 + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
223 + } else {
224 + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
225 + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
226 + }
227 +
228 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
229 - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
230 + bcm63xx_cpu_variant = bcm63xx_cpu_id;
231
232 switch (bcm63xx_cpu_id) {
233 case BCM3368_CPU_ID:
234 @@ -399,6 +441,15 @@ void __init bcm63xx_cpu_init(void)
235 /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
236 bcm63xx_cpu_id = BCM6368_CPU_ID;
237 break;
238 + case BCM63168_CPU_ID:
239 + case BCM63169_CPU_ID:
240 + case BCM63268_CPU_ID:
241 + case BCM63269_CPU_ID:
242 + bcm63xx_regs_base = bcm63268_regs_base;
243 + bcm63xx_irqs = bcm63268_irqs;
244 +
245 + bcm63xx_cpu_id = BCM63268_CPU_ID;
246 + break;
247 default:
248 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
249 break;
250 --- a/arch/mips/bcm63xx/dev-flash.c
251 +++ b/arch/mips/bcm63xx/dev-flash.c
252 @@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t
253 case STRAPBUS_6368_BOOT_SEL_PARALLEL:
254 return BCM63XX_FLASH_TYPE_PARALLEL;
255 }
256 + case BCM63268_CPU_ID:
257 + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
258 + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
259 + return BCM63XX_FLASH_TYPE_SERIAL;
260 + else
261 + return BCM63XX_FLASH_TYPE_NAND;
262 default:
263 return -EINVAL;
264 }
265 --- a/arch/mips/bcm63xx/dev-spi.c
266 +++ b/arch/mips/bcm63xx/dev-spi.c
267 @@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
268 if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
269 bcm63xx_regs_spi = bcm6348_regs_spi;
270 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
271 - BCMCPU_IS_6362() || BCMCPU_IS_6368())
272 + BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268())
273 bcm63xx_regs_spi = bcm6358_regs_spi;
274 }
275
276 @@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void)
277 }
278
279 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
280 - BCMCPU_IS_6368()) {
281 + BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
282 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
283 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
284 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
285 --- a/arch/mips/bcm63xx/irq.c
286 +++ b/arch/mips/bcm63xx/irq.c
287 @@ -158,6 +158,7 @@ static void __internal_irq_unmask_##widt
288
289 BUILD_IPIC_INTERNAL(32);
290 BUILD_IPIC_INTERNAL(64);
291 +BUILD_IPIC_INTERNAL(128);
292
293 asmlinkage void plat_irq_dispatch(void)
294 {
295 @@ -343,6 +344,7 @@ static int bcm63xx_external_irq_set_type
296 case BCM6358_CPU_ID:
297 case BCM6362_CPU_ID:
298 case BCM6368_CPU_ID:
299 + case BCM63268_CPU_ID:
300 if (levelsense)
301 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
302 else
303 @@ -515,6 +517,18 @@ static void bcm63xx_init_irq(void)
304 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
305 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
306 break;
307 + case BCM63268_CPU_ID:
308 + irq_stat_addr[0] += PERF_IRQSTAT_63268_REG(0);
309 + irq_mask_addr[0] += PERF_IRQMASK_63268_REG(0);
310 + irq_stat_addr[1] += PERF_IRQSTAT_63268_REG(1);
311 + irq_mask_addr[1] += PERF_IRQMASK_63268_REG(1);
312 + irq_bits = 128;
313 + ext_irq_count = 4;
314 + is_ext_irq_cascaded = 1;
315 + ext_irq_start = BCM_63268_EXT_IRQ0 - IRQ_INTERNAL_BASE;
316 + ext_irq_end = BCM_63268_EXT_IRQ3 - IRQ_INTERNAL_BASE;
317 + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_63268;
318 + break;
319 default:
320 BUG();
321 }
322 @@ -523,10 +537,14 @@ static void bcm63xx_init_irq(void)
323 dispatch_internal = __dispatch_internal_32;
324 internal_irq_mask = __internal_irq_mask_32;
325 internal_irq_unmask = __internal_irq_unmask_32;
326 - } else {
327 + } else if (irq_bits == 64) {
328 dispatch_internal = __dispatch_internal_64;
329 internal_irq_mask = __internal_irq_mask_64;
330 internal_irq_unmask = __internal_irq_unmask_64;
331 + } else {
332 + dispatch_internal = __dispatch_internal_128;
333 + internal_irq_mask = __internal_irq_mask_128;
334 + internal_irq_unmask = __internal_irq_unmask_128;
335 }
336 }
337
338 --- a/arch/mips/bcm63xx/reset.c
339 +++ b/arch/mips/bcm63xx/reset.c
340 @@ -125,6 +125,20 @@
341 #define BCM6368_RESET_PCIE 0
342 #define BCM6368_RESET_PCIE_EXT 0
343
344 +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
345 +#define BCM63268_RESET_ENET 0
346 +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK
347 +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK
348 +#define BCM63268_RESET_DSL 0
349 +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK
350 +#define BCM63268_RESET_EPHY 0
351 +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
352 +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
353 +#define BCM63268_RESET_MPI 0
354 +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
355 + SOFTRESET_63268_PCIE_CORE_MASK)
356 +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
357 +
358 /*
359 * core reset bits
360 */
361 @@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] =
362 __GEN_RESET_BITS_TABLE(6368)
363 };
364
365 +static const u32 bcm63268_reset_bits[] = {
366 + __GEN_RESET_BITS_TABLE(63268)
367 +};
368 +
369 const u32 *bcm63xx_reset_bits;
370 static int reset_reg;
371
372 @@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini
373 } else if (BCMCPU_IS_6368()) {
374 reset_reg = PERF_SOFTRESET_6368_REG;
375 bcm63xx_reset_bits = bcm6368_reset_bits;
376 + } else if (BCMCPU_IS_63268()) {
377 + reset_reg = PERF_SOFTRESET_63268_REG;
378 + bcm63xx_reset_bits = bcm63268_reset_bits;
379 }
380
381 return 0;
382 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
383 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
384 @@ -21,6 +21,10 @@
385 #define BCM6362_CPU_ID 0x6362
386 #define BCM6368_CPU_ID 0x6368
387 #define BCM6369_CPU_ID 0x6369
388 +#define BCM63168_CPU_ID 0x63168
389 +#define BCM63169_CPU_ID 0x63169
390 +#define BCM63268_CPU_ID 0x63268
391 +#define BCM63269_CPU_ID 0x63269
392
393 void __init bcm63xx_cpu_init(void);
394 u32 bcm63xx_get_cpu_variant(void);
395 @@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c
396 #ifdef CONFIG_BCM63XX_CPU_6368
397 case BCM6368_CPU_ID:
398 #endif
399 +
400 +#ifdef CONFIG_BCM63XX_CPU_63268
401 + case BCM63268_CPU_ID:
402 +#endif
403 break;
404 default:
405 unreachable();
406 @@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
407 #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
408 #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
409 #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
410 +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
411
412 #define BCMCPU_VARIANT_IS_3368() \
413 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
414 @@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu
415 (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
416 #define BCMCPU_VARIANT_IS_6369() \
417 (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
418 +#define BCMCPU_VARIANT_IS_63168() \
419 + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
420 +#define BCMCPU_VARIANT_IS_63169() \
421 + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
422 +#define BCMCPU_VARIANT_IS_63268() \
423 + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
424 +#define BCMCPU_VARIANT_IS_63269() \
425 + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
426
427 /*
428 * While registers sets are (mostly) the same across 63xx CPU, base
429 @@ -573,6 +590,52 @@ enum bcm63xx_regs_set {
430 #define BCM_6368_RNG_BASE (0xb0004180)
431 #define BCM_6368_MISC_BASE (0xdeadbeef)
432
433 +/*
434 + * 63268 register sets base address
435 + */
436 +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef)
437 +#define BCM_63268_PERF_BASE (0xb0000000)
438 +#define BCM_63268_TIMER_BASE (0xb0000080)
439 +#define BCM_63268_WDT_BASE (0xb000009c)
440 +#define BCM_63268_UART0_BASE (0xb0000180)
441 +#define BCM_63268_UART1_BASE (0xb00001a0)
442 +#define BCM_63268_GPIO_BASE (0xb00000c0)
443 +#define BCM_63268_SPI_BASE (0xb0000800)
444 +#define BCM_63268_HSSPI_BASE (0xb0001000)
445 +#define BCM_63268_UDC0_BASE (0xdeadbeef)
446 +#define BCM_63268_USBDMA_BASE (0xb000c800)
447 +#define BCM_63268_OHCI0_BASE (0xb0002600)
448 +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef)
449 +#define BCM_63268_USBH_PRIV_BASE (0xb0002700)
450 +#define BCM_63268_USBD_BASE (0xb0002400)
451 +#define BCM_63268_MPI_BASE (0xdeadbeef)
452 +#define BCM_63268_PCMCIA_BASE (0xdeadbeef)
453 +#define BCM_63268_PCIE_BASE (0xb06e0000)
454 +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef)
455 +#define BCM_63268_DSL_BASE (0xdeadbeef)
456 +#define BCM_63268_UBUS_BASE (0xdeadbeef)
457 +#define BCM_63268_ENET0_BASE (0xdeadbeef)
458 +#define BCM_63268_ENET1_BASE (0xdeadbeef)
459 +#define BCM_63268_ENETDMA_BASE (0xb000d800)
460 +#define BCM_63268_ENETDMAC_BASE (0xb000da00)
461 +#define BCM_63268_ENETDMAS_BASE (0xb000dc00)
462 +#define BCM_63268_ENETSW_BASE (0xb0700000)
463 +#define BCM_63268_EHCI0_BASE (0xb0002500)
464 +#define BCM_63268_SDRAM_BASE (0xdeadbeef)
465 +#define BCM_63268_MEMC_BASE (0xdeadbeef)
466 +#define BCM_63268_DDR_BASE (0xb0003000)
467 +#define BCM_63268_M2M_BASE (0xdeadbeef)
468 +#define BCM_63268_ATM_BASE (0xdeadbeef)
469 +#define BCM_63268_XTM_BASE (0xb0007000)
470 +#define BCM_63268_XTMDMA_BASE (0xb000b800)
471 +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef)
472 +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef)
473 +#define BCM_63268_PCM_BASE (0xb000b000)
474 +#define BCM_63268_PCMDMA_BASE (0xb000b800)
475 +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef)
476 +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
477 +#define BCM_63268_RNG_BASE (0xdeadbeef)
478 +#define BCM_63268_MISC_BASE (0xb0001800)
479
480 extern const unsigned long *bcm63xx_regs_base;
481
482 @@ -1084,6 +1147,73 @@ enum bcm63xx_irq {
483 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
484 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
485
486 +/*
487 + * 63268 irqs
488 + */
489 +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
490 +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32)
491 +
492 +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
493 +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16)
494 +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5)
495 +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2)
496 +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23)
497 +#define BCM_63268_UDC0_IRQ 0
498 +#define BCM_63268_ENET0_IRQ 0
499 +#define BCM_63268_ENET1_IRQ 0
500 +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13)
501 +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6)
502 +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
503 +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
504 +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
505 +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19)
506 +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4)
507 +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20)
508 +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5)
509 +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21)
510 +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6)
511 +#define BCM_63268_PCMCIA_IRQ 0
512 +#define BCM_63268_ENET0_RXDMA_IRQ 0
513 +#define BCM_63268_ENET0_TXDMA_IRQ 0
514 +#define BCM_63268_ENET1_RXDMA_IRQ 0
515 +#define BCM_63268_ENET1_TXDMA_IRQ 0
516 +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8)
517 +#define BCM_63268_ATM_IRQ 0
518 +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1)
519 +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2)
520 +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3)
521 +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4)
522 +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0)
523 +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1)
524 +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2)
525 +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3)
526 +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17)
527 +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
528 +
529 +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20)
530 +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3)
531 +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
532 +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
533 +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18)
534 +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
535 +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15)
536 +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
537 +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
538 +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
539 +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
540 +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22)
541 +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7)
542 +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24)
543 +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25)
544 +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10)
545 +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11)
546 +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0)
547 +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1)
548 +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12)
549 +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13)
550 +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14)
551 +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15)
552 +
553 extern const int *bcm63xx_irqs;
554
555 #define __GEN_CPU_IRQ_TABLE(__cpu) \
556 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
557 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
558 @@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio
559 return 48;
560 case BCM6368_CPU_ID:
561 return 38;
562 + case BCM63268_CPU_ID:
563 + return 52;
564 case BCM6348_CPU_ID:
565 default:
566 return 37;
567 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
568 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
569 @@ -9,6 +9,8 @@
570 #define PERF_REV_REG 0x0
571 #define REV_CHIPID_SHIFT 16
572 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
573 +#define REV_LONG_CHIPID_SHIFT 12
574 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
575 #define REV_VARID_SHIFT 8
576 #define REV_VARID_MASK (0xf << REV_VARID_SHIFT)
577 #define REV_REVID_SHIFT 0
578 @@ -211,6 +213,52 @@
579 CKCTL_6368_NAND_EN | \
580 CKCTL_6368_IPSEC_EN)
581
582 +#define CKCTL_63268_DISABLE_GLESS (1 << 0)
583 +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1)
584 +#define CKCTL_63268_VDSL_AFE_EN (1 << 2)
585 +#define CKCTL_63268_VDSL_EN (1 << 3)
586 +#define CKCTL_63268_MIPS_EN (1 << 4)
587 +#define CKCTL_63268_WLAN_OCP_EN (1 << 5)
588 +#define CKCTL_63268_DECT_EN (1 << 6)
589 +#define CKCTL_63268_FAP0_EN (1 << 7)
590 +#define CKCTL_63268_FAP1_EN (1 << 8)
591 +#define CKCTL_63268_SAR_EN (1 << 9)
592 +#define CKCTL_63268_ROBOSW_EN (1 << 10)
593 +#define CKCTL_63268_PCM_EN (1 << 11)
594 +#define CKCTL_63268_USBD_EN (1 << 12)
595 +#define CKCTL_63268_USBH_EN (1 << 13)
596 +#define CKCTL_63268_IPSEC_EN (1 << 14)
597 +#define CKCTL_63268_SPI_EN (1 << 15)
598 +#define CKCTL_63268_HSSPI_EN (1 << 16)
599 +#define CKCTL_63268_PCIE_EN (1 << 17)
600 +#define CKCTL_63268_PHYMIPS_EN (1 << 18)
601 +#define CKCTL_63268_GMAC_EN (1 << 19)
602 +#define CKCTL_63268_NAND_EN (1 << 20)
603 +#define CKCTL_63268_TBUS_EN (1 << 27)
604 +#define CKCTL_63268_ROBOSW250_EN (1 << 31)
605 +
606 +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \
607 + CKCTL_63268_VDSL_AFE_EN | \
608 + CKCTL_63268_VDSL_EN | \
609 + CKCTL_63268_WLAN_OCP_EN | \
610 + CKCTL_63268_DECT_EN | \
611 + CKCTL_63268_FAP0_EN | \
612 + CKCTL_63268_FAP1_EN | \
613 + CKCTL_63268_SAR_EN | \
614 + CKCTL_63268_ROBOSW_EN | \
615 + CKCTL_63268_PCM_EN | \
616 + CKCTL_63268_USBD_EN | \
617 + CKCTL_63268_USBH_EN | \
618 + CKCTL_63268_IPSEC_EN | \
619 + CKCTL_63268_SPI_EN | \
620 + CKCTL_63268_HSSPI_EN | \
621 + CKCTL_63268_PCIE_EN | \
622 + CKCTL_63268_PHYMIPS_EN | \
623 + CKCTL_63268_GMAC_EN | \
624 + CKCTL_63268_NAND_EN | \
625 + CKCTL_63268_TBUS_EN | \
626 + CKCTL_63268_ROBOSW250_EN)
627 +
628 /* System PLL Control register */
629 #define PERF_SYS_PLL_CTL_REG 0x8
630 #define SYS_PLL_SOFT_RESET 0x1
631 @@ -224,6 +272,7 @@
632 #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
633 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
634 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
635 +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20)
636
637 /* Interrupt Status register */
638 #define PERF_IRQSTAT_3368_REG 0x10
639 @@ -234,6 +283,7 @@
640 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
641 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
642 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
643 +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20)
644
645 /* External Interrupt Configuration register */
646 #define PERF_EXTIRQ_CFG_REG_3368 0x14
647 @@ -244,6 +294,7 @@
648 #define PERF_EXTIRQ_CFG_REG_6358 0x14
649 #define PERF_EXTIRQ_CFG_REG_6362 0x18
650 #define PERF_EXTIRQ_CFG_REG_6368 0x18
651 +#define PERF_EXTIRQ_CFG_REG_63268 0x18
652
653 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
654
655 @@ -273,6 +324,7 @@
656 #define PERF_SOFTRESET_6358_REG 0x34
657 #define PERF_SOFTRESET_6362_REG 0x10
658 #define PERF_SOFTRESET_6368_REG 0x10
659 +#define PERF_SOFTRESET_63268_REG 0x10
660
661 #define SOFTRESET_3368_SPI_MASK (1 << 0)
662 #define SOFTRESET_3368_ENET_MASK (1 << 2)
663 @@ -366,6 +418,26 @@
664 #define SOFTRESET_6368_USBH_MASK (1 << 12)
665 #define SOFTRESET_6368_PCM_MASK (1 << 13)
666
667 +#define SOFTRESET_63268_SPI_MASK (1 << 0)
668 +#define SOFTRESET_63268_IPSEC_MASK (1 << 1)
669 +#define SOFTRESET_63268_EPHY_MASK (1 << 2)
670 +#define SOFTRESET_63268_SAR_MASK (1 << 3)
671 +#define SOFTRESET_63268_ENETSW_MASK (1 << 4)
672 +#define SOFTRESET_63268_USBS_MASK (1 << 5)
673 +#define SOFTRESET_63268_USBH_MASK (1 << 6)
674 +#define SOFTRESET_63268_PCM_MASK (1 << 7)
675 +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8)
676 +#define SOFTRESET_63268_PCIE_MASK (1 << 9)
677 +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10)
678 +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11)
679 +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12)
680 +#define SOFTRESET_63268_FAP0_MASK (1 << 13)
681 +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14)
682 +#define SOFTRESET_63268_DECT_MASK (1 << 15)
683 +#define SOFTRESET_63268_FAP1_MASK (1 << 16)
684 +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17)
685 +#define SOFTRESET_63268_GPHY_MASK (1 << 18)
686 +
687 /* MIPS PLL control register */
688 #define PERF_MIPSPLLCTL_REG 0x34
689 #define MIPSPLLCTL_N1_SHIFT 20
690 @@ -1499,6 +1571,13 @@
691 #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
692 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
693
694 +#define MISC_STRAPBUS_63268_REG 0x14
695 +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9)
696 +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11)
697 +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11)
698 +#define STRAPBUS_63268_FCVO_SHIFT 21
699 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
700 +
701 #define MISC_STRAPBUS_6328_REG 0x240
702 #define STRAPBUS_6328_FCVO_SHIFT 7
703 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
704 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
705 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
706 @@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re
707 case BCM6328_CPU_ID:
708 case BCM6362_CPU_ID:
709 case BCM6368_CPU_ID:
710 + case BCM63268_CPU_ID:
711 if (offset >= 0xb0000000 && offset < 0xb1000000)
712 return 1;
713 break;
714 --- a/arch/mips/bcm63xx/dev-hsspi.c
715 +++ b/arch/mips/bcm63xx/dev-hsspi.c
716 @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
717
718 int __init bcm63xx_hsspi_register(void)
719 {
720 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
721 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
722 return -ENODEV;
723
724 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
725 --- a/arch/mips/bcm63xx/dev-enet.c
726 +++ b/arch/mips/bcm63xx/dev-enet.c
727 @@ -176,7 +176,8 @@ static int __init register_shared(void)
728 else
729 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
730
731 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
732 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
733 + BCMCPU_IS_63268())
734 chan_count = 32;
735 else if (BCMCPU_IS_6345())
736 chan_count = 8;
737 @@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm
738 {
739 int ret;
740
741 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
742 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
743 + !BCMCPU_IS_63268())
744 return -ENODEV;
745
746 ret = register_shared();
747 @@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm
748 enetsw_pd.num_ports = ENETSW_PORTS_6328;
749 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
750 enetsw_pd.num_ports = ENETSW_PORTS_6368;
751 + else if (BCMCPU_IS_63268())
752 + enetsw_pd.num_ports = ENETSW_PORTS_63268;
753
754 enetsw_pd.dma_has_sram = true;
755 enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
756 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
757 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
758 @@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data {
759 #define ENETSW_MAX_PORT 8
760 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
761 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
762 +#define ENETSW_PORTS_63268 4 /* 3 FE PHY + 1 RGMII */
763
764 #define ENETSW_RGMII_PORT0 4
765
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