target/linux/brcm63xx/patches-3.3/316-MIPS-BCM63XX-Add-PCIe-register-set-definitions.patch

   1 From 9a16718a325c1969422eb9d9b644eb89ce06692c Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sun, 3 Jul 2011 03:41:02 +0200
   4 Subject: [PATCH 46/79] MIPS: BCM63XX: Add PCIe register set definitions
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 ++++
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    6 +++
  10  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   54 +++++++++++++++++++++
  11  3 files changed, 69 insertions(+)
  12
  13 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  14 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  15 @@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
  16         RSET_USBH_PRIV,
  17         RSET_MPI,
  18         RSET_PCMCIA,
  19 +       RSET_PCIE,
  20         RSET_DSL,
  21         RSET_ENET0,
  22         RSET_ENET1,
  23 @@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
  24  #define BCM_6328_USBH_PRIV_BASE                (0xdeadbeef)
  25  #define BCM_6328_MPI_BASE              (0xdeadbeef)
  26  #define BCM_6328_PCMCIA_BASE           (0xdeadbeef)
  27 +#define BCM_6328_PCIE_BASE             (0xb0e40000)
  28  #define BCM_6328_SDRAM_REGS_BASE       (0xdeadbeef)
  29  #define BCM_6328_DSL_BASE              (0xb0001900)
  30  #define BCM_6328_UBUS_BASE             (0xdeadbeef)
  31 @@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
  32  #define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)
  33  #define BCM_6338_MPI_BASE              (0xfffe3160)
  34  #define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
  35 +#define BCM_6338_PCIE_BASE             (0xdeadbeef)
  36  #define BCM_6338_SDRAM_REGS_BASE       (0xfffe3100)
  37  #define BCM_6338_DSL_BASE              (0xfffe1000)
  38  #define BCM_6338_UBUS_BASE             (0xdeadbeef)
  39 @@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
  40  #define BCM_6345_ENETSW_BASE           (0xdeadbeef)
  41  #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
  42  #define BCM_6345_MPI_BASE              (0xfffe2000)
  43 +#define BCM_6345_PCIE_BASE             (0xdeadbeef)
  44  #define BCM_6345_OHCI0_BASE            (0xfffe2100)
  45  #define BCM_6345_OHCI_PRIV_BASE                (0xfffe2200)
  46  #define BCM_6345_USBH_PRIV_BASE                (0xdeadbeef)
  47 @@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
  48  #define BCM_6348_USBH_PRIV_BASE                (0xdeadbeef)
  49  #define BCM_6348_MPI_BASE              (0xfffe2000)
  50  #define BCM_6348_PCMCIA_BASE           (0xfffe2054)
  51 +#define BCM_6348_PCIE_BASE             (0xdeadbeef)
  52  #define BCM_6348_SDRAM_REGS_BASE       (0xfffe2300)
  53  #define BCM_6348_M2M_BASE              (0xfffe2800)
  54  #define BCM_6348_DSL_BASE              (0xfffe3000)
  55 @@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
  56  #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
  57  #define BCM_6358_MPI_BASE              (0xfffe1000)
  58  #define BCM_6358_PCMCIA_BASE           (0xfffe1054)
  59 +#define BCM_6358_PCIE_BASE             (0xdeadbeef)
  60  #define BCM_6358_SDRAM_REGS_BASE       (0xfffe2300)
  61  #define BCM_6358_M2M_BASE              (0xdeadbeef)
  62  #define BCM_6358_DSL_BASE              (0xfffe3000)
  63 @@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
  64  #define BCM_6368_USBH_PRIV_BASE                (0xb0001700)
  65  #define BCM_6368_MPI_BASE              (0xb0001000)
  66  #define BCM_6368_PCMCIA_BASE           (0xb0001054)
  67 +#define BCM_6368_PCIE_BASE             (0xdeadbeef)
  68  #define BCM_6368_SDRAM_REGS_BASE       (0xdeadbeef)
  69  #define BCM_6368_M2M_BASE              (0xdeadbeef)
  70  #define BCM_6368_DSL_BASE              (0xdeadbeef)
  71 @@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
  72         __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
  73         __GEN_RSET_BASE(__cpu, MPI)                                     \
  74         __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
  75 +       __GEN_RSET_BASE(__cpu, PCIE)                                    \
  76         __GEN_RSET_BASE(__cpu, DSL)                                     \
  77         __GEN_RSET_BASE(__cpu, ENET0)                                   \
  78         __GEN_RSET_BASE(__cpu, ENET1)                                   \
  79 @@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
  80         [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
  81         [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
  82         [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
  83 +       [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
  84         [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
  85         [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
  86         [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
  87 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  88 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  89 @@ -40,6 +40,10 @@
  90  #define BCM_CB_MEM_END_PA              (BCM_CB_MEM_BASE_PA +           \
  91                                         BCM_CB_MEM_SIZE - 1)
  92
  93 +#define BCM_PCIE_MEM_BASE_PA           0x10f00000
  94 +#define BCM_PCIE_MEM_SIZE              (16 * 1024 * 1024)
  95 +#define BCM_PCIE_MEM_END_PA            (BCM_PCIE_MEM_BASE_PA +         \
  96 +                                       BCM_PCIE_MEM_SIZE - 1)
  97
  98  /*
  99   * Internal registers are accessed through KSEG3
 100 @@ -85,6 +89,8 @@
 101  #define bcm_mpi_writel(v, o)   bcm_rset_writel(RSET_MPI, (v), (o))
 102  #define bcm_pcmcia_readl(o)    bcm_rset_readl(RSET_PCMCIA, (o))
 103  #define bcm_pcmcia_writel(v, o)        bcm_rset_writel(RSET_PCMCIA, (v), (o))
 104 +#define bcm_pcie_readl(o)      bcm_rset_readl(RSET_PCIE, (o))
 105 +#define bcm_pcie_writel(v, o)  bcm_rset_writel(RSET_PCIE, (v), (o))
 106  #define bcm_sdram_readl(o)     bcm_rset_readl(RSET_SDRAM, (o))
 107  #define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
 108  #define bcm_memc_readl(o)      bcm_rset_readl(RSET_MEMC, (o))
 109 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 110 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 111 @@ -1170,6 +1170,9 @@
 112  /*************************************************************************
 113   * _REG relative to RSET_MISC
 114   *************************************************************************/
 115 +#define MISC_SERDES_CTRL_REG           0x0
 116 +#define SERDES_PCIE_EN                 (1 << 0)
 117 +#define SERDES_PCIE_EXD_EN             (1 << 15)
 118
 119  #define MISC_STRAPBUS_6328_REG         0x240
 120  #define STRAPBUS_6328_FCVO_SHIFT       7
 121 @@ -1177,4 +1180,55 @@
 122  #define STRAPBUS_6328_BOOT_SEL_SERIAL  (1 << 28)
 123  #define STRAPBUS_6328_BOOT_SEL_NAND    (0 << 28)
 124
 125 +/*************************************************************************
 126 + * _REG relative to RSET_PCIE
 127 + *************************************************************************/
 128 +
 129 +#define PCIE_CONFIG2_REG               0x408
 130 +#define CONFIG2_BAR1_SIZE_EN           1
 131 +#define CONFIG2_BAR1_SIZE_MASK         0xf
 132 +
 133 +#define PCIE_IDVAL3_REG                        0x43c
 134 +#define IDVAL3_CLASS_CODE_MASK         0xffffff
 135 +#define IDVAL3_SUBCLASS_SHIFT          8
 136 +#define IDVAL3_CLASS_SHIFT             16
 137 +
 138 +#define PCIE_DLSTATUS_REG              0x1048
 139 +#define DLSTATUS_PHYLINKUP             (1 << 13)
 140 +
 141 +#define PCIE_BRIDGE_OPT1_REG           0x2820
 142 +#define OPT1_RD_BE_OPT_EN              (1 << 7)
 143 +#define OPT1_RD_REPLY_BE_FIX_EN                (1 << 9)
 144 +#define OPT1_PCIE_BRIDGE_HOLE_DET_EN   (1 << 11)
 145 +#define OPT1_L1_INT_STATUS_MASK_POL    (1 << 12)
 146 +
 147 +#define PCIE_BRIDGE_OPT2_REG           0x2824
 148 +#define OPT2_UBUS_UR_DECODE_DIS                (1 << 2)
 149 +#define OPT2_TX_CREDIT_CHK_EN          (1 << 4)
 150 +#define OPT2_CFG_TYPE1_BD_SEL          (1 << 7)
 151 +#define OPT2_CFG_TYPE1_BUS_NO_SHIFT    16
 152 +#define OPT2_CFG_TYPE1_BUS_NO_MASK     (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
 153 +
 154 +#define PCIE_BRIDGE_BAR0_BASEMASK_REG  0x2828
 155 +#define PCIE_BRIDGE_BAR1_BASEMASK_REG  0x2830
 156 +#define BASEMASK_REMAP_EN              (1 << 0)
 157 +#define BASEMASK_SWAP_EN               (1 << 1)
 158 +#define BASEMASK_MASK_SHIFT            4
 159 +#define BASEMASK_MASK_MASK             (0xfff << BASEMASK_MASK_SHIFT)
 160 +#define BASEMASK_BASE_SHIFT            20
 161 +#define BASEMASK_BASE_MASK             (0xfff << BASEMASK_BASE_SHIFT)
 162 +
 163 +#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
 164 +#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
 165 +#define REBASE_ADDR_BASE_SHIFT         20
 166 +#define REBASE_ADDR_BASE_MASK          (0xfff << REBASE_ADDR_BASE_SHIFT)
 167 +
 168 +#define PCIE_BRIDGE_RC_INT_MASK_REG    0x2854
 169 +#define PCIE_RC_INT_A                  (1 << 0)
 170 +#define PCIE_RC_INT_B                  (1 << 1)
 171 +#define PCIE_RC_INT_C                  (1 << 2)
 172 +#define PCIE_RC_INT_D                  (1 << 3)
 173 +
 174 +#define PCIE_DEVICE_OFFSET             0x8000
 175 +
 176  #endif /* BCM63XX_REGS_H_ */