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bcm63xx: add support for the HSSPI controller
[openwrt/openwrt.git] / target / linux / brcm63xx / patches-3.3 / 419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch
1 From 2982127b8a0127667cb5354e03987cd3baa84b8c Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sat, 12 Nov 2011 12:19:55 +0100
4 Subject: [PATCH 54/79] SPI: MIPS: BCM63XX: Add HS SPI driver
5
6 Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
7
8 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
9 ---
10 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 +
11 .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h | 3 +
12 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 47 ++
13 drivers/spi/Kconfig | 7 +
14 drivers/spi/Makefile | 1 +
15 drivers/spi/spi-bcm63xx-hsspi.c | 502 ++++++++++++++++++++
16 6 files changed, 578 insertions(+)
17 create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
18
19 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
20 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
21 @@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
22 RSET_UART1,
23 RSET_GPIO,
24 RSET_SPI,
25 + RSET_HSSPI,
26 RSET_UDC0,
27 RSET_OHCI0,
28 RSET_OHCI_PRIV,
29 @@ -161,6 +162,7 @@ enum bcm63xx_regs_set {
30 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
31 #define RSET_ENETSW_SIZE 65536
32 #define RSET_UART_SIZE 24
33 +#define RSET_HSSPI_SIZE 2048
34 #define RSET_UDC_SIZE 256
35 #define RSET_OHCI_SIZE 256
36 #define RSET_EHCI_SIZE 256
37 @@ -184,6 +186,7 @@ enum bcm63xx_regs_set {
38 #define BCM_6328_UART1_BASE (0xb0000120)
39 #define BCM_6328_GPIO_BASE (0xb0000080)
40 #define BCM_6328_SPI_BASE (0xdeadbeef)
41 +#define BCM_6328_HSSPI_BASE (0xb0001000)
42 #define BCM_6328_UDC0_BASE (0xdeadbeef)
43 #define BCM_6328_USBDMA_BASE (0xdeadbeef)
44 #define BCM_6328_OHCI0_BASE (0xdeadbeef)
45 @@ -229,6 +232,7 @@ enum bcm63xx_regs_set {
46 #define BCM_6338_UART1_BASE (0xdeadbeef)
47 #define BCM_6338_GPIO_BASE (0xfffe0400)
48 #define BCM_6338_SPI_BASE (0xfffe0c00)
49 +#define BCM_6338_HSSPI_BASE (0xdeadbeef)
50 #define BCM_6338_UDC0_BASE (0xdeadbeef)
51 #define BCM_6338_USBDMA_BASE (0xfffe2400)
52 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
53 @@ -275,6 +279,7 @@ enum bcm63xx_regs_set {
54 #define BCM_6345_UART1_BASE (0xdeadbeef)
55 #define BCM_6345_GPIO_BASE (0xfffe0400)
56 #define BCM_6345_SPI_BASE (0xdeadbeef)
57 +#define BCM_6345_HSSPI_BASE (0xdeadbeef)
58 #define BCM_6345_UDC0_BASE (0xdeadbeef)
59 #define BCM_6345_USBDMA_BASE (0xfffe2800)
60 #define BCM_6345_ENET0_BASE (0xfffe1800)
61 @@ -320,6 +325,7 @@ enum bcm63xx_regs_set {
62 #define BCM_6348_UART1_BASE (0xdeadbeef)
63 #define BCM_6348_GPIO_BASE (0xfffe0400)
64 #define BCM_6348_SPI_BASE (0xfffe0c00)
65 +#define BCM_6348_HSSPI_BASE (0xdeadbeef)
66 #define BCM_6348_UDC0_BASE (0xfffe1000)
67 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
68 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
69 @@ -363,6 +369,7 @@ enum bcm63xx_regs_set {
70 #define BCM_6358_UART1_BASE (0xfffe0120)
71 #define BCM_6358_GPIO_BASE (0xfffe0080)
72 #define BCM_6358_SPI_BASE (0xfffe0800)
73 +#define BCM_6358_HSSPI_BASE (0xdeadbeef)
74 #define BCM_6358_UDC0_BASE (0xfffe0800)
75 #define BCM_6358_OHCI0_BASE (0xfffe1400)
76 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
77 @@ -407,6 +414,7 @@ enum bcm63xx_regs_set {
78 #define BCM_6368_UART1_BASE (0xb0000120)
79 #define BCM_6368_GPIO_BASE (0xb0000080)
80 #define BCM_6368_SPI_BASE (0xb0000800)
81 +#define BCM_6368_HSSPI_BASE (0xdeadbeef)
82 #define BCM_6368_UDC0_BASE (0xdeadbeef)
83 #define BCM_6368_OHCI0_BASE (0xb0001600)
84 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
85 @@ -456,6 +464,7 @@ extern const unsigned long *bcm63xx_regs
86 __GEN_RSET_BASE(__cpu, UART1) \
87 __GEN_RSET_BASE(__cpu, GPIO) \
88 __GEN_RSET_BASE(__cpu, SPI) \
89 + __GEN_RSET_BASE(__cpu, HSSPI) \
90 __GEN_RSET_BASE(__cpu, UDC0) \
91 __GEN_RSET_BASE(__cpu, OHCI0) \
92 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
93 @@ -497,6 +506,7 @@ extern const unsigned long *bcm63xx_regs
94 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
95 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
96 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
97 + [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
98 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
99 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
100 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
101 @@ -569,6 +579,7 @@ enum bcm63xx_irq {
102 IRQ_ENET0,
103 IRQ_ENET1,
104 IRQ_ENET_PHY,
105 + IRQ_HSSPI,
106 IRQ_OHCI0,
107 IRQ_EHCI0,
108 IRQ_ENET0_RXDMA,
109 @@ -604,6 +615,7 @@ enum bcm63xx_irq {
110 #define BCM_6328_ENET0_IRQ 0
111 #define BCM_6328_ENET1_IRQ 0
112 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
113 +#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
114 #define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
115 #define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
116 #define BCM_6328_PCMCIA_IRQ 0
117 @@ -642,6 +654,7 @@ enum bcm63xx_irq {
118 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
119 #define BCM_6338_ENET1_IRQ 0
120 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
121 +#define BCM_6338_HSSPI_IRQ 0
122 #define BCM_6338_OHCI0_IRQ 0
123 #define BCM_6338_EHCI0_IRQ 0
124 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
125 @@ -673,6 +686,7 @@ enum bcm63xx_irq {
126 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
127 #define BCM_6345_ENET1_IRQ 0
128 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
129 +#define BCM_6345_HSSPI_IRQ 0
130 #define BCM_6345_OHCI0_IRQ 0
131 #define BCM_6345_EHCI0_IRQ 0
132 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
133 @@ -704,6 +718,7 @@ enum bcm63xx_irq {
134 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
135 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
136 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
137 +#define BCM_6348_HSSPI_IRQ 0
138 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
139 #define BCM_6348_EHCI0_IRQ 0
140 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
141 @@ -735,6 +750,7 @@ enum bcm63xx_irq {
142 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
143 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
144 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
145 +#define BCM_6358_HSSPI_IRQ 0
146 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
147 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
148 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
149 @@ -775,6 +791,7 @@ enum bcm63xx_irq {
150 #define BCM_6368_ENET0_IRQ 0
151 #define BCM_6368_ENET1_IRQ 0
152 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
153 +#define BCM_6368_HSSPI_IRQ 0
154 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
155 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
156 #define BCM_6368_PCMCIA_IRQ 0
157 @@ -815,6 +832,7 @@ extern const int *bcm63xx_irqs;
158 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
159 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
160 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
161 + [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
162 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
163 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
164 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
165 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
166 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
167 @@ -23,4 +23,7 @@ struct bcm63xx_hsspi_pdata {
168 #define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
169 #define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
170
171 +#define HS_SPI_CLOCK_DEF 40000000
172 +#define HS_SPI_BUFFER_LEN 512
173 +
174 #endif /* BCM63XX_DEV_HSSPI_H */
175 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
176 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
177 @@ -1276,4 +1276,51 @@
178
179 #define PCIE_DEVICE_OFFSET 0x8000
180
181 +/*************************************************************************
182 + * _REG relative to RSET_HSSPI
183 + *************************************************************************/
184 +
185 +#define HSSPI_GLOBAL_CTRL_REG 0x0
186 +#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
187 +#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
188 +
189 +#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
190 +
191 +#define HSSPI_INT_STATUS_REG 0x8
192 +#define HSSPI_INT_STATUS_MASKED_REG 0xc
193 +#define HSSPI_INT_MASK_REG 0x10
194 +
195 +#define HSSPI_PING0_CMD_DONE BIT(0)
196 +
197 +#define HSSPI_INT_CLEAR_ALL 0xff001f1f
198 +
199 +#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
200 +#define PINGPONG_CMD_COMMAND_MASK 0xf
201 +#define PINGPONG_COMMAND_NOOP 0
202 +#define PINGPONG_COMMAND_START_NOW 1
203 +#define PINGPONG_COMMAND_START_TRIGGER 2
204 +#define PINGPONG_COMMAND_HALT 3
205 +#define PINGPONG_COMMAND_FLUSH 4
206 +#define PINGPONG_CMD_PROFILE_SHIFT 8
207 +#define PINGPONG_CMD_SS_SHIFT 12
208 +
209 +#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
210 +
211 +#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
212 +#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
213 +
214 +#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
215 +#define SIGNAL_CTRL_LATCH_RISING BIT(12)
216 +#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
217 +#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
218 +
219 +#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
220 +#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
221 +#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
222 +#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
223 +#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
224 +#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
225 +
226 +#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
227 +
228 #endif /* BCM63XX_REGS_H_ */
229 --- a/drivers/spi/Kconfig
230 +++ b/drivers/spi/Kconfig
231 @@ -100,6 +100,13 @@ config SPI_BCM63XX
232 help
233 Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
234
235 +config SPI_BCM63XX_HSSPI
236 + tristate "Broadcom BCM63XX HS SPI controller driver"
237 + depends on BCM63XX
238 + help
239 + This enables support for the High Speed SPI controller present on
240 + newer Broadcom BCM63XX SoCs.
241 +
242 config SPI_BITBANG
243 tristate "Utilities for Bitbanging SPI masters"
244 help
245 --- a/drivers/spi/Makefile
246 +++ b/drivers/spi/Makefile
247 @@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
248 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
249 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
250 obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
251 +obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
252 obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
253 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
254 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
255 --- /dev/null
256 +++ b/drivers/spi/spi-bcm63xx-hsspi.c
257 @@ -0,0 +1,502 @@
258 +/*
259 + * Broadcom BCM63XX High Speed SPI Controller driver
260 + *
261 + * Copyright 2000-2010 Broadcom Corporation
262 + * Copyright 2011 Jonas Gorski <jonas.gorski@gmail.com>
263 + *
264 + * Licensed under the GNU/GPL. See COPYING for details.
265 + */
266 +
267 +#include <linux/kernel.h>
268 +#include <linux/init.h>
269 +#include <linux/clk.h>
270 +#include <linux/module.h>
271 +#include <linux/platform_device.h>
272 +#include <linux/delay.h>
273 +#include <linux/dma-mapping.h>
274 +#include <linux/err.h>
275 +#include <linux/interrupt.h>
276 +#include <linux/spi/spi.h>
277 +#include <linux/workqueue.h>
278 +
279 +#include <bcm63xx_regs.h>
280 +#include <bcm63xx_dev_hsspi.h>
281 +
282 +
283 +#define PFX KBUILD_MODNAME
284 +
285 +struct bcm63xx_hsspi {
286 + spinlock_t lock;
287 + int irq;
288 + u8 stopping;
289 +
290 + struct list_head queue;
291 + struct workqueue_struct *workqueue;
292 + struct work_struct ws;
293 + struct completion done;
294 +
295 + struct spi_transfer *curr_trans;
296 +
297 + struct platform_device *pdev;
298 + void __iomem *regs;
299 + struct clk *clk;
300 +
301 + /* Platform data */
302 + u32 speed_hz;
303 +
304 + /* data iomem */
305 + u8 __iomem *fifo;
306 +
307 +
308 +};
309 +
310 +static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
311 + int profile)
312 +{
313 + int clock;
314 +
315 + clock = bs->speed_hz / hz;
316 + if (bs->speed_hz % HS_SPI_CLOCK_DEF)
317 + clock++;
318 +
319 + clock = 2048 / clock;
320 + if (2048 % clock)
321 + clock++;
322 +
323 + bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | clock,
324 + HSSPI_PROFILE_CLK_CTRL_REG(profile));
325 +}
326 +
327 +static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
328 + struct spi_transfer *t1,
329 + struct spi_transfer *t2)
330 +{
331 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
332 + u8 chip_select = spi->chip_select;
333 + u16 opcode = 0;
334 + int prepend_size = 0;
335 +
336 + init_completion(&bs->done);
337 + bs->curr_trans = t2 ? t2 : t1;
338 + bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
339 +
340 + BUG_ON(t2 && !t1->tx_buf && t1->rx_buf && t2->tx_buf && !t2->rx_buf);
341 +
342 + if (t2 && !t2->tx_buf)
343 + prepend_size = t1->len;
344 +
345 + bcm_hsspi_writel(prepend_size<<MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
346 + 2<<MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
347 + 2<<MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
348 + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
349 +
350 + if (t1->rx_buf && t1->tx_buf)
351 + opcode = HSSPI_OP_READ_WRITE;
352 + else if (t1->rx_buf || (t2 && t2->rx_buf))
353 + opcode = HSSPI_OP_READ;
354 + else if (t1->tx_buf)
355 + opcode = HSSPI_OP_WRITE;
356 +
357 + BUG_ON(opcode == 0);
358 +
359 + if (opcode == HSSPI_OP_READ && t2)
360 + opcode |= t2->len;
361 + else
362 + opcode |= t1->len;
363 +
364 + if (t1->tx_buf) {
365 + memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
366 + if (t2 && t2->tx_buf) {
367 + memcpy_toio(bs->fifo + 2 + t1->len,
368 + t2->tx_buf, t2->len);
369 + opcode += t2->len;
370 + }
371 + }
372 +
373 + memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
374 +
375 + /* enable interrupt */
376 + bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
377 +
378 + /* start the transfer */
379 + bcm_hsspi_writel(chip_select << PINGPONG_CMD_SS_SHIFT |
380 + chip_select << PINGPONG_CMD_PROFILE_SHIFT |
381 + PINGPONG_COMMAND_START_NOW,
382 + HSSPI_PINGPONG_COMMAND_REG(0));
383 +
384 + wait_for_completion(&bs->done);
385 + return t1->len + (t2 ? t2->len : 0);
386 +}
387 +static int bcm63xx_hsspi_setup(struct spi_device *spi)
388 +{
389 + struct bcm63xx_hsspi *bs;
390 + u32 reg;
391 + bs = spi_master_get_devdata(spi->master);
392 +
393 + if (bs->stopping)
394 + return -ESHUTDOWN;
395 +
396 + if (!spi->bits_per_word)
397 + spi->bits_per_word = 8;
398 +
399 + if (spi->bits_per_word != 8)
400 + return -EINVAL;
401 +
402 + if (spi->max_speed_hz == 0)
403 + return -EINVAL;
404 +
405 + reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
406 + reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
407 +
408 + if (spi->mode & SPI_CPHA)
409 + reg |= SIGNAL_CTRL_LAUNCH_RISING;
410 + else
411 + reg |= SIGNAL_CTRL_LATCH_RISING;
412 +
413 + bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
414 +
415 + return 0;
416 +}
417 +
418 +
419 +static int bcm63xx_hsspi_transfer(struct spi_device *spi,
420 + struct spi_message *msg)
421 +{
422 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
423 + struct spi_transfer *t, *prev = NULL;
424 +
425 + if (unlikely(list_empty(&msg->transfers)))
426 + return -EINVAL;
427 +
428 + if (bs->stopping)
429 + return -ESHUTDOWN;
430 +
431 + list_for_each_entry(t, &msg->transfers, transfer_list) {
432 + /* check transfer parameters */
433 + if (!t->tx_buf && !t->rx_buf)
434 + return -EINVAL;
435 +
436 + if (t->speed_hz == 0)
437 + t->speed_hz = spi->max_speed_hz;
438 +
439 + if (t->speed_hz > spi->max_speed_hz)
440 + return -EINVAL;
441 +
442 + if (t->len > HS_SPI_BUFFER_LEN)
443 + return -EINVAL;
444 +
445 + /* reject if we have to combine two tx transfers and their
446 + * combined length is bigger than the buffer
447 + */
448 + if (prev && !prev->cs_change && !t->cs_change && prev->tx_buf &&
449 + t->tx_buf && (prev->len + t->len) > HS_SPI_BUFFER_LEN)
450 + return -EINVAL;
451 +
452 + prev = t;
453 + }
454 +
455 +
456 + msg->actual_length = 0;
457 +
458 +#if 0
459 + /* disable interrupts for the SPI controller
460 + using spin_lock_irqsave would disable all interrupts */
461 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
462 +#endif
463 + spin_lock(&bs->lock);
464 + list_add_tail(&msg->queue, &bs->queue);
465 + queue_work(bs->workqueue, &bs->ws);
466 + spin_unlock(&bs->lock);
467 +
468 +#if 0
469 + bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
470 +#endif
471 + return 0;
472 +}
473 +
474 +static void bcm63xx_hsspi_do_work(struct work_struct *work)
475 +{
476 + struct bcm63xx_hsspi *bs = container_of(work, struct bcm63xx_hsspi,
477 + ws);
478 + struct spi_message *msg;
479 + struct spi_transfer *prev = NULL;
480 + struct spi_transfer *t;
481 + u32 reg;
482 +
483 + int len = 0;
484 +
485 + spin_lock(&bs->lock);
486 + msg = list_entry(bs->queue.next, struct spi_message, queue);
487 + list_del(&msg->queue);
488 + spin_unlock(&bs->lock);
489 +
490 + if (bs->stopping) {
491 + msg->status = -ESHUTDOWN;
492 + goto out;
493 + }
494 +
495 + /* setup clock polarity */
496 + reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
497 + reg &= ~GLOBAL_CTRL_CLK_POLARITY;
498 +
499 + if (msg->spi->mode & SPI_CPOL)
500 + reg |= GLOBAL_CTRL_CLK_POLARITY;
501 +
502 + bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
503 +
504 + list_for_each_entry(t, &msg->transfers, transfer_list) {
505 + /*
506 + * This controller does not support keeping the chip select
507 + * active between transfers.
508 + * This logic currently supports combining:
509 + * write then read with no cs_change (e.g. m25p80 RDSR)
510 + * write then write with no cs_change (e.g. m25p80 PP)
511 + */
512 + if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
513 + /* combine write with following transfer */
514 + len += bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
515 + prev = NULL;
516 + continue;
517 + }
518 +
519 + /* write the previous pending transfer */
520 + if (prev != NULL)
521 + len += bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
522 +
523 + prev = t;
524 + }
525 +
526 + /* do last pending transfer */
527 + if (prev != NULL)
528 + len += bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
529 +
530 + msg->status = 0;
531 + msg->actual_length = len;
532 +out:
533 + msg->complete(msg->context);
534 +}
535 +
536 +static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
537 +{
538 + struct spi_master *master = (struct spi_master *)dev_id;
539 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
540 +
541 + if (bcm_hsspi_readl(HSSPI_INT_STATUS_MASKED_REG) == 0)
542 + return IRQ_NONE;
543 +
544 + bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
545 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
546 +
547 + spin_lock(&bs->lock);
548 +
549 + if (bs->curr_trans && bs->curr_trans->rx_buf)
550 + memcpy_fromio(bs->curr_trans->rx_buf, bs->fifo,
551 + bs->curr_trans->len);
552 +
553 + complete(&bs->done);
554 + spin_unlock(&bs->lock);
555 +
556 + return IRQ_HANDLED;
557 +}
558 +
559 +
560 +static void bcm63xx_hsspi_cleanup(struct spi_device *spi)
561 +{
562 + /* would free spi_controller memory here if any was allocated */
563 +}
564 +
565 +static int __devinit bcm63xx_hsspi_probe(struct platform_device *pdev)
566 +{
567 +
568 + struct spi_master *master;
569 + struct bcm63xx_hsspi *bs;
570 + struct resource *res_mem;
571 + struct device *dev = &pdev->dev;
572 + struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
573 + struct clk *clk;
574 + int irq;
575 + int ret;
576 +
577 + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
578 + if (!res_mem) {
579 + dev_err(dev, "no iomem\n");
580 + return -ENXIO;
581 + }
582 +
583 + irq = platform_get_irq(pdev, 0);
584 + if (irq < 0) {
585 + dev_err(dev, "no irq\n");
586 + return -ENXIO;
587 + }
588 +
589 + clk = clk_get(dev, "hsspi");
590 +
591 + if (IS_ERR(clk)) {
592 + ret = PTR_ERR(clk);
593 + goto out_release;
594 + }
595 + clk_enable(clk);
596 +
597 + master = spi_alloc_master(&pdev->dev, sizeof(*bs));
598 + if (!master) {
599 + ret = -ENOMEM;
600 + goto out_disable_clk;
601 + }
602 +
603 + bs = spi_master_get_devdata(master);
604 + init_completion(&bs->done);
605 + bs->pdev = pdev;
606 + bs->clk = clk;
607 +
608 + bs->regs = devm_request_and_ioremap(dev, res_mem);
609 + if (!bs->regs) {
610 + dev_err(dev, "unable to ioremap regs\n");
611 + ret = -ENOMEM;
612 + goto out_put_master;
613 + }
614 +
615 + master->bus_num = pdata->bus_num;
616 + master->num_chipselect = 8;
617 + master->setup = bcm63xx_hsspi_setup;
618 + master->transfer = bcm63xx_hsspi_transfer;
619 + master->cleanup = bcm63xx_hsspi_cleanup;
620 + master->mode_bits = SPI_CPOL | SPI_CPHA;
621 +
622 + bs->speed_hz = pdata->speed_hz;
623 + bs->fifo = (u8 *)(bs->regs + HSSPI_FIFO_REG(0));
624 +
625 + platform_set_drvdata(pdev, master);
626 +
627 + spin_lock_init(&bs->lock);
628 + INIT_LIST_HEAD(&bs->queue);
629 + INIT_WORK(&bs->ws, bcm63xx_hsspi_do_work);
630 + bs->workqueue = create_singlethread_workqueue(pdev->name);
631 + bs->curr_trans = NULL;
632 +
633 + /* Initialize the hardware */
634 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
635 +
636 + bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
637 + GLOBAL_CTRL_CLK_GATE_SSOFF,
638 + HSSPI_GLOBAL_CTRL_REG);
639 +
640 + ret = request_irq(irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, pdev->name,
641 + master);
642 +
643 + if (ret)
644 + goto out_destroy_workqueue;
645 +
646 + spin_lock(&bs->lock);
647 + bs->irq = irq;
648 + spin_unlock(&bs->lock);
649 +
650 + /* register and we are done */
651 + ret = spi_register_master(master);
652 + if (ret)
653 + goto out_free_irq;
654 +
655 + return 0;
656 +
657 +out_free_irq:
658 + free_irq(bs->irq, master);
659 +out_destroy_workqueue:
660 + flush_workqueue(bs->workqueue);
661 + destroy_workqueue(bs->workqueue);
662 + iounmap(bs->regs);
663 +out_put_master:
664 + spi_master_put(master);
665 +out_disable_clk:
666 + clk_disable(clk);
667 + clk_put(clk);
668 +out_release:
669 + release_mem_region(res_mem->start, resource_size(res_mem));
670 +
671 + return ret;
672 +}
673 +
674 +
675 +static int __exit bcm63xx_hsspi_remove(struct platform_device *pdev)
676 +{
677 + struct spi_master *master = platform_get_drvdata(pdev);
678 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
679 + struct spi_message *msg;
680 +
681 + cancel_work_sync(&bs->ws);
682 +
683 + /* reset the hardware and block queue progress */
684 + bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
685 +
686 + spin_lock(&bs->lock);
687 + /* HW shutdown */
688 + bs->stopping = 1;
689 + spin_unlock(&bs->lock);
690 +
691 +
692 + /* Terminate remaining queued transfers */
693 + list_for_each_entry(msg, &bs->queue, queue) {
694 + msg->status = -ESHUTDOWN;
695 + msg->complete(msg->context);
696 + }
697 +
698 +
699 + free_irq(bs->irq, master);
700 + flush_workqueue(bs->workqueue);
701 + destroy_workqueue(bs->workqueue);
702 +
703 + clk_disable(bs->clk);
704 + clk_put(bs->clk);
705 +
706 + spi_unregister_master(master);
707 + return 0;
708 +}
709 +
710 +#ifdef CONFIG_PM
711 +static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
712 + pm_message_t mesg)
713 +{
714 + struct spi_master *master = platform_get_drvdata(pdev);
715 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
716 +
717 + clk_disable(bs->clk);
718 +
719 + return 0;
720 +}
721 +
722 +static int bcm63xx_hsspi_resume(struct platform_device *pdev)
723 +{
724 + struct spi_master *master = platform_get_drvdata(pdev);
725 + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
726 +
727 + clk_enable(bs->clk);
728 +
729 + return 0;
730 +}
731 +
732 +static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
733 + .suspend = bcm63xx_hsspi_suspend,
734 + .resume = bcm63xx_hsspi_resume,
735 +};
736 +
737 +#define BCM63XX_HSSPI_PM_OPS (&bcm63xx_hsspi_pm_ops)
738 +#else
739 +#define BCM63XX_HSSPI_PM_OPS NULL
740 +#endif
741 +
742 +
743 +
744 +static struct platform_driver bcm63xx_hsspi_driver = {
745 + .driver = {
746 + .name = "bcm63xx-hsspi",
747 + .owner = THIS_MODULE,
748 + .pm = BCM63XX_HSSPI_PM_OPS,
749 + },
750 + .probe = bcm63xx_hsspi_probe,
751 + .remove = __exit_p(bcm63xx_hsspi_remove),
752 +};
753 +
754 +module_platform_driver(bcm63xx_hsspi_driver);
755 +
756 +MODULE_ALIAS("platform:bcm63xx_hsspi");
757 +MODULE_DESCRIPTION("Broadcom BCM63xx HS SPI Controller driver");
758 +MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
759 +MODULE_LICENSE("GPL");
OpenWrt Source Repository