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brcm63xx: remove misleading warning about partial SPI NOR writes
[openwrt/openwrt.git] / target / linux / brcm63xx / patches-4.4 / 000-4.5-31-gpio-generic-factor-into-gpio_chip-struct.patch
1 From 0f4630f3720e7e6e921bf525c8357fea7ef3dbab Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Fri, 4 Dec 2015 14:02:58 +0100
4 Subject: [PATCH] gpio: generic: factor into gpio_chip struct
5
6 The separate struct bgpio_chip has been a pain to handle, both
7 by being confusingly similar in name to struct gpio_chip and
8 for being contained inside a struct so that struct gpio_chip
9 is contained in a struct contained in a struct, making several
10 steps of dereferencing necessary.
11
12 Make things simpler: include the fields directly into
13 <linux/gpio/driver.h>, #ifdef:ed for CONFIG_GENERIC_GPIO, and
14 get rid of the <linux/basic_mmio_gpio.h> altogether. Prefix
15 some of the member variables with bgpio_* and add proper
16 kerneldoc while we're at it.
17
18 Modify all users to handle the change and use a struct
19 gpio_chip directly. And while we're at it: replace all
20 container_of() dereferencing by gpiochip_get_data() and
21 registering the gpio_chip with gpiochip_add_data().
22
23 Cc: arm@kernel.org
24 Cc: Alexander Shiyan <shc_work@mail.ru>
25 Cc: Shawn Guo <shawnguo@kernel.org>
26 Cc: Sascha Hauer <kernel@pengutronix.de>
27 Cc: Kukjin Kim <kgene@kernel.org>
28 Cc: Alexandre Courbot <gnurou@gmail.com>
29 Cc: Brian Norris <computersforpeace@gmail.com>
30 Cc: Florian Fainelli <f.fainelli@gmail.com>
31 Cc: Sudeep Holla <sudeep.holla@arm.com>
32 Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
33 Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
34 Cc: Olof Johansson <olof@lixom.net>
35 Cc: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
36 Cc: Rabin Vincent <rabin@rab.in>
37 Cc: linux-arm-kernel@lists.infradead.org
38 Cc: linux-omap@vger.kernel.org
39 Cc: linux-samsung-soc@vger.kernel.org
40 Cc: bcm-kernel-feedback-list@broadcom.com
41 Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
42 Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
43 Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
44 Acked-by: Tony Lindgren <tony@atomide.com>
45 Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
46 Acked-by: Lee Jones <lee.jones@linaro.org>
47 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
48 ---
49 arch/arm/mach-clps711x/board-autcpu12.c | 2 +-
50 arch/arm/mach-clps711x/board-p720t.c | 2 +-
51 arch/arm/mach-imx/mach-mx21ads.c | 2 +-
52 arch/arm/mach-omap1/board-ams-delta.c | 2 +-
53 arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
54 drivers/gpio/gpio-74xx-mmio.c | 37 ++--
55 drivers/gpio/gpio-brcmstb.c | 80 ++++-----
56 drivers/gpio/gpio-clps711x.c | 28 +--
57 drivers/gpio/gpio-dwapb.c | 92 +++++-----
58 drivers/gpio/gpio-ep93xx.c | 25 +--
59 drivers/gpio/gpio-etraxfs.c | 49 +++---
60 drivers/gpio/gpio-ge.c | 24 +--
61 drivers/gpio/gpio-generic.c | 292 +++++++++++++++-----------------
62 drivers/gpio/gpio-grgpio.c | 73 ++++----
63 drivers/gpio/gpio-moxart.c | 29 ++--
64 drivers/gpio/gpio-mxc.c | 27 ++-
65 drivers/gpio/gpio-mxs.c | 33 ++--
66 drivers/gpio/gpio-sodaville.c | 13 +-
67 drivers/gpio/gpio-xgene-sb.c | 40 ++---
68 drivers/mfd/vexpress-sysreg.c | 8 +-
69 include/linux/basic_mmio_gpio.h | 80 ---------
70 include/linux/gpio/driver.h | 54 ++++++
71 22 files changed, 442 insertions(+), 552 deletions(-)
72 delete mode 100644 include/linux/basic_mmio_gpio.h
73
74 --- a/arch/arm/mach-clps711x/board-autcpu12.c
75 +++ b/arch/arm/mach-clps711x/board-autcpu12.c
76 @@ -31,7 +31,7 @@
77 #include <linux/mtd/partitions.h>
78 #include <linux/mtd/nand-gpio.h>
79 #include <linux/platform_device.h>
80 -#include <linux/basic_mmio_gpio.h>
81 +#include <linux/gpio/driver.h>
82
83 #include <mach/hardware.h>
84 #include <asm/sizes.h>
85 --- a/arch/arm/mach-clps711x/board-p720t.c
86 +++ b/arch/arm/mach-clps711x/board-p720t.c
87 @@ -28,7 +28,7 @@
88 #include <linux/leds.h>
89 #include <linux/sizes.h>
90 #include <linux/backlight.h>
91 -#include <linux/basic_mmio_gpio.h>
92 +#include <linux/gpio/driver.h>
93 #include <linux/platform_device.h>
94 #include <linux/mtd/partitions.h>
95 #include <linux/mtd/nand-gpio.h>
96 --- a/arch/arm/mach-imx/mach-mx21ads.c
97 +++ b/arch/arm/mach-imx/mach-mx21ads.c
98 @@ -17,7 +17,7 @@
99 #include <linux/platform_device.h>
100 #include <linux/mtd/mtd.h>
101 #include <linux/mtd/physmap.h>
102 -#include <linux/basic_mmio_gpio.h>
103 +#include <linux/gpio/driver.h>
104 #include <linux/gpio.h>
105 #include <linux/regulator/fixed.h>
106 #include <linux/regulator/machine.h>
107 --- a/arch/arm/mach-omap1/board-ams-delta.c
108 +++ b/arch/arm/mach-omap1/board-ams-delta.c
109 @@ -11,7 +11,7 @@
110 * it under the terms of the GNU General Public License version 2 as
111 * published by the Free Software Foundation.
112 */
113 -#include <linux/basic_mmio_gpio.h>
114 +#include <linux/gpio/driver.h>
115 #include <linux/gpio.h>
116 #include <linux/kernel.h>
117 #include <linux/init.h>
118 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c
119 +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
120 @@ -29,7 +29,7 @@
121 #include <linux/pwm_backlight.h>
122 #include <linux/dm9000.h>
123 #include <linux/gpio_keys.h>
124 -#include <linux/basic_mmio_gpio.h>
125 +#include <linux/gpio/driver.h>
126 #include <linux/spi/spi.h>
127
128 #include <linux/platform_data/pca953x.h>
129 --- a/drivers/gpio/gpio-74xx-mmio.c
130 +++ b/drivers/gpio/gpio-74xx-mmio.c
131 @@ -10,10 +10,9 @@
132 */
133
134 #include <linux/err.h>
135 -#include <linux/gpio.h>
136 #include <linux/module.h>
137 #include <linux/of_device.h>
138 -#include <linux/basic_mmio_gpio.h>
139 +#include <linux/gpio/driver.h>
140 #include <linux/platform_device.h>
141
142 #define MMIO_74XX_DIR_IN (0 << 8)
143 @@ -21,7 +20,7 @@
144 #define MMIO_74XX_BIT_CNT(x) ((x) & 0xff)
145
146 struct mmio_74xx_gpio_priv {
147 - struct bgpio_chip bgc;
148 + struct gpio_chip gc;
149 unsigned flags;
150 };
151
152 @@ -78,30 +77,23 @@ static const struct of_device_id mmio_74
153 };
154 MODULE_DEVICE_TABLE(of, mmio_74xx_gpio_ids);
155
156 -static inline struct mmio_74xx_gpio_priv *to_74xx_gpio(struct gpio_chip *gc)
157 -{
158 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
159 -
160 - return container_of(bgc, struct mmio_74xx_gpio_priv, bgc);
161 -}
162 -
163 static int mmio_74xx_get_direction(struct gpio_chip *gc, unsigned offset)
164 {
165 - struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
166 + struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
167
168 - return (priv->flags & MMIO_74XX_DIR_OUT) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
169 + return !(priv->flags & MMIO_74XX_DIR_OUT);
170 }
171
172 static int mmio_74xx_dir_in(struct gpio_chip *gc, unsigned int gpio)
173 {
174 - struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
175 + struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
176
177 return (priv->flags & MMIO_74XX_DIR_OUT) ? -ENOTSUPP : 0;
178 }
179
180 static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
181 {
182 - struct mmio_74xx_gpio_priv *priv = to_74xx_gpio(gc);
183 + struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
184
185 if (priv->flags & MMIO_74XX_DIR_OUT) {
186 gc->set(gc, gpio, val);
187 @@ -134,28 +126,29 @@ static int mmio_74xx_gpio_probe(struct p
188
189 priv->flags = (uintptr_t) of_id->data;
190
191 - err = bgpio_init(&priv->bgc, &pdev->dev,
192 + err = bgpio_init(&priv->gc, &pdev->dev,
193 DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8),
194 dat, NULL, NULL, NULL, NULL, 0);
195 if (err)
196 return err;
197
198 - priv->bgc.gc.direction_input = mmio_74xx_dir_in;
199 - priv->bgc.gc.direction_output = mmio_74xx_dir_out;
200 - priv->bgc.gc.get_direction = mmio_74xx_get_direction;
201 - priv->bgc.gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
202 - priv->bgc.gc.owner = THIS_MODULE;
203 + priv->gc.direction_input = mmio_74xx_dir_in;
204 + priv->gc.direction_output = mmio_74xx_dir_out;
205 + priv->gc.get_direction = mmio_74xx_get_direction;
206 + priv->gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
207 + priv->gc.owner = THIS_MODULE;
208
209 platform_set_drvdata(pdev, priv);
210
211 - return gpiochip_add(&priv->bgc.gc);
212 + return gpiochip_add_data(&priv->gc, priv);
213 }
214
215 static int mmio_74xx_gpio_remove(struct platform_device *pdev)
216 {
217 struct mmio_74xx_gpio_priv *priv = platform_get_drvdata(pdev);
218
219 - return bgpio_remove(&priv->bgc);
220 + gpiochip_remove(&priv->gc);
221 + return 0;
222 }
223
224 static struct platform_driver mmio_74xx_gpio_driver = {
225 --- a/drivers/gpio/gpio-brcmstb.c
226 +++ b/drivers/gpio/gpio-brcmstb.c
227 @@ -16,7 +16,6 @@
228 #include <linux/of_device.h>
229 #include <linux/of_irq.h>
230 #include <linux/module.h>
231 -#include <linux/basic_mmio_gpio.h>
232 #include <linux/irqdomain.h>
233 #include <linux/irqchip/chained_irq.h>
234 #include <linux/interrupt.h>
235 @@ -35,7 +34,7 @@
236 struct brcmstb_gpio_bank {
237 struct list_head node;
238 int id;
239 - struct bgpio_chip bgc;
240 + struct gpio_chip gc;
241 struct brcmstb_gpio_priv *parent_priv;
242 u32 width;
243 struct irq_chip irq_chip;
244 @@ -57,37 +56,30 @@ struct brcmstb_gpio_priv {
245 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
246 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
247
248 -static inline struct brcmstb_gpio_bank *
249 -brcmstb_gpio_gc_to_bank(struct gpio_chip *gc)
250 -{
251 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
252 - return container_of(bgc, struct brcmstb_gpio_bank, bgc);
253 -}
254 -
255 static inline struct brcmstb_gpio_priv *
256 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
257 {
258 - struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
259 + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
260 return bank->parent_priv;
261 }
262
263 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
264 unsigned int offset, bool enable)
265 {
266 - struct bgpio_chip *bgc = &bank->bgc;
267 + struct gpio_chip *gc = &bank->gc;
268 struct brcmstb_gpio_priv *priv = bank->parent_priv;
269 - u32 mask = bgc->pin2mask(bgc, offset);
270 + u32 mask = gc->pin2mask(gc, offset);
271 u32 imask;
272 unsigned long flags;
273
274 - spin_lock_irqsave(&bgc->lock, flags);
275 - imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id));
276 + spin_lock_irqsave(&gc->bgpio_lock, flags);
277 + imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
278 if (enable)
279 imask |= mask;
280 else
281 imask &= ~mask;
282 - bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
283 - spin_unlock_irqrestore(&bgc->lock, flags);
284 + gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
285 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
286 }
287
288 /* -------------------- IRQ chip functions -------------------- */
289 @@ -95,7 +87,7 @@ static void brcmstb_gpio_set_imask(struc
290 static void brcmstb_gpio_irq_mask(struct irq_data *d)
291 {
292 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
293 - struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
294 + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
295
296 brcmstb_gpio_set_imask(bank, d->hwirq, false);
297 }
298 @@ -103,7 +95,7 @@ static void brcmstb_gpio_irq_mask(struct
299 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
300 {
301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
302 - struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
303 + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
304
305 brcmstb_gpio_set_imask(bank, d->hwirq, true);
306 }
307 @@ -111,7 +103,7 @@ static void brcmstb_gpio_irq_unmask(stru
308 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
309 {
310 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
311 - struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
312 + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
313 struct brcmstb_gpio_priv *priv = bank->parent_priv;
314 u32 mask = BIT(d->hwirq);
315 u32 edge_insensitive, iedge_insensitive;
316 @@ -149,23 +141,23 @@ static int brcmstb_gpio_irq_set_type(str
317 return -EINVAL;
318 }
319
320 - spin_lock_irqsave(&bank->bgc.lock, flags);
321 + spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
322
323 - iedge_config = bank->bgc.read_reg(priv->reg_base +
324 + iedge_config = bank->gc.read_reg(priv->reg_base +
325 GIO_EC(bank->id)) & ~mask;
326 - iedge_insensitive = bank->bgc.read_reg(priv->reg_base +
327 + iedge_insensitive = bank->gc.read_reg(priv->reg_base +
328 GIO_EI(bank->id)) & ~mask;
329 - ilevel = bank->bgc.read_reg(priv->reg_base +
330 + ilevel = bank->gc.read_reg(priv->reg_base +
331 GIO_LEVEL(bank->id)) & ~mask;
332
333 - bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id),
334 + bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
335 iedge_config | edge_config);
336 - bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id),
337 + bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
338 iedge_insensitive | edge_insensitive);
339 - bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
340 + bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
341 ilevel | level);
342
343 - spin_unlock_irqrestore(&bank->bgc.lock, flags);
344 + spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
345 return 0;
346 }
347
348 @@ -210,29 +202,29 @@ static irqreturn_t brcmstb_gpio_wake_irq
349 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
350 {
351 struct brcmstb_gpio_priv *priv = bank->parent_priv;
352 - struct irq_domain *irq_domain = bank->bgc.gc.irqdomain;
353 + struct irq_domain *irq_domain = bank->gc.irqdomain;
354 void __iomem *reg_base = priv->reg_base;
355 unsigned long status;
356 unsigned long flags;
357
358 - spin_lock_irqsave(&bank->bgc.lock, flags);
359 - while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) &
360 - bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) {
361 + spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
362 + while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
363 + bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
364 int bit;
365
366 for_each_set_bit(bit, &status, 32) {
367 - u32 stat = bank->bgc.read_reg(reg_base +
368 + u32 stat = bank->gc.read_reg(reg_base +
369 GIO_STAT(bank->id));
370 if (bit >= bank->width)
371 dev_warn(&priv->pdev->dev,
372 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
373 bank->id, bit);
374 - bank->bgc.write_reg(reg_base + GIO_STAT(bank->id),
375 + bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
376 stat | BIT(bit));
377 generic_handle_irq(irq_find_mapping(irq_domain, bit));
378 }
379 }
380 - spin_unlock_irqrestore(&bank->bgc.lock, flags);
381 + spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
382 }
383
384 /* Each UPG GIO block has one IRQ for all banks */
385 @@ -303,9 +295,7 @@ static int brcmstb_gpio_remove(struct pl
386 */
387 list_for_each(pos, &priv->bank_list) {
388 bank = list_entry(pos, struct brcmstb_gpio_bank, node);
389 - ret = bgpio_remove(&bank->bgc);
390 - if (ret)
391 - dev_err(&pdev->dev, "gpiochip_remove fail in cleanup\n");
392 + gpiochip_remove(&bank->gc);
393 }
394 if (priv->reboot_notifier.notifier_call) {
395 ret = unregister_reboot_notifier(&priv->reboot_notifier);
396 @@ -320,7 +310,7 @@ static int brcmstb_gpio_of_xlate(struct
397 const struct of_phandle_args *gpiospec, u32 *flags)
398 {
399 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
400 - struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
401 + struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
402 int offset;
403
404 if (gc->of_gpio_n_cells != 2) {
405 @@ -398,9 +388,9 @@ static int brcmstb_gpio_irq_setup(struct
406 if (priv->can_wake)
407 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
408
409 - gpiochip_irqchip_add(&bank->bgc.gc, &bank->irq_chip, 0,
410 + gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
411 handle_simple_irq, IRQ_TYPE_NONE);
412 - gpiochip_set_chained_irqchip(&bank->bgc.gc, &bank->irq_chip,
413 + gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
414 priv->parent_irq, brcmstb_gpio_irq_handler);
415
416 return 0;
417 @@ -451,7 +441,6 @@ static int brcmstb_gpio_probe(struct pla
418 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
419 bank_width) {
420 struct brcmstb_gpio_bank *bank;
421 - struct bgpio_chip *bgc;
422 struct gpio_chip *gc;
423
424 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
425 @@ -473,8 +462,8 @@ static int brcmstb_gpio_probe(struct pla
426 * Regs are 4 bytes wide, have data reg, no set/clear regs,
427 * and direction bits have 0 = output and 1 = input
428 */
429 - bgc = &bank->bgc;
430 - err = bgpio_init(bgc, dev, 4,
431 + gc = &bank->gc;
432 + err = bgpio_init(gc, dev, 4,
433 reg_base + GIO_DATA(bank->id),
434 NULL, NULL, NULL,
435 reg_base + GIO_IODIR(bank->id), 0);
436 @@ -483,7 +472,6 @@ static int brcmstb_gpio_probe(struct pla
437 goto fail;
438 }
439
440 - gc = &bgc->gc;
441 gc->of_node = np;
442 gc->owner = THIS_MODULE;
443 gc->label = np->full_name;
444 @@ -497,9 +485,9 @@ static int brcmstb_gpio_probe(struct pla
445 * Mask all interrupts by default, since wakeup interrupts may
446 * be retained from S5 cold boot
447 */
448 - bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0);
449 + gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
450
451 - err = gpiochip_add(gc);
452 + err = gpiochip_add_data(gc, bank);
453 if (err) {
454 dev_err(dev, "Could not add gpiochip for bank %d\n",
455 bank->id);
456 --- a/drivers/gpio/gpio-clps711x.c
457 +++ b/drivers/gpio/gpio-clps711x.c
458 @@ -10,24 +10,23 @@
459 */
460
461 #include <linux/err.h>
462 -#include <linux/gpio.h>
463 #include <linux/module.h>
464 -#include <linux/basic_mmio_gpio.h>
465 +#include <linux/gpio/driver.h>
466 #include <linux/platform_device.h>
467
468 static int clps711x_gpio_probe(struct platform_device *pdev)
469 {
470 struct device_node *np = pdev->dev.of_node;
471 void __iomem *dat, *dir;
472 - struct bgpio_chip *bgc;
473 + struct gpio_chip *gc;
474 struct resource *res;
475 int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id;
476
477 if ((id < 0) || (id > 4))
478 return -ENODEV;
479
480 - bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
481 - if (!bgc)
482 + gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
483 + if (!gc)
484 return -ENOMEM;
485
486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487 @@ -43,11 +42,11 @@ static int clps711x_gpio_probe(struct pl
488 switch (id) {
489 case 3:
490 /* PORTD is inverted logic for direction register */
491 - err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
492 + err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
493 NULL, dir, 0);
494 break;
495 default:
496 - err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
497 + err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
498 dir, NULL, 0);
499 break;
500 }
501 @@ -58,24 +57,25 @@ static int clps711x_gpio_probe(struct pl
502 switch (id) {
503 case 4:
504 /* PORTE is 3 lines only */
505 - bgc->gc.ngpio = 3;
506 + gc->ngpio = 3;
507 break;
508 default:
509 break;
510 }
511
512 - bgc->gc.base = id * 8;
513 - bgc->gc.owner = THIS_MODULE;
514 - platform_set_drvdata(pdev, bgc);
515 + gc->base = id * 8;
516 + gc->owner = THIS_MODULE;
517 + platform_set_drvdata(pdev, gc);
518
519 - return gpiochip_add(&bgc->gc);
520 + return gpiochip_add_data(gc, NULL);
521 }
522
523 static int clps711x_gpio_remove(struct platform_device *pdev)
524 {
525 - struct bgpio_chip *bgc = platform_get_drvdata(pdev);
526 + struct gpio_chip *gc = platform_get_drvdata(pdev);
527
528 - return bgpio_remove(bgc);
529 + gpiochip_remove(gc);
530 + return 0;
531 }
532
533 static const struct of_device_id __maybe_unused clps711x_gpio_ids[] = {
534 --- a/drivers/gpio/gpio-dwapb.c
535 +++ b/drivers/gpio/gpio-dwapb.c
536 @@ -7,7 +7,9 @@
537 *
538 * All enquiries to support@picochip.com
539 */
540 -#include <linux/basic_mmio_gpio.h>
541 +#include <linux/gpio/driver.h>
542 +/* FIXME: for gpio_get_value(), replace this with direct register read */
543 +#include <linux/gpio.h>
544 #include <linux/err.h>
545 #include <linux/init.h>
546 #include <linux/interrupt.h>
547 @@ -66,7 +68,7 @@ struct dwapb_context {
548 #endif
549
550 struct dwapb_gpio_port {
551 - struct bgpio_chip bgc;
552 + struct gpio_chip gc;
553 bool is_registered;
554 struct dwapb_gpio *gpio;
555 #ifdef CONFIG_PM_SLEEP
556 @@ -83,33 +85,26 @@ struct dwapb_gpio {
557 struct irq_domain *domain;
558 };
559
560 -static inline struct dwapb_gpio_port *
561 -to_dwapb_gpio_port(struct bgpio_chip *bgc)
562 -{
563 - return container_of(bgc, struct dwapb_gpio_port, bgc);
564 -}
565 -
566 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
567 {
568 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
569 + struct gpio_chip *gc = &gpio->ports[0].gc;
570 void __iomem *reg_base = gpio->regs;
571
572 - return bgc->read_reg(reg_base + offset);
573 + return gc->read_reg(reg_base + offset);
574 }
575
576 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
577 u32 val)
578 {
579 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
580 + struct gpio_chip *gc = &gpio->ports[0].gc;
581 void __iomem *reg_base = gpio->regs;
582
583 - bgc->write_reg(reg_base + offset, val);
584 + gc->write_reg(reg_base + offset, val);
585 }
586
587 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
588 {
589 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
590 - struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
591 + struct dwapb_gpio_port *port = gpiochip_get_data(gc);
592 struct dwapb_gpio *gpio = port->gpio;
593
594 return irq_find_mapping(gpio->domain, offset);
595 @@ -119,7 +114,7 @@ static void dwapb_toggle_trigger(struct
596 {
597 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
598
599 - if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
600 + if (gpio_get_value(gpio->ports[0].gc.base + offs))
601 v &= ~BIT(offs);
602 else
603 v |= BIT(offs);
604 @@ -162,39 +157,39 @@ static void dwapb_irq_enable(struct irq_
605 {
606 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
607 struct dwapb_gpio *gpio = igc->private;
608 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
609 + struct gpio_chip *gc = &gpio->ports[0].gc;
610 unsigned long flags;
611 u32 val;
612
613 - spin_lock_irqsave(&bgc->lock, flags);
614 + spin_lock_irqsave(&gc->bgpio_lock, flags);
615 val = dwapb_read(gpio, GPIO_INTEN);
616 val |= BIT(d->hwirq);
617 dwapb_write(gpio, GPIO_INTEN, val);
618 - spin_unlock_irqrestore(&bgc->lock, flags);
619 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
620 }
621
622 static void dwapb_irq_disable(struct irq_data *d)
623 {
624 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
625 struct dwapb_gpio *gpio = igc->private;
626 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
627 + struct gpio_chip *gc = &gpio->ports[0].gc;
628 unsigned long flags;
629 u32 val;
630
631 - spin_lock_irqsave(&bgc->lock, flags);
632 + spin_lock_irqsave(&gc->bgpio_lock, flags);
633 val = dwapb_read(gpio, GPIO_INTEN);
634 val &= ~BIT(d->hwirq);
635 dwapb_write(gpio, GPIO_INTEN, val);
636 - spin_unlock_irqrestore(&bgc->lock, flags);
637 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
638 }
639
640 static int dwapb_irq_reqres(struct irq_data *d)
641 {
642 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
643 struct dwapb_gpio *gpio = igc->private;
644 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
645 + struct gpio_chip *gc = &gpio->ports[0].gc;
646
647 - if (gpiochip_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
648 + if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
649 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
650 irqd_to_hwirq(d));
651 return -EINVAL;
652 @@ -206,16 +201,16 @@ static void dwapb_irq_relres(struct irq_
653 {
654 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
655 struct dwapb_gpio *gpio = igc->private;
656 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
657 + struct gpio_chip *gc = &gpio->ports[0].gc;
658
659 - gpiochip_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
660 + gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
661 }
662
663 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
664 {
665 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
666 struct dwapb_gpio *gpio = igc->private;
667 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
668 + struct gpio_chip *gc = &gpio->ports[0].gc;
669 int bit = d->hwirq;
670 unsigned long level, polarity, flags;
671
672 @@ -223,7 +218,7 @@ static int dwapb_irq_set_type(struct irq
673 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
674 return -EINVAL;
675
676 - spin_lock_irqsave(&bgc->lock, flags);
677 + spin_lock_irqsave(&gc->bgpio_lock, flags);
678 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
679 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
680
681 @@ -254,7 +249,7 @@ static int dwapb_irq_set_type(struct irq
682
683 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
684 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
685 - spin_unlock_irqrestore(&bgc->lock, flags);
686 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
687
688 return 0;
689 }
690 @@ -262,13 +257,12 @@ static int dwapb_irq_set_type(struct irq
691 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
692 unsigned offset, unsigned debounce)
693 {
694 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
695 - struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
696 + struct dwapb_gpio_port *port = gpiochip_get_data(gc);
697 struct dwapb_gpio *gpio = port->gpio;
698 unsigned long flags, val_deb;
699 - unsigned long mask = bgc->pin2mask(bgc, offset);
700 + unsigned long mask = gc->pin2mask(gc, offset);
701
702 - spin_lock_irqsave(&bgc->lock, flags);
703 + spin_lock_irqsave(&gc->bgpio_lock, flags);
704
705 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
706 if (debounce)
707 @@ -276,7 +270,7 @@ static int dwapb_gpio_set_debounce(struc
708 else
709 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
710
711 - spin_unlock_irqrestore(&bgc->lock, flags);
712 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
713
714 return 0;
715 }
716 @@ -295,7 +289,7 @@ static void dwapb_configure_irqs(struct
717 struct dwapb_gpio_port *port,
718 struct dwapb_port_property *pp)
719 {
720 - struct gpio_chip *gc = &port->bgc.gc;
721 + struct gpio_chip *gc = &port->gc;
722 struct device_node *node = pp->node;
723 struct irq_chip_generic *irq_gc = NULL;
724 unsigned int hwirq, ngpio = gc->ngpio;
725 @@ -369,13 +363,13 @@ static void dwapb_configure_irqs(struct
726 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
727 irq_create_mapping(gpio->domain, hwirq);
728
729 - port->bgc.gc.to_irq = dwapb_gpio_to_irq;
730 + port->gc.to_irq = dwapb_gpio_to_irq;
731 }
732
733 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
734 {
735 struct dwapb_gpio_port *port = &gpio->ports[0];
736 - struct gpio_chip *gc = &port->bgc.gc;
737 + struct gpio_chip *gc = &port->gc;
738 unsigned int ngpio = gc->ngpio;
739 irq_hw_number_t hwirq;
740
741 @@ -412,7 +406,7 @@ static int dwapb_gpio_add_port(struct dw
742 dirout = gpio->regs + GPIO_SWPORTA_DDR +
743 (pp->idx * GPIO_SWPORT_DDR_SIZE);
744
745 - err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
746 + err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
747 NULL, false);
748 if (err) {
749 dev_err(gpio->dev, "failed to init gpio chip for %s\n",
750 @@ -421,19 +415,19 @@ static int dwapb_gpio_add_port(struct dw
751 }
752
753 #ifdef CONFIG_OF_GPIO
754 - port->bgc.gc.of_node = pp->node;
755 + port->gc.of_node = pp->node;
756 #endif
757 - port->bgc.gc.ngpio = pp->ngpio;
758 - port->bgc.gc.base = pp->gpio_base;
759 + port->gc.ngpio = pp->ngpio;
760 + port->gc.base = pp->gpio_base;
761
762 /* Only port A support debounce */
763 if (pp->idx == 0)
764 - port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
765 + port->gc.set_debounce = dwapb_gpio_set_debounce;
766
767 if (pp->irq)
768 dwapb_configure_irqs(gpio, port, pp);
769
770 - err = gpiochip_add(&port->bgc.gc);
771 + err = gpiochip_add_data(&port->gc, port);
772 if (err)
773 dev_err(gpio->dev, "failed to register gpiochip for %s\n",
774 pp->name);
775 @@ -449,7 +443,7 @@ static void dwapb_gpio_unregister(struct
776
777 for (m = 0; m < gpio->nr_ports; ++m)
778 if (gpio->ports[m].is_registered)
779 - gpiochip_remove(&gpio->ports[m].bgc.gc);
780 + gpiochip_remove(&gpio->ports[m].gc);
781 }
782
783 static struct dwapb_platform_data *
784 @@ -591,11 +585,11 @@ static int dwapb_gpio_suspend(struct dev
785 {
786 struct platform_device *pdev = to_platform_device(dev);
787 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
788 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
789 + struct gpio_chip *gc = &gpio->ports[0].gc;
790 unsigned long flags;
791 int i;
792
793 - spin_lock_irqsave(&bgc->lock, flags);
794 + spin_lock_irqsave(&gc->bgpio_lock, flags);
795 for (i = 0; i < gpio->nr_ports; i++) {
796 unsigned int offset;
797 unsigned int idx = gpio->ports[i].idx;
798 @@ -624,7 +618,7 @@ static int dwapb_gpio_suspend(struct dev
799 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
800 }
801 }
802 - spin_unlock_irqrestore(&bgc->lock, flags);
803 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
804
805 return 0;
806 }
807 @@ -633,11 +627,11 @@ static int dwapb_gpio_resume(struct devi
808 {
809 struct platform_device *pdev = to_platform_device(dev);
810 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
811 - struct bgpio_chip *bgc = &gpio->ports[0].bgc;
812 + struct gpio_chip *gc = &gpio->ports[0].gc;
813 unsigned long flags;
814 int i;
815
816 - spin_lock_irqsave(&bgc->lock, flags);
817 + spin_lock_irqsave(&gc->bgpio_lock, flags);
818 for (i = 0; i < gpio->nr_ports; i++) {
819 unsigned int offset;
820 unsigned int idx = gpio->ports[i].idx;
821 @@ -666,7 +660,7 @@ static int dwapb_gpio_resume(struct devi
822 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
823 }
824 }
825 - spin_unlock_irqrestore(&bgc->lock, flags);
826 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
827
828 return 0;
829 }
830 --- a/drivers/gpio/gpio-ep93xx.c
831 +++ b/drivers/gpio/gpio-ep93xx.c
832 @@ -16,10 +16,11 @@
833 #include <linux/module.h>
834 #include <linux/platform_device.h>
835 #include <linux/io.h>
836 -#include <linux/gpio.h>
837 #include <linux/irq.h>
838 #include <linux/slab.h>
839 -#include <linux/basic_mmio_gpio.h>
840 +#include <linux/gpio/driver.h>
841 +/* FIXME: this is here for gpio_to_irq() - get rid of this! */
842 +#include <linux/gpio.h>
843
844 #include <mach/hardware.h>
845 #include <mach/gpio-ep93xx.h>
846 @@ -28,7 +29,7 @@
847
848 struct ep93xx_gpio {
849 void __iomem *mmio_base;
850 - struct bgpio_chip bgc[8];
851 + struct gpio_chip gc[8];
852 };
853
854 /*************************************************************************
855 @@ -319,26 +320,26 @@ static int ep93xx_gpio_to_irq(struct gpi
856 return 64 + gpio;
857 }
858
859 -static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
860 +static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
861 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
862 {
863 void __iomem *data = mmio_base + bank->data;
864 void __iomem *dir = mmio_base + bank->dir;
865 int err;
866
867 - err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
868 + err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
869 if (err)
870 return err;
871
872 - bgc->gc.label = bank->label;
873 - bgc->gc.base = bank->base;
874 + gc->label = bank->label;
875 + gc->base = bank->base;
876
877 if (bank->has_debounce) {
878 - bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
879 - bgc->gc.to_irq = ep93xx_gpio_to_irq;
880 + gc->set_debounce = ep93xx_gpio_set_debounce;
881 + gc->to_irq = ep93xx_gpio_to_irq;
882 }
883
884 - return gpiochip_add(&bgc->gc);
885 + return gpiochip_add_data(gc, NULL);
886 }
887
888 static int ep93xx_gpio_probe(struct platform_device *pdev)
889 @@ -358,10 +359,10 @@ static int ep93xx_gpio_probe(struct plat
890 return PTR_ERR(ep93xx_gpio->mmio_base);
891
892 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
893 - struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
894 + struct gpio_chip *gc = &ep93xx_gpio->gc[i];
895 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
896
897 - if (ep93xx_gpio_add_bank(bgc, &pdev->dev,
898 + if (ep93xx_gpio_add_bank(gc, &pdev->dev,
899 ep93xx_gpio->mmio_base, bank))
900 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
901 bank->label);
902 --- a/drivers/gpio/gpio-etraxfs.c
903 +++ b/drivers/gpio/gpio-etraxfs.c
904 @@ -1,12 +1,10 @@
905 #include <linux/kernel.h>
906 #include <linux/init.h>
907 -#include <linux/gpio.h>
908 #include <linux/gpio/driver.h>
909 #include <linux/of_gpio.h>
910 #include <linux/io.h>
911 #include <linux/interrupt.h>
912 #include <linux/platform_device.h>
913 -#include <linux/basic_mmio_gpio.h>
914
915 #define ETRAX_FS_rw_pa_dout 0
916 #define ETRAX_FS_r_pa_din 4
917 @@ -67,7 +65,7 @@ struct etraxfs_gpio_block {
918 };
919
920 struct etraxfs_gpio_chip {
921 - struct bgpio_chip bgc;
922 + struct gpio_chip gc;
923 struct etraxfs_gpio_block *block;
924 };
925
926 @@ -176,11 +174,6 @@ static const struct etraxfs_gpio_info et
927 .rw_intr_pins = ARTPEC3_rw_intr_pins,
928 };
929
930 -static struct etraxfs_gpio_chip *to_etraxfs(struct gpio_chip *gc)
931 -{
932 - return container_of(gc, struct etraxfs_gpio_chip, bgc.gc);
933 -}
934 -
935 static unsigned int etraxfs_gpio_chip_to_port(struct gpio_chip *gc)
936 {
937 return gc->label[0] - 'A';
938 @@ -220,13 +213,13 @@ static unsigned int etraxfs_gpio_to_grou
939 static unsigned int etraxfs_gpio_to_group_pin(struct etraxfs_gpio_chip *chip,
940 unsigned int gpio)
941 {
942 - return 4 * etraxfs_gpio_chip_to_port(&chip->bgc.gc) + gpio / 8;
943 + return 4 * etraxfs_gpio_chip_to_port(&chip->gc) + gpio / 8;
944 }
945
946 static void etraxfs_gpio_irq_ack(struct irq_data *d)
947 {
948 struct etraxfs_gpio_chip *chip =
949 - to_etraxfs(irq_data_get_irq_chip_data(d));
950 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
951 struct etraxfs_gpio_block *block = chip->block;
952 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
953
954 @@ -236,7 +229,7 @@ static void etraxfs_gpio_irq_ack(struct
955 static void etraxfs_gpio_irq_mask(struct irq_data *d)
956 {
957 struct etraxfs_gpio_chip *chip =
958 - to_etraxfs(irq_data_get_irq_chip_data(d));
959 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
960 struct etraxfs_gpio_block *block = chip->block;
961 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
962
963 @@ -249,7 +242,7 @@ static void etraxfs_gpio_irq_mask(struct
964 static void etraxfs_gpio_irq_unmask(struct irq_data *d)
965 {
966 struct etraxfs_gpio_chip *chip =
967 - to_etraxfs(irq_data_get_irq_chip_data(d));
968 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
969 struct etraxfs_gpio_block *block = chip->block;
970 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
971
972 @@ -262,7 +255,7 @@ static void etraxfs_gpio_irq_unmask(stru
973 static int etraxfs_gpio_irq_set_type(struct irq_data *d, u32 type)
974 {
975 struct etraxfs_gpio_chip *chip =
976 - to_etraxfs(irq_data_get_irq_chip_data(d));
977 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
978 struct etraxfs_gpio_block *block = chip->block;
979 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
980 u32 cfg;
981 @@ -299,7 +292,7 @@ static int etraxfs_gpio_irq_set_type(str
982 static int etraxfs_gpio_irq_request_resources(struct irq_data *d)
983 {
984 struct etraxfs_gpio_chip *chip =
985 - to_etraxfs(irq_data_get_irq_chip_data(d));
986 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
987 struct etraxfs_gpio_block *block = chip->block;
988 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
989 int ret = -EBUSY;
990 @@ -308,7 +301,7 @@ static int etraxfs_gpio_irq_request_reso
991 if (block->group[grpirq])
992 goto out;
993
994 - ret = gpiochip_lock_as_irq(&chip->bgc.gc, d->hwirq);
995 + ret = gpiochip_lock_as_irq(&chip->gc, d->hwirq);
996 if (ret)
997 goto out;
998
999 @@ -330,13 +323,13 @@ out:
1000 static void etraxfs_gpio_irq_release_resources(struct irq_data *d)
1001 {
1002 struct etraxfs_gpio_chip *chip =
1003 - to_etraxfs(irq_data_get_irq_chip_data(d));
1004 + gpiochip_get_data(irq_data_get_irq_chip_data(d));
1005 struct etraxfs_gpio_block *block = chip->block;
1006 unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
1007
1008 spin_lock(&block->lock);
1009 block->group[grpirq] = 0;
1010 - gpiochip_unlock_as_irq(&chip->bgc.gc, d->hwirq);
1011 + gpiochip_unlock_as_irq(&chip->gc, d->hwirq);
1012 spin_unlock(&block->lock);
1013 }
1014
1015 @@ -419,7 +412,7 @@ static int etraxfs_gpio_probe(struct pla
1016
1017 for (i = 0; i < info->num_ports; i++) {
1018 struct etraxfs_gpio_chip *chip = &chips[i];
1019 - struct bgpio_chip *bgc = &chip->bgc;
1020 + struct gpio_chip *gc = &chip->gc;
1021 const struct etraxfs_gpio_port *port = &info->ports[i];
1022 unsigned long flags = BGPIOF_READ_OUTPUT_REG_SET;
1023 void __iomem *dat = regs + port->din;
1024 @@ -433,7 +426,7 @@ static int etraxfs_gpio_probe(struct pla
1025 flags = BGPIOF_NO_OUTPUT;
1026 }
1027
1028 - ret = bgpio_init(bgc, dev, 4,
1029 + ret = bgpio_init(gc, dev, 4,
1030 dat, set, NULL, dirout, NULL,
1031 flags);
1032 if (ret) {
1033 @@ -442,28 +435,28 @@ static int etraxfs_gpio_probe(struct pla
1034 continue;
1035 }
1036
1037 - bgc->gc.ngpio = port->ngpio;
1038 - bgc->gc.label = port->label;
1039 + gc->ngpio = port->ngpio;
1040 + gc->label = port->label;
1041
1042 - bgc->gc.of_node = dev->of_node;
1043 - bgc->gc.of_gpio_n_cells = 3;
1044 - bgc->gc.of_xlate = etraxfs_gpio_of_xlate;
1045 + gc->of_node = dev->of_node;
1046 + gc->of_gpio_n_cells = 3;
1047 + gc->of_xlate = etraxfs_gpio_of_xlate;
1048
1049 - ret = gpiochip_add(&bgc->gc);
1050 + ret = gpiochip_add_data(gc, chip);
1051 if (ret) {
1052 dev_err(dev, "Unable to register port %s\n",
1053 - bgc->gc.label);
1054 + gc->label);
1055 continue;
1056 }
1057
1058 if (i > 0 && !allportsirq)
1059 continue;
1060
1061 - ret = gpiochip_irqchip_add(&bgc->gc, &etraxfs_gpio_irq_chip, 0,
1062 + ret = gpiochip_irqchip_add(gc, &etraxfs_gpio_irq_chip, 0,
1063 handle_level_irq, IRQ_TYPE_NONE);
1064 if (ret) {
1065 dev_err(dev, "Unable to add irqchip to port %s\n",
1066 - bgc->gc.label);
1067 + gc->label);
1068 }
1069 }
1070
1071 --- a/drivers/gpio/gpio-ge.c
1072 +++ b/drivers/gpio/gpio-ge.c
1073 @@ -24,7 +24,7 @@
1074 #include <linux/of_gpio.h>
1075 #include <linux/of_address.h>
1076 #include <linux/module.h>
1077 -#include <linux/basic_mmio_gpio.h>
1078 +#include <linux/gpio/driver.h>
1079
1080 #define GEF_GPIO_DIRECT 0x00
1081 #define GEF_GPIO_IN 0x04
1082 @@ -55,19 +55,19 @@ static int __init gef_gpio_probe(struct
1083 {
1084 const struct of_device_id *of_id =
1085 of_match_device(gef_gpio_ids, &pdev->dev);
1086 - struct bgpio_chip *bgc;
1087 + struct gpio_chip *gc;
1088 void __iomem *regs;
1089 int ret;
1090
1091 - bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
1092 - if (!bgc)
1093 + gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
1094 + if (!gc)
1095 return -ENOMEM;
1096
1097 regs = of_iomap(pdev->dev.of_node, 0);
1098 if (!regs)
1099 return -ENOMEM;
1100
1101 - ret = bgpio_init(bgc, &pdev->dev, 4, regs + GEF_GPIO_IN,
1102 + ret = bgpio_init(gc, &pdev->dev, 4, regs + GEF_GPIO_IN,
1103 regs + GEF_GPIO_OUT, NULL, NULL,
1104 regs + GEF_GPIO_DIRECT, BGPIOF_BIG_ENDIAN_BYTE_ORDER);
1105 if (ret) {
1106 @@ -76,20 +76,20 @@ static int __init gef_gpio_probe(struct
1107 }
1108
1109 /* Setup pointers to chip functions */
1110 - bgc->gc.label = devm_kstrdup(&pdev->dev, pdev->dev.of_node->full_name,
1111 + gc->label = devm_kstrdup(&pdev->dev, pdev->dev.of_node->full_name,
1112 GFP_KERNEL);
1113 - if (!bgc->gc.label) {
1114 + if (!gc->label) {
1115 ret = -ENOMEM;
1116 goto err0;
1117 }
1118
1119 - bgc->gc.base = -1;
1120 - bgc->gc.ngpio = (u16)(uintptr_t)of_id->data;
1121 - bgc->gc.of_gpio_n_cells = 2;
1122 - bgc->gc.of_node = pdev->dev.of_node;
1123 + gc->base = -1;
1124 + gc->ngpio = (u16)(uintptr_t)of_id->data;
1125 + gc->of_gpio_n_cells = 2;
1126 + gc->of_node = pdev->dev.of_node;
1127
1128 /* This function adds a memory mapped GPIO chip */
1129 - ret = gpiochip_add(&bgc->gc);
1130 + ret = gpiochip_add_data(gc, NULL);
1131 if (ret)
1132 goto err0;
1133
1134 --- a/drivers/gpio/gpio-generic.c
1135 +++ b/drivers/gpio/gpio-generic.c
1136 @@ -56,11 +56,10 @@ o ` ~~~~\___/
1137 #include <linux/log2.h>
1138 #include <linux/ioport.h>
1139 #include <linux/io.h>
1140 -#include <linux/gpio.h>
1141 +#include <linux/gpio/driver.h>
1142 #include <linux/slab.h>
1143 #include <linux/platform_device.h>
1144 #include <linux/mod_devicetable.h>
1145 -#include <linux/basic_mmio_gpio.h>
1146
1147 static void bgpio_write8(void __iomem *reg, unsigned long data)
1148 {
1149 @@ -124,33 +123,30 @@ static unsigned long bgpio_read32be(void
1150 return ioread32be(reg);
1151 }
1152
1153 -static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
1154 +static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
1155 {
1156 return 1 << pin;
1157 }
1158
1159 -static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
1160 +static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
1161 unsigned int pin)
1162 {
1163 - return 1 << (bgc->bits - 1 - pin);
1164 + return 1 << (gc->bgpio_bits - 1 - pin);
1165 }
1166
1167 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
1168 {
1169 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1170 - unsigned long pinmask = bgc->pin2mask(bgc, gpio);
1171 + unsigned long pinmask = gc->pin2mask(gc, gpio);
1172
1173 - if (bgc->dir & pinmask)
1174 - return !!(bgc->read_reg(bgc->reg_set) & pinmask);
1175 + if (gc->bgpio_dir & pinmask)
1176 + return !!(gc->read_reg(gc->reg_set) & pinmask);
1177 else
1178 - return !!(bgc->read_reg(bgc->reg_dat) & pinmask);
1179 + return !!(gc->read_reg(gc->reg_dat) & pinmask);
1180 }
1181
1182 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
1183 {
1184 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1185 -
1186 - return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
1187 + return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
1188 }
1189
1190 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
1191 @@ -159,53 +155,50 @@ static void bgpio_set_none(struct gpio_c
1192
1193 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
1194 {
1195 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1196 - unsigned long mask = bgc->pin2mask(bgc, gpio);
1197 + unsigned long mask = gc->pin2mask(gc, gpio);
1198 unsigned long flags;
1199
1200 - spin_lock_irqsave(&bgc->lock, flags);
1201 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1202
1203 if (val)
1204 - bgc->data |= mask;
1205 + gc->bgpio_data |= mask;
1206 else
1207 - bgc->data &= ~mask;
1208 + gc->bgpio_data &= ~mask;
1209
1210 - bgc->write_reg(bgc->reg_dat, bgc->data);
1211 + gc->write_reg(gc->reg_dat, gc->bgpio_data);
1212
1213 - spin_unlock_irqrestore(&bgc->lock, flags);
1214 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1215 }
1216
1217 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
1218 int val)
1219 {
1220 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1221 - unsigned long mask = bgc->pin2mask(bgc, gpio);
1222 + unsigned long mask = gc->pin2mask(gc, gpio);
1223
1224 if (val)
1225 - bgc->write_reg(bgc->reg_set, mask);
1226 + gc->write_reg(gc->reg_set, mask);
1227 else
1228 - bgc->write_reg(bgc->reg_clr, mask);
1229 + gc->write_reg(gc->reg_clr, mask);
1230 }
1231
1232 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
1233 {
1234 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1235 - unsigned long mask = bgc->pin2mask(bgc, gpio);
1236 + unsigned long mask = gc->pin2mask(gc, gpio);
1237 unsigned long flags;
1238
1239 - spin_lock_irqsave(&bgc->lock, flags);
1240 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1241
1242 if (val)
1243 - bgc->data |= mask;
1244 + gc->bgpio_data |= mask;
1245 else
1246 - bgc->data &= ~mask;
1247 + gc->bgpio_data &= ~mask;
1248
1249 - bgc->write_reg(bgc->reg_set, bgc->data);
1250 + gc->write_reg(gc->reg_set, gc->bgpio_data);
1251
1252 - spin_unlock_irqrestore(&bgc->lock, flags);
1253 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1254 }
1255
1256 -static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
1257 +static void bgpio_multiple_get_masks(struct gpio_chip *gc,
1258 unsigned long *mask, unsigned long *bits,
1259 unsigned long *set_mask,
1260 unsigned long *clear_mask)
1261 @@ -215,19 +208,19 @@ static void bgpio_multiple_get_masks(str
1262 *set_mask = 0;
1263 *clear_mask = 0;
1264
1265 - for (i = 0; i < bgc->bits; i++) {
1266 + for (i = 0; i < gc->bgpio_bits; i++) {
1267 if (*mask == 0)
1268 break;
1269 if (__test_and_clear_bit(i, mask)) {
1270 if (test_bit(i, bits))
1271 - *set_mask |= bgc->pin2mask(bgc, i);
1272 + *set_mask |= gc->pin2mask(gc, i);
1273 else
1274 - *clear_mask |= bgc->pin2mask(bgc, i);
1275 + *clear_mask |= gc->pin2mask(gc, i);
1276 }
1277 }
1278 }
1279
1280 -static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
1281 +static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
1282 unsigned long *mask,
1283 unsigned long *bits,
1284 void __iomem *reg)
1285 @@ -235,47 +228,42 @@ static void bgpio_set_multiple_single_re
1286 unsigned long flags;
1287 unsigned long set_mask, clear_mask;
1288
1289 - spin_lock_irqsave(&bgc->lock, flags);
1290 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1291
1292 - bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
1293 + bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
1294
1295 - bgc->data |= set_mask;
1296 - bgc->data &= ~clear_mask;
1297 + gc->bgpio_data |= set_mask;
1298 + gc->bgpio_data &= ~clear_mask;
1299
1300 - bgc->write_reg(reg, bgc->data);
1301 + gc->write_reg(reg, gc->bgpio_data);
1302
1303 - spin_unlock_irqrestore(&bgc->lock, flags);
1304 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1305 }
1306
1307 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
1308 unsigned long *bits)
1309 {
1310 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1311 -
1312 - bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
1313 + bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
1314 }
1315
1316 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
1317 unsigned long *bits)
1318 {
1319 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1320 -
1321 - bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
1322 + bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
1323 }
1324
1325 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
1326 unsigned long *mask,
1327 unsigned long *bits)
1328 {
1329 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1330 unsigned long set_mask, clear_mask;
1331
1332 - bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
1333 + bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
1334
1335 if (set_mask)
1336 - bgc->write_reg(bgc->reg_set, set_mask);
1337 + gc->write_reg(gc->reg_set, set_mask);
1338 if (clear_mask)
1339 - bgc->write_reg(bgc->reg_clr, clear_mask);
1340 + gc->write_reg(gc->reg_clr, clear_mask);
1341 }
1342
1343 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
1344 @@ -299,111 +287,103 @@ static int bgpio_simple_dir_out(struct g
1345
1346 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
1347 {
1348 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1349 unsigned long flags;
1350
1351 - spin_lock_irqsave(&bgc->lock, flags);
1352 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1353
1354 - bgc->dir &= ~bgc->pin2mask(bgc, gpio);
1355 - bgc->write_reg(bgc->reg_dir, bgc->dir);
1356 + gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
1357 + gc->write_reg(gc->reg_dir, gc->bgpio_dir);
1358
1359 - spin_unlock_irqrestore(&bgc->lock, flags);
1360 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1361
1362 return 0;
1363 }
1364
1365 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
1366 {
1367 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1368 -
1369 - return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
1370 - GPIOF_DIR_OUT : GPIOF_DIR_IN;
1371 + /* Return 0 if output, 1 of input */
1372 + return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
1373 }
1374
1375 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
1376 {
1377 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1378 unsigned long flags;
1379
1380 gc->set(gc, gpio, val);
1381
1382 - spin_lock_irqsave(&bgc->lock, flags);
1383 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1384
1385 - bgc->dir |= bgc->pin2mask(bgc, gpio);
1386 - bgc->write_reg(bgc->reg_dir, bgc->dir);
1387 + gc->bgpio_dir |= gc->pin2mask(gc, gpio);
1388 + gc->write_reg(gc->reg_dir, gc->bgpio_dir);
1389
1390 - spin_unlock_irqrestore(&bgc->lock, flags);
1391 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1392
1393 return 0;
1394 }
1395
1396 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
1397 {
1398 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1399 unsigned long flags;
1400
1401 - spin_lock_irqsave(&bgc->lock, flags);
1402 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1403
1404 - bgc->dir |= bgc->pin2mask(bgc, gpio);
1405 - bgc->write_reg(bgc->reg_dir, bgc->dir);
1406 + gc->bgpio_dir |= gc->pin2mask(gc, gpio);
1407 + gc->write_reg(gc->reg_dir, gc->bgpio_dir);
1408
1409 - spin_unlock_irqrestore(&bgc->lock, flags);
1410 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1411
1412 return 0;
1413 }
1414
1415 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
1416 {
1417 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1418 unsigned long flags;
1419
1420 gc->set(gc, gpio, val);
1421
1422 - spin_lock_irqsave(&bgc->lock, flags);
1423 + spin_lock_irqsave(&gc->bgpio_lock, flags);
1424
1425 - bgc->dir &= ~bgc->pin2mask(bgc, gpio);
1426 - bgc->write_reg(bgc->reg_dir, bgc->dir);
1427 + gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
1428 + gc->write_reg(gc->reg_dir, gc->bgpio_dir);
1429
1430 - spin_unlock_irqrestore(&bgc->lock, flags);
1431 + spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1432
1433 return 0;
1434 }
1435
1436 static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
1437 {
1438 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1439 -
1440 - return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
1441 - GPIOF_DIR_IN : GPIOF_DIR_OUT;
1442 + /* Return 0 if output, 1 if input */
1443 + return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
1444 }
1445
1446 static int bgpio_setup_accessors(struct device *dev,
1447 - struct bgpio_chip *bgc,
1448 + struct gpio_chip *gc,
1449 bool bit_be,
1450 bool byte_be)
1451 {
1452
1453 - switch (bgc->bits) {
1454 + switch (gc->bgpio_bits) {
1455 case 8:
1456 - bgc->read_reg = bgpio_read8;
1457 - bgc->write_reg = bgpio_write8;
1458 + gc->read_reg = bgpio_read8;
1459 + gc->write_reg = bgpio_write8;
1460 break;
1461 case 16:
1462 if (byte_be) {
1463 - bgc->read_reg = bgpio_read16be;
1464 - bgc->write_reg = bgpio_write16be;
1465 + gc->read_reg = bgpio_read16be;
1466 + gc->write_reg = bgpio_write16be;
1467 } else {
1468 - bgc->read_reg = bgpio_read16;
1469 - bgc->write_reg = bgpio_write16;
1470 + gc->read_reg = bgpio_read16;
1471 + gc->write_reg = bgpio_write16;
1472 }
1473 break;
1474 case 32:
1475 if (byte_be) {
1476 - bgc->read_reg = bgpio_read32be;
1477 - bgc->write_reg = bgpio_write32be;
1478 + gc->read_reg = bgpio_read32be;
1479 + gc->write_reg = bgpio_write32be;
1480 } else {
1481 - bgc->read_reg = bgpio_read32;
1482 - bgc->write_reg = bgpio_write32;
1483 + gc->read_reg = bgpio_read32;
1484 + gc->write_reg = bgpio_write32;
1485 }
1486 break;
1487 #if BITS_PER_LONG >= 64
1488 @@ -413,17 +393,17 @@ static int bgpio_setup_accessors(struct
1489 "64 bit big endian byte order unsupported\n");
1490 return -EINVAL;
1491 } else {
1492 - bgc->read_reg = bgpio_read64;
1493 - bgc->write_reg = bgpio_write64;
1494 + gc->read_reg = bgpio_read64;
1495 + gc->write_reg = bgpio_write64;
1496 }
1497 break;
1498 #endif /* BITS_PER_LONG >= 64 */
1499 default:
1500 - dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
1501 + dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
1502 return -EINVAL;
1503 }
1504
1505 - bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
1506 + gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
1507
1508 return 0;
1509 }
1510 @@ -450,44 +430,44 @@ static int bgpio_setup_accessors(struct
1511 * - an input direction register (named "dirin") where a 1 bit indicates
1512 * the GPIO is an input.
1513 */
1514 -static int bgpio_setup_io(struct bgpio_chip *bgc,
1515 +static int bgpio_setup_io(struct gpio_chip *gc,
1516 void __iomem *dat,
1517 void __iomem *set,
1518 void __iomem *clr,
1519 unsigned long flags)
1520 {
1521
1522 - bgc->reg_dat = dat;
1523 - if (!bgc->reg_dat)
1524 + gc->reg_dat = dat;
1525 + if (!gc->reg_dat)
1526 return -EINVAL;
1527
1528 if (set && clr) {
1529 - bgc->reg_set = set;
1530 - bgc->reg_clr = clr;
1531 - bgc->gc.set = bgpio_set_with_clear;
1532 - bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
1533 + gc->reg_set = set;
1534 + gc->reg_clr = clr;
1535 + gc->set = bgpio_set_with_clear;
1536 + gc->set_multiple = bgpio_set_multiple_with_clear;
1537 } else if (set && !clr) {
1538 - bgc->reg_set = set;
1539 - bgc->gc.set = bgpio_set_set;
1540 - bgc->gc.set_multiple = bgpio_set_multiple_set;
1541 + gc->reg_set = set;
1542 + gc->set = bgpio_set_set;
1543 + gc->set_multiple = bgpio_set_multiple_set;
1544 } else if (flags & BGPIOF_NO_OUTPUT) {
1545 - bgc->gc.set = bgpio_set_none;
1546 - bgc->gc.set_multiple = NULL;
1547 + gc->set = bgpio_set_none;
1548 + gc->set_multiple = NULL;
1549 } else {
1550 - bgc->gc.set = bgpio_set;
1551 - bgc->gc.set_multiple = bgpio_set_multiple;
1552 + gc->set = bgpio_set;
1553 + gc->set_multiple = bgpio_set_multiple;
1554 }
1555
1556 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
1557 (flags & BGPIOF_READ_OUTPUT_REG_SET))
1558 - bgc->gc.get = bgpio_get_set;
1559 + gc->get = bgpio_get_set;
1560 else
1561 - bgc->gc.get = bgpio_get;
1562 + gc->get = bgpio_get;
1563
1564 return 0;
1565 }
1566
1567 -static int bgpio_setup_direction(struct bgpio_chip *bgc,
1568 +static int bgpio_setup_direction(struct gpio_chip *gc,
1569 void __iomem *dirout,
1570 void __iomem *dirin,
1571 unsigned long flags)
1572 @@ -495,21 +475,21 @@ static int bgpio_setup_direction(struct
1573 if (dirout && dirin) {
1574 return -EINVAL;
1575 } else if (dirout) {
1576 - bgc->reg_dir = dirout;
1577 - bgc->gc.direction_output = bgpio_dir_out;
1578 - bgc->gc.direction_input = bgpio_dir_in;
1579 - bgc->gc.get_direction = bgpio_get_dir;
1580 + gc->reg_dir = dirout;
1581 + gc->direction_output = bgpio_dir_out;
1582 + gc->direction_input = bgpio_dir_in;
1583 + gc->get_direction = bgpio_get_dir;
1584 } else if (dirin) {
1585 - bgc->reg_dir = dirin;
1586 - bgc->gc.direction_output = bgpio_dir_out_inv;
1587 - bgc->gc.direction_input = bgpio_dir_in_inv;
1588 - bgc->gc.get_direction = bgpio_get_dir_inv;
1589 + gc->reg_dir = dirin;
1590 + gc->direction_output = bgpio_dir_out_inv;
1591 + gc->direction_input = bgpio_dir_in_inv;
1592 + gc->get_direction = bgpio_get_dir_inv;
1593 } else {
1594 if (flags & BGPIOF_NO_OUTPUT)
1595 - bgc->gc.direction_output = bgpio_dir_out_err;
1596 + gc->direction_output = bgpio_dir_out_err;
1597 else
1598 - bgc->gc.direction_output = bgpio_simple_dir_out;
1599 - bgc->gc.direction_input = bgpio_simple_dir_in;
1600 + gc->direction_output = bgpio_simple_dir_out;
1601 + gc->direction_input = bgpio_simple_dir_in;
1602 }
1603
1604 return 0;
1605 @@ -523,14 +503,7 @@ static int bgpio_request(struct gpio_chi
1606 return -EINVAL;
1607 }
1608
1609 -int bgpio_remove(struct bgpio_chip *bgc)
1610 -{
1611 - gpiochip_remove(&bgc->gc);
1612 - return 0;
1613 -}
1614 -EXPORT_SYMBOL_GPL(bgpio_remove);
1615 -
1616 -int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
1617 +int bgpio_init(struct gpio_chip *gc, struct device *dev,
1618 unsigned long sz, void __iomem *dat, void __iomem *set,
1619 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
1620 unsigned long flags)
1621 @@ -540,36 +513,36 @@ int bgpio_init(struct bgpio_chip *bgc, s
1622 if (!is_power_of_2(sz))
1623 return -EINVAL;
1624
1625 - bgc->bits = sz * 8;
1626 - if (bgc->bits > BITS_PER_LONG)
1627 + gc->bgpio_bits = sz * 8;
1628 + if (gc->bgpio_bits > BITS_PER_LONG)
1629 return -EINVAL;
1630
1631 - spin_lock_init(&bgc->lock);
1632 - bgc->gc.dev = dev;
1633 - bgc->gc.label = dev_name(dev);
1634 - bgc->gc.base = -1;
1635 - bgc->gc.ngpio = bgc->bits;
1636 - bgc->gc.request = bgpio_request;
1637 + spin_lock_init(&gc->bgpio_lock);
1638 + gc->dev = dev;
1639 + gc->label = dev_name(dev);
1640 + gc->base = -1;
1641 + gc->ngpio = gc->bgpio_bits;
1642 + gc->request = bgpio_request;
1643
1644 - ret = bgpio_setup_io(bgc, dat, set, clr, flags);
1645 + ret = bgpio_setup_io(gc, dat, set, clr, flags);
1646 if (ret)
1647 return ret;
1648
1649 - ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
1650 + ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
1651 flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
1652 if (ret)
1653 return ret;
1654
1655 - ret = bgpio_setup_direction(bgc, dirout, dirin, flags);
1656 + ret = bgpio_setup_direction(gc, dirout, dirin, flags);
1657 if (ret)
1658 return ret;
1659
1660 - bgc->data = bgc->read_reg(bgc->reg_dat);
1661 - if (bgc->gc.set == bgpio_set_set &&
1662 + gc->bgpio_data = gc->read_reg(gc->reg_dat);
1663 + if (gc->set == bgpio_set_set &&
1664 !(flags & BGPIOF_UNREADABLE_REG_SET))
1665 - bgc->data = bgc->read_reg(bgc->reg_set);
1666 - if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
1667 - bgc->dir = bgc->read_reg(bgc->reg_dir);
1668 + gc->bgpio_data = gc->read_reg(gc->reg_set);
1669 + if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
1670 + gc->bgpio_dir = gc->read_reg(gc->reg_dir);
1671
1672 return ret;
1673 }
1674 @@ -607,7 +580,7 @@ static int bgpio_pdev_probe(struct platf
1675 unsigned long sz;
1676 unsigned long flags = pdev->id_entry->driver_data;
1677 int err;
1678 - struct bgpio_chip *bgc;
1679 + struct gpio_chip *gc;
1680 struct bgpio_pdata *pdata = dev_get_platdata(dev);
1681
1682 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1683 @@ -636,32 +609,33 @@ static int bgpio_pdev_probe(struct platf
1684 if (IS_ERR(dirin))
1685 return PTR_ERR(dirin);
1686
1687 - bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
1688 - if (!bgc)
1689 + gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
1690 + if (!gc)
1691 return -ENOMEM;
1692
1693 - err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
1694 + err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
1695 if (err)
1696 return err;
1697
1698 if (pdata) {
1699 if (pdata->label)
1700 - bgc->gc.label = pdata->label;
1701 - bgc->gc.base = pdata->base;
1702 + gc->label = pdata->label;
1703 + gc->base = pdata->base;
1704 if (pdata->ngpio > 0)
1705 - bgc->gc.ngpio = pdata->ngpio;
1706 + gc->ngpio = pdata->ngpio;
1707 }
1708
1709 - platform_set_drvdata(pdev, bgc);
1710 + platform_set_drvdata(pdev, gc);
1711
1712 - return gpiochip_add(&bgc->gc);
1713 + return gpiochip_add_data(gc, NULL);
1714 }
1715
1716 static int bgpio_pdev_remove(struct platform_device *pdev)
1717 {
1718 - struct bgpio_chip *bgc = platform_get_drvdata(pdev);
1719 + struct gpio_chip *gc = platform_get_drvdata(pdev);
1720
1721 - return bgpio_remove(bgc);
1722 + gpiochip_remove(gc);
1723 + return 0;
1724 }
1725
1726 static const struct platform_device_id bgpio_id_table[] = {
1727 --- a/drivers/gpio/gpio-grgpio.c
1728 +++ b/drivers/gpio/gpio-grgpio.c
1729 @@ -31,7 +31,7 @@
1730 #include <linux/gpio.h>
1731 #include <linux/slab.h>
1732 #include <linux/err.h>
1733 -#include <linux/basic_mmio_gpio.h>
1734 +#include <linux/gpio/driver.h>
1735 #include <linux/interrupt.h>
1736 #include <linux/irq.h>
1737 #include <linux/irqdomain.h>
1738 @@ -63,7 +63,7 @@ struct grgpio_lirq {
1739 };
1740
1741 struct grgpio_priv {
1742 - struct bgpio_chip bgc;
1743 + struct gpio_chip gc;
1744 void __iomem *regs;
1745 struct device *dev;
1746
1747 @@ -92,29 +92,22 @@ struct grgpio_priv {
1748 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
1749 };
1750
1751 -static inline struct grgpio_priv *grgpio_gc_to_priv(struct gpio_chip *gc)
1752 -{
1753 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
1754 -
1755 - return container_of(bgc, struct grgpio_priv, bgc);
1756 -}
1757 -
1758 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
1759 int val)
1760 {
1761 - struct bgpio_chip *bgc = &priv->bgc;
1762 - unsigned long mask = bgc->pin2mask(bgc, offset);
1763 + struct gpio_chip *gc = &priv->gc;
1764 + unsigned long mask = gc->pin2mask(gc, offset);
1765
1766 if (val)
1767 priv->imask |= mask;
1768 else
1769 priv->imask &= ~mask;
1770 - bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
1771 + gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
1772 }
1773
1774 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
1775 {
1776 - struct grgpio_priv *priv = grgpio_gc_to_priv(gc);
1777 + struct grgpio_priv *priv = gpiochip_get_data(gc);
1778
1779 if (offset >= gc->ngpio)
1780 return -ENXIO;
1781 @@ -158,15 +151,15 @@ static int grgpio_irq_set_type(struct ir
1782 return -EINVAL;
1783 }
1784
1785 - spin_lock_irqsave(&priv->bgc.lock, flags);
1786 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1787
1788 - ipol = priv->bgc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
1789 - iedge = priv->bgc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
1790 + ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
1791 + iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
1792
1793 - priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
1794 - priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
1795 + priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
1796 + priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
1797
1798 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1799 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1800
1801 return 0;
1802 }
1803 @@ -177,11 +170,11 @@ static void grgpio_irq_mask(struct irq_d
1804 int offset = d->hwirq;
1805 unsigned long flags;
1806
1807 - spin_lock_irqsave(&priv->bgc.lock, flags);
1808 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1809
1810 grgpio_set_imask(priv, offset, 0);
1811
1812 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1813 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1814 }
1815
1816 static void grgpio_irq_unmask(struct irq_data *d)
1817 @@ -190,11 +183,11 @@ static void grgpio_irq_unmask(struct irq
1818 int offset = d->hwirq;
1819 unsigned long flags;
1820
1821 - spin_lock_irqsave(&priv->bgc.lock, flags);
1822 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1823
1824 grgpio_set_imask(priv, offset, 1);
1825
1826 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1827 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1828 }
1829
1830 static struct irq_chip grgpio_irq_chip = {
1831 @@ -207,12 +200,12 @@ static struct irq_chip grgpio_irq_chip =
1832 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
1833 {
1834 struct grgpio_priv *priv = dev;
1835 - int ngpio = priv->bgc.gc.ngpio;
1836 + int ngpio = priv->gc.ngpio;
1837 unsigned long flags;
1838 int i;
1839 int match = 0;
1840
1841 - spin_lock_irqsave(&priv->bgc.lock, flags);
1842 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1843
1844 /*
1845 * For each gpio line, call its interrupt handler if it its underlying
1846 @@ -228,7 +221,7 @@ static irqreturn_t grgpio_irq_handler(in
1847 }
1848 }
1849
1850 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1851 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1852
1853 if (!match)
1854 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
1855 @@ -260,7 +253,7 @@ static int grgpio_irq_map(struct irq_dom
1856 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
1857 irq, offset);
1858
1859 - spin_lock_irqsave(&priv->bgc.lock, flags);
1860 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1861
1862 /* Request underlying irq if not already requested */
1863 lirq->irq = irq;
1864 @@ -273,14 +266,14 @@ static int grgpio_irq_map(struct irq_dom
1865 "Could not request underlying irq %d\n",
1866 uirq->uirq);
1867
1868 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1869 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1870
1871 return ret;
1872 }
1873 }
1874 uirq->refcnt++;
1875
1876 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1877 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1878
1879 /* Setup irq */
1880 irq_set_chip_data(irq, priv);
1881 @@ -298,13 +291,13 @@ static void grgpio_irq_unmap(struct irq_
1882 struct grgpio_lirq *lirq;
1883 struct grgpio_uirq *uirq;
1884 unsigned long flags;
1885 - int ngpio = priv->bgc.gc.ngpio;
1886 + int ngpio = priv->gc.ngpio;
1887 int i;
1888
1889 irq_set_chip_and_handler(irq, NULL, NULL);
1890 irq_set_chip_data(irq, NULL);
1891
1892 - spin_lock_irqsave(&priv->bgc.lock, flags);
1893 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1894
1895 /* Free underlying irq if last user unmapped */
1896 index = -1;
1897 @@ -326,7 +319,7 @@ static void grgpio_irq_unmap(struct irq_
1898 free_irq(uirq->uirq, priv);
1899 }
1900
1901 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1902 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1903 }
1904
1905 static const struct irq_domain_ops grgpio_irq_domain_ops = {
1906 @@ -341,7 +334,6 @@ static int grgpio_probe(struct platform_
1907 struct device_node *np = ofdev->dev.of_node;
1908 void __iomem *regs;
1909 struct gpio_chip *gc;
1910 - struct bgpio_chip *bgc;
1911 struct grgpio_priv *priv;
1912 struct resource *res;
1913 int err;
1914 @@ -359,8 +351,8 @@ static int grgpio_probe(struct platform_
1915 if (IS_ERR(regs))
1916 return PTR_ERR(regs);
1917
1918 - bgc = &priv->bgc;
1919 - err = bgpio_init(bgc, &ofdev->dev, 4, regs + GRGPIO_DATA,
1920 + gc = &priv->gc;
1921 + err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
1922 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
1923 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
1924 if (err) {
1925 @@ -369,10 +361,9 @@ static int grgpio_probe(struct platform_
1926 }
1927
1928 priv->regs = regs;
1929 - priv->imask = bgc->read_reg(regs + GRGPIO_IMASK);
1930 + priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
1931 priv->dev = &ofdev->dev;
1932
1933 - gc = &bgc->gc;
1934 gc->of_node = np;
1935 gc->owner = THIS_MODULE;
1936 gc->to_irq = grgpio_to_irq;
1937 @@ -435,7 +426,7 @@ static int grgpio_probe(struct platform_
1938
1939 platform_set_drvdata(ofdev, priv);
1940
1941 - err = gpiochip_add(gc);
1942 + err = gpiochip_add_data(gc, priv);
1943 if (err) {
1944 dev_err(&ofdev->dev, "Could not add gpiochip\n");
1945 if (priv->domain)
1946 @@ -456,7 +447,7 @@ static int grgpio_remove(struct platform
1947 int i;
1948 int ret = 0;
1949
1950 - spin_lock_irqsave(&priv->bgc.lock, flags);
1951 + spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
1952
1953 if (priv->domain) {
1954 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
1955 @@ -467,13 +458,13 @@ static int grgpio_remove(struct platform
1956 }
1957 }
1958
1959 - gpiochip_remove(&priv->bgc.gc);
1960 + gpiochip_remove(&priv->gc);
1961
1962 if (priv->domain)
1963 irq_domain_remove(priv->domain);
1964
1965 out:
1966 - spin_unlock_irqrestore(&priv->bgc.lock, flags);
1967 + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
1968
1969 return ret;
1970 }
1971 --- a/drivers/gpio/gpio-moxart.c
1972 +++ b/drivers/gpio/gpio-moxart.c
1973 @@ -14,7 +14,6 @@
1974 #include <linux/init.h>
1975 #include <linux/irq.h>
1976 #include <linux/io.h>
1977 -#include <linux/gpio.h>
1978 #include <linux/platform_device.h>
1979 #include <linux/module.h>
1980 #include <linux/of_address.h>
1981 @@ -23,7 +22,7 @@
1982 #include <linux/delay.h>
1983 #include <linux/timer.h>
1984 #include <linux/bitops.h>
1985 -#include <linux/basic_mmio_gpio.h>
1986 +#include <linux/gpio/driver.h>
1987
1988 #define GPIO_DATA_OUT 0x00
1989 #define GPIO_DATA_IN 0x04
1990 @@ -33,12 +32,12 @@ static int moxart_gpio_probe(struct plat
1991 {
1992 struct device *dev = &pdev->dev;
1993 struct resource *res;
1994 - struct bgpio_chip *bgc;
1995 + struct gpio_chip *gc;
1996 void __iomem *base;
1997 int ret;
1998
1999 - bgc = devm_kzalloc(dev, sizeof(*bgc), GFP_KERNEL);
2000 - if (!bgc)
2001 + gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
2002 + if (!gc)
2003 return -ENOMEM;
2004
2005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2006 @@ -46,7 +45,7 @@ static int moxart_gpio_probe(struct plat
2007 if (IS_ERR(base))
2008 return PTR_ERR(base);
2009
2010 - ret = bgpio_init(bgc, dev, 4, base + GPIO_DATA_IN,
2011 + ret = bgpio_init(gc, dev, 4, base + GPIO_DATA_IN,
2012 base + GPIO_DATA_OUT, NULL,
2013 base + GPIO_PIN_DIRECTION, NULL,
2014 BGPIOF_READ_OUTPUT_REG_SET);
2015 @@ -55,16 +54,16 @@ static int moxart_gpio_probe(struct plat
2016 return ret;
2017 }
2018
2019 - bgc->gc.label = "moxart-gpio";
2020 - bgc->gc.request = gpiochip_generic_request;
2021 - bgc->gc.free = gpiochip_generic_free;
2022 - bgc->data = bgc->read_reg(bgc->reg_set);
2023 - bgc->gc.base = 0;
2024 - bgc->gc.ngpio = 32;
2025 - bgc->gc.dev = dev;
2026 - bgc->gc.owner = THIS_MODULE;
2027 + gc->label = "moxart-gpio";
2028 + gc->request = gpiochip_generic_request;
2029 + gc->free = gpiochip_generic_free;
2030 + gc->bgpio_data = bgc->read_reg(bgc->reg_set);
2031 + gc->base = 0;
2032 + gc->ngpio = 32;
2033 + gc->dev = dev;
2034 + gc->owner = THIS_MODULE;
2035
2036 - ret = gpiochip_add(&bgc->gc);
2037 + ret = gpiochip_add_data(gc, NULL);
2038 if (ret) {
2039 dev_err(dev, "%s: gpiochip_add failed\n",
2040 dev->of_node->full_name);
2041 --- a/drivers/gpio/gpio-mxc.c
2042 +++ b/drivers/gpio/gpio-mxc.c
2043 @@ -26,10 +26,11 @@
2044 #include <linux/irq.h>
2045 #include <linux/irqdomain.h>
2046 #include <linux/irqchip/chained_irq.h>
2047 -#include <linux/gpio.h>
2048 #include <linux/platform_device.h>
2049 #include <linux/slab.h>
2050 -#include <linux/basic_mmio_gpio.h>
2051 +#include <linux/gpio/driver.h>
2052 +/* FIXME: for gpio_get_value() replace this with direct register read */
2053 +#include <linux/gpio.h>
2054 #include <linux/of.h>
2055 #include <linux/of_device.h>
2056 #include <linux/module.h>
2057 @@ -64,7 +65,7 @@ struct mxc_gpio_port {
2058 int irq;
2059 int irq_high;
2060 struct irq_domain *domain;
2061 - struct bgpio_chip bgc;
2062 + struct gpio_chip gc;
2063 u32 both_edges;
2064 };
2065
2066 @@ -172,7 +173,7 @@ static int gpio_set_irq_type(struct irq_
2067 struct mxc_gpio_port *port = gc->private;
2068 u32 bit, val;
2069 u32 gpio_idx = d->hwirq;
2070 - u32 gpio = port->bgc.gc.base + gpio_idx;
2071 + u32 gpio = port->gc.base + gpio_idx;
2072 int edge;
2073 void __iomem *reg = port->base;
2074
2075 @@ -398,9 +399,7 @@ static void mxc_gpio_get_hw(struct platf
2076
2077 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2078 {
2079 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
2080 - struct mxc_gpio_port *port =
2081 - container_of(bgc, struct mxc_gpio_port, bgc);
2082 + struct mxc_gpio_port *port = gpiochip_get_data(gc);
2083
2084 return irq_find_mapping(port->domain, offset);
2085 }
2086 @@ -451,7 +450,7 @@ static int mxc_gpio_probe(struct platfor
2087 port);
2088 }
2089
2090 - err = bgpio_init(&port->bgc, &pdev->dev, 4,
2091 + err = bgpio_init(&port->gc, &pdev->dev, 4,
2092 port->base + GPIO_PSR,
2093 port->base + GPIO_DR, NULL,
2094 port->base + GPIO_GDIR, NULL,
2095 @@ -459,13 +458,13 @@ static int mxc_gpio_probe(struct platfor
2096 if (err)
2097 goto out_bgio;
2098
2099 - port->bgc.gc.to_irq = mxc_gpio_to_irq;
2100 - port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
2101 + port->gc.to_irq = mxc_gpio_to_irq;
2102 + port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
2103 pdev->id * 32;
2104
2105 - err = gpiochip_add(&port->bgc.gc);
2106 + err = gpiochip_add_data(&port->gc, port);
2107 if (err)
2108 - goto out_bgpio_remove;
2109 + goto out_bgio;
2110
2111 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
2112 if (irq_base < 0) {
2113 @@ -494,9 +493,7 @@ out_irqdomain_remove:
2114 out_irqdesc_free:
2115 irq_free_descs(irq_base, 32);
2116 out_gpiochip_remove:
2117 - gpiochip_remove(&port->bgc.gc);
2118 -out_bgpio_remove:
2119 - bgpio_remove(&port->bgc);
2120 + gpiochip_remove(&port->gc);
2121 out_bgio:
2122 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
2123 return err;
2124 --- a/drivers/gpio/gpio-mxs.c
2125 +++ b/drivers/gpio/gpio-mxs.c
2126 @@ -26,13 +26,14 @@
2127 #include <linux/io.h>
2128 #include <linux/irq.h>
2129 #include <linux/irqdomain.h>
2130 -#include <linux/gpio.h>
2131 #include <linux/of.h>
2132 #include <linux/of_address.h>
2133 #include <linux/of_device.h>
2134 #include <linux/platform_device.h>
2135 #include <linux/slab.h>
2136 -#include <linux/basic_mmio_gpio.h>
2137 +#include <linux/gpio/driver.h>
2138 +/* FIXME: for gpio_get_value(), replace this by direct register read */
2139 +#include <linux/gpio.h>
2140 #include <linux/module.h>
2141
2142 #define MXS_SET 0x4
2143 @@ -64,7 +65,7 @@ struct mxs_gpio_port {
2144 int id;
2145 int irq;
2146 struct irq_domain *domain;
2147 - struct bgpio_chip bgc;
2148 + struct gpio_chip gc;
2149 enum mxs_gpio_id devid;
2150 u32 both_edges;
2151 };
2152 @@ -93,7 +94,7 @@ static int mxs_gpio_set_irq_type(struct
2153 port->both_edges &= ~pin_mask;
2154 switch (type) {
2155 case IRQ_TYPE_EDGE_BOTH:
2156 - val = gpio_get_value(port->bgc.gc.base + d->hwirq);
2157 + val = gpio_get_value(port->gc.base + d->hwirq);
2158 if (val)
2159 edge = GPIO_INT_FALL_EDGE;
2160 else
2161 @@ -225,18 +226,14 @@ static int __init mxs_gpio_init_gc(struc
2162
2163 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2164 {
2165 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
2166 - struct mxs_gpio_port *port =
2167 - container_of(bgc, struct mxs_gpio_port, bgc);
2168 + struct mxs_gpio_port *port = gpiochip_get_data(gc);
2169
2170 return irq_find_mapping(port->domain, offset);
2171 }
2172
2173 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
2174 {
2175 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
2176 - struct mxs_gpio_port *port =
2177 - container_of(bgc, struct mxs_gpio_port, bgc);
2178 + struct mxs_gpio_port *port = gpiochip_get_data(gc);
2179 u32 mask = 1 << offset;
2180 u32 dir;
2181
2182 @@ -330,26 +327,24 @@ static int mxs_gpio_probe(struct platfor
2183 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
2184 port);
2185
2186 - err = bgpio_init(&port->bgc, &pdev->dev, 4,
2187 + err = bgpio_init(&port->gc, &pdev->dev, 4,
2188 port->base + PINCTRL_DIN(port),
2189 port->base + PINCTRL_DOUT(port) + MXS_SET,
2190 port->base + PINCTRL_DOUT(port) + MXS_CLR,
2191 port->base + PINCTRL_DOE(port), NULL, 0);
2192 if (err)
2193 - goto out_irqdesc_free;
2194 + goto out_irqdomain_remove;
2195
2196 - port->bgc.gc.to_irq = mxs_gpio_to_irq;
2197 - port->bgc.gc.get_direction = mxs_gpio_get_direction;
2198 - port->bgc.gc.base = port->id * 32;
2199 + port->gc.to_irq = mxs_gpio_to_irq;
2200 + port->gc.get_direction = mxs_gpio_get_direction;
2201 + port->gc.base = port->id * 32;
2202
2203 - err = gpiochip_add(&port->bgc.gc);
2204 + err = gpiochip_add_data(&port->gc, port);
2205 if (err)
2206 - goto out_bgpio_remove;
2207 + goto out_irqdomain_remove;
2208
2209 return 0;
2210
2211 -out_bgpio_remove:
2212 - bgpio_remove(&port->bgc);
2213 out_irqdomain_remove:
2214 irq_domain_remove(port->domain);
2215 out_irqdesc_free:
2216 --- a/drivers/gpio/gpio-sodaville.c
2217 +++ b/drivers/gpio/gpio-sodaville.c
2218 @@ -10,7 +10,6 @@
2219 */
2220
2221 #include <linux/errno.h>
2222 -#include <linux/gpio.h>
2223 #include <linux/init.h>
2224 #include <linux/io.h>
2225 #include <linux/irq.h>
2226 @@ -20,7 +19,7 @@
2227 #include <linux/pci.h>
2228 #include <linux/platform_device.h>
2229 #include <linux/of_irq.h>
2230 -#include <linux/basic_mmio_gpio.h>
2231 +#include <linux/gpio/driver.h>
2232
2233 #define DRV_NAME "sdv_gpio"
2234 #define SDV_NUM_PUB_GPIOS 12
2235 @@ -43,7 +42,7 @@ struct sdv_gpio_chip_data {
2236 void __iomem *gpio_pub_base;
2237 struct irq_domain *id;
2238 struct irq_chip_generic *gc;
2239 - struct bgpio_chip bgpio;
2240 + struct gpio_chip chip;
2241 };
2242
2243 static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
2244 @@ -226,14 +225,14 @@ static int sdv_gpio_probe(struct pci_dev
2245 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
2246 }
2247
2248 - ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
2249 + ret = bgpio_init(&sd->chip, &pdev->dev, 4,
2250 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
2251 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
2252 if (ret)
2253 goto unmap;
2254 - sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
2255 + sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
2256
2257 - ret = gpiochip_add(&sd->bgpio.gc);
2258 + ret = gpiochip_add_data(&sd->chip, sd);
2259 if (ret < 0) {
2260 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
2261 goto unmap;
2262 @@ -265,7 +264,7 @@ static void sdv_gpio_remove(struct pci_d
2263 free_irq(pdev->irq, sd);
2264 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
2265
2266 - gpiochip_remove(&sd->bgpio.gc);
2267 + gpiochip_remove(&sd->chip);
2268 pci_release_region(pdev, GPIO_BAR);
2269 iounmap(sd->gpio_pub_base);
2270 pci_disable_device(pdev);
2271 --- a/drivers/gpio/gpio-xgene-sb.c
2272 +++ b/drivers/gpio/gpio-xgene-sb.c
2273 @@ -23,10 +23,8 @@
2274 #include <linux/io.h>
2275 #include <linux/platform_device.h>
2276 #include <linux/of_gpio.h>
2277 -#include <linux/gpio.h>
2278 #include <linux/gpio/driver.h>
2279 #include <linux/acpi.h>
2280 -#include <linux/basic_mmio_gpio.h>
2281
2282 #include "gpiolib.h"
2283
2284 @@ -43,38 +41,31 @@
2285
2286 /**
2287 * struct xgene_gpio_sb - GPIO-Standby private data structure.
2288 - * @bgc: memory-mapped GPIO controllers.
2289 + * @gc: memory-mapped GPIO controllers.
2290 * @irq: Mapping GPIO pins and interrupt number
2291 * nirq: Number of GPIO pins that supports interrupt
2292 */
2293 struct xgene_gpio_sb {
2294 - struct bgpio_chip bgc;
2295 + struct gpio_chip gc;
2296 u32 *irq;
2297 u32 nirq;
2298 };
2299
2300 -static inline struct xgene_gpio_sb *to_xgene_gpio_sb(struct gpio_chip *gc)
2301 -{
2302 - struct bgpio_chip *bgc = to_bgpio_chip(gc);
2303 -
2304 - return container_of(bgc, struct xgene_gpio_sb, bgc);
2305 -}
2306 -
2307 -static void xgene_gpio_set_bit(struct bgpio_chip *bgc, void __iomem *reg, u32 gpio, int val)
2308 +static void xgene_gpio_set_bit(struct gpio_chip *gc, void __iomem *reg, u32 gpio, int val)
2309 {
2310 u32 data;
2311
2312 - data = bgc->read_reg(reg);
2313 + data = gc->read_reg(reg);
2314 if (val)
2315 data |= GPIO_MASK(gpio);
2316 else
2317 data &= ~GPIO_MASK(gpio);
2318 - bgc->write_reg(reg, data);
2319 + gc->write_reg(reg, data);
2320 }
2321
2322 static int apm_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
2323 {
2324 - struct xgene_gpio_sb *priv = to_xgene_gpio_sb(gc);
2325 + struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
2326
2327 if (priv->irq[gpio])
2328 return priv->irq[gpio];
2329 @@ -99,15 +90,15 @@ static int xgene_gpio_sb_probe(struct pl
2330 if (IS_ERR(regs))
2331 return PTR_ERR(regs);
2332
2333 - ret = bgpio_init(&priv->bgc, &pdev->dev, 4,
2334 + ret = bgpio_init(&priv->gc, &pdev->dev, 4,
2335 regs + MPA_GPIO_IN_ADDR,
2336 regs + MPA_GPIO_OUT_ADDR, NULL,
2337 regs + MPA_GPIO_OE_ADDR, NULL, 0);
2338 if (ret)
2339 return ret;
2340
2341 - priv->bgc.gc.to_irq = apm_gpio_sb_to_irq;
2342 - priv->bgc.gc.ngpio = XGENE_MAX_GPIO_DS;
2343 + priv->gc.to_irq = apm_gpio_sb_to_irq;
2344 + priv->gc.ngpio = XGENE_MAX_GPIO_DS;
2345
2346 priv->nirq = XGENE_MAX_GPIO_DS_IRQ;
2347
2348 @@ -118,14 +109,14 @@ static int xgene_gpio_sb_probe(struct pl
2349
2350 for (i = 0; i < priv->nirq; i++) {
2351 priv->irq[default_lines[i]] = platform_get_irq(pdev, i);
2352 - xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_SEL_LO,
2353 + xgene_gpio_set_bit(&priv->gc, regs + MPA_GPIO_SEL_LO,
2354 default_lines[i] * 2, 1);
2355 - xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_INT_LVL, i, 1);
2356 + xgene_gpio_set_bit(&priv->gc, regs + MPA_GPIO_INT_LVL, i, 1);
2357 }
2358
2359 platform_set_drvdata(pdev, priv);
2360
2361 - ret = gpiochip_add(&priv->bgc.gc);
2362 + ret = gpiochip_add_data(&priv->gc, priv);
2363 if (ret)
2364 dev_err(&pdev->dev, "failed to register X-Gene GPIO Standby driver\n");
2365 else
2366 @@ -133,7 +124,7 @@ static int xgene_gpio_sb_probe(struct pl
2367
2368 if (priv->nirq > 0) {
2369 /* Register interrupt handlers for gpio signaled acpi events */
2370 - acpi_gpiochip_request_interrupts(&priv->bgc.gc);
2371 + acpi_gpiochip_request_interrupts(&priv->gc);
2372 }
2373
2374 return ret;
2375 @@ -144,10 +135,11 @@ static int xgene_gpio_sb_remove(struct p
2376 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
2377
2378 if (priv->nirq > 0) {
2379 - acpi_gpiochip_free_interrupts(&priv->bgc.gc);
2380 + acpi_gpiochip_free_interrupts(&priv->gc);
2381 }
2382
2383 - return bgpio_remove(&priv->bgc);
2384 + gpiochip_remove(&priv->gc);
2385 + return 0;
2386 }
2387
2388 static const struct of_device_id xgene_gpio_sb_of_match[] = {
2389 --- a/drivers/mfd/vexpress-sysreg.c
2390 +++ b/drivers/mfd/vexpress-sysreg.c
2391 @@ -11,7 +11,7 @@
2392 * Copyright (C) 2012 ARM Limited
2393 */
2394
2395 -#include <linux/basic_mmio_gpio.h>
2396 +#include <linux/gpio/driver.h>
2397 #include <linux/err.h>
2398 #include <linux/io.h>
2399 #include <linux/mfd/core.h>
2400 @@ -164,7 +164,7 @@ static int vexpress_sysreg_probe(struct
2401 {
2402 struct resource *mem;
2403 void __iomem *base;
2404 - struct bgpio_chip *mmc_gpio_chip;
2405 + struct gpio_chip *mmc_gpio_chip;
2406 int master;
2407 u32 dt_hbi;
2408
2409 @@ -201,8 +201,8 @@ static int vexpress_sysreg_probe(struct
2410 return -ENOMEM;
2411 bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI,
2412 NULL, NULL, NULL, NULL, 0);
2413 - mmc_gpio_chip->gc.ngpio = 2;
2414 - gpiochip_add(&mmc_gpio_chip->gc);
2415 + mmc_gpio_chip->ngpio = 2;
2416 + gpiochip_add(mmc_gpio_chip);
2417
2418 return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
2419 vexpress_sysreg_cells,
2420 --- a/include/linux/basic_mmio_gpio.h
2421 +++ /dev/null
2422 @@ -1,80 +0,0 @@
2423 -/*
2424 - * Basic memory-mapped GPIO controllers.
2425 - *
2426 - * Copyright 2008 MontaVista Software, Inc.
2427 - * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
2428 - *
2429 - * This program is free software; you can redistribute it and/or modify it
2430 - * under the terms of the GNU General Public License as published by the
2431 - * Free Software Foundation; either version 2 of the License, or (at your
2432 - * option) any later version.
2433 - */
2434 -
2435 -#ifndef __BASIC_MMIO_GPIO_H
2436 -#define __BASIC_MMIO_GPIO_H
2437 -
2438 -#include <linux/gpio.h>
2439 -#include <linux/types.h>
2440 -#include <linux/compiler.h>
2441 -#include <linux/spinlock_types.h>
2442 -
2443 -struct bgpio_pdata {
2444 - const char *label;
2445 - int base;
2446 - int ngpio;
2447 -};
2448 -
2449 -struct device;
2450 -
2451 -struct bgpio_chip {
2452 - struct gpio_chip gc;
2453 -
2454 - unsigned long (*read_reg)(void __iomem *reg);
2455 - void (*write_reg)(void __iomem *reg, unsigned long data);
2456 -
2457 - void __iomem *reg_dat;
2458 - void __iomem *reg_set;
2459 - void __iomem *reg_clr;
2460 - void __iomem *reg_dir;
2461 -
2462 - /* Number of bits (GPIOs): <register width> * 8. */
2463 - int bits;
2464 -
2465 - /*
2466 - * Some GPIO controllers work with the big-endian bits notation,
2467 - * e.g. in a 8-bits register, GPIO7 is the least significant bit.
2468 - */
2469 - unsigned long (*pin2mask)(struct bgpio_chip *bgc, unsigned int pin);
2470 -
2471 - /*
2472 - * Used to lock bgpio_chip->data. Also, this is needed to keep
2473 - * shadowed and real data registers writes together.
2474 - */
2475 - spinlock_t lock;
2476 -
2477 - /* Shadowed data register to clear/set bits safely. */
2478 - unsigned long data;
2479 -
2480 - /* Shadowed direction registers to clear/set direction safely. */
2481 - unsigned long dir;
2482 -};
2483 -
2484 -static inline struct bgpio_chip *to_bgpio_chip(struct gpio_chip *gc)
2485 -{
2486 - return container_of(gc, struct bgpio_chip, gc);
2487 -}
2488 -
2489 -int bgpio_remove(struct bgpio_chip *bgc);
2490 -int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
2491 - unsigned long sz, void __iomem *dat, void __iomem *set,
2492 - void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
2493 - unsigned long flags);
2494 -
2495 -#define BGPIOF_BIG_ENDIAN BIT(0)
2496 -#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
2497 -#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
2498 -#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
2499 -#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
2500 -#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
2501 -
2502 -#endif /* __BASIC_MMIO_GPIO_H */
2503 --- a/include/linux/gpio/driver.h
2504 +++ b/include/linux/gpio/driver.h
2505 @@ -8,6 +8,7 @@
2506 #include <linux/irqdomain.h>
2507 #include <linux/lockdep.h>
2508 #include <linux/pinctrl/pinctrl.h>
2509 +#include <linux/kconfig.h>
2510
2511 struct device;
2512 struct gpio_desc;
2513 @@ -66,6 +67,23 @@ struct seq_file;
2514 * registers.
2515 * @irq_not_threaded: flag must be set if @can_sleep is set but the
2516 * IRQs don't need to be threaded
2517 + * @read_reg: reader function for generic GPIO
2518 + * @write_reg: writer function for generic GPIO
2519 + * @pin2mask: some generic GPIO controllers work with the big-endian bits
2520 + * notation, e.g. in a 8-bits register, GPIO7 is the least significant
2521 + * bit. This callback assigns the right bit mask.
2522 + * @reg_dat: data (in) register for generic GPIO
2523 + * @reg_set: output set register (out=high) for generic GPIO
2524 + * @reg_clk: output clear register (out=low) for generic GPIO
2525 + * @reg_dir: direction setting register for generic GPIO
2526 + * @bgpio_bits: number of register bits used for a generic GPIO i.e.
2527 + * <register width> * 8
2528 + * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
2529 + * shadowed and real data registers writes together.
2530 + * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
2531 + * safely.
2532 + * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
2533 + * direction safely.
2534 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
2535 * @irqdomain: Interrupt translation domain; responsible for mapping
2536 * between GPIO hwirq number and linux irq number
2537 @@ -129,6 +147,20 @@ struct gpio_chip {
2538 bool can_sleep;
2539 bool irq_not_threaded;
2540
2541 +#if IS_ENABLED(CONFIG_GPIO_GENERIC)
2542 + unsigned long (*read_reg)(void __iomem *reg);
2543 + void (*write_reg)(void __iomem *reg, unsigned long data);
2544 + unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
2545 + void __iomem *reg_dat;
2546 + void __iomem *reg_set;
2547 + void __iomem *reg_clr;
2548 + void __iomem *reg_dir;
2549 + int bgpio_bits;
2550 + spinlock_t bgpio_lock;
2551 + unsigned long bgpio_data;
2552 + unsigned long bgpio_dir;
2553 +#endif
2554 +
2555 #ifdef CONFIG_GPIOLIB_IRQCHIP
2556 /*
2557 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
2558 @@ -189,6 +221,28 @@ static inline void *gpiochip_get_data(st
2559
2560 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
2561
2562 +#if IS_ENABLED(CONFIG_GPIO_GENERIC)
2563 +
2564 +struct bgpio_pdata {
2565 + const char *label;
2566 + int base;
2567 + int ngpio;
2568 +};
2569 +
2570 +int bgpio_init(struct gpio_chip *gc, struct device *dev,
2571 + unsigned long sz, void __iomem *dat, void __iomem *set,
2572 + void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
2573 + unsigned long flags);
2574 +
2575 +#define BGPIOF_BIG_ENDIAN BIT(0)
2576 +#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
2577 +#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
2578 +#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
2579 +#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
2580 +#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
2581 +
2582 +#endif
2583 +
2584 #ifdef CONFIG_GPIOLIB_IRQCHIP
2585
2586 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
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