target/linux/brcm63xx/patches-4.4/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch

   1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sun, 3 Jul 2011 15:00:38 +0200
   4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/bcm63xx/dev-flash.c                     |   35 +++++++++++++++++++-
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +
  10  2 files changed, 33 insertions(+), 2 deletions(-)
  11
  12 --- a/arch/mips/bcm63xx/dev-flash.c
  13 +++ b/arch/mips/bcm63xx/dev-flash.c
  14 @@ -17,9 +17,13 @@
  15  #include <linux/mtd/partitions.h>
  16  #include <linux/mtd/physmap.h>
  17  #include <linux/mtd/spi-nor.h>
  18 +#include <linux/of.h>
  19 +#include <linux/spi/spi.h>
  20 +#include <linux/spi/flash.h>
  21
  22  #include <bcm63xx_cpu.h>
  23  #include <bcm63xx_dev_flash.h>
  24 +#include <bcm63xx_dev_hsspi.h>
  25  #include <bcm63xx_regs.h>
  26  #include <bcm63xx_io.h>
  27
  28 @@ -66,6 +70,41 @@ void __init bcm63xx_flash_force_phys_bas
  29         mtd_resources[0].end = end;
  30  }
  31
  32 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
  33 +       {
  34 +               .bus_num        = 0,
  35 +               .chip_select    = 0,
  36 +               .mode           = 0,
  37 +               .max_speed_hz   = 781000,
  38 +               .modalias       = "m25p80",
  39 +       },
  40 +};
  41 +
  42 +static void bcm63xx_of_update_spi_flash_speed(struct device_node *np,
  43 +                                              unsigned int new_hz)
  44 +{
  45 +       struct property *max_hz;
  46 +       __be32 *hz;
  47 +
  48 +       max_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL);
  49 +       if (!max_hz)
  50 +               return;
  51 +
  52 +       max_hz->name = kstrdup("spi-max-frequency", GFP_KERNEL);
  53 +       if (!max_hz->name) {
  54 +               kfree(max_hz);
  55 +               return;
  56 +       }
  57 +
  58 +       max_hz->value = max_hz + 1;
  59 +       max_hz->length = sizeof(*hz);
  60 +
  61 +       hz = max_hz->value;
  62 +       *hz = cpu_to_be32(new_hz);
  63 +
  64 +       of_update_property(np, max_hz);
  65 +}
  66 +
  67  static int __init bcm63xx_detect_flash_type(void)
  68  {
  69         u32 val;
  70 @@ -73,9 +112,15 @@ static int __init bcm63xx_detect_flash_t
  71         switch (bcm63xx_get_cpu_id()) {
  72         case BCM6318_CPU_ID:
  73                 /* only support serial flash */
  74 +               bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
  75                 return BCM63XX_FLASH_TYPE_SERIAL;
  76         case BCM6328_CPU_ID:
  77                 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
  78 +               if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
  79 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
  80 +               else
  81 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
  82 +
  83                 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  84                         return BCM63XX_FLASH_TYPE_SERIAL;
  85                 else
  86 @@ -94,12 +139,20 @@ static int __init bcm63xx_detect_flash_t
  87                         return BCM63XX_FLASH_TYPE_SERIAL;
  88         case BCM6362_CPU_ID:
  89                 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
  90 +               if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
  91 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
  92 +               else
  93 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
  94 +
  95                 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
  96                         return BCM63XX_FLASH_TYPE_SERIAL;
  97                 else
  98                         return BCM63XX_FLASH_TYPE_NAND;
  99         case BCM6368_CPU_ID:
 100                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
 101 +               if (val & STRAPBUS_6368_SPI_CLK_FAST)
 102 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
 103 +
 104                 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
 105                 case STRAPBUS_6368_BOOT_SEL_NAND:
 106                         return BCM63XX_FLASH_TYPE_NAND;
 107 @@ -110,6 +163,11 @@ static int __init bcm63xx_detect_flash_t
 108                 }
 109         case BCM63268_CPU_ID:
 110                 val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
 111 +               if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
 112 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
 113 +               else
 114 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
 115 +
 116                 if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
 117                         return BCM63XX_FLASH_TYPE_SERIAL;
 118                 else
 119 @@ -176,6 +234,7 @@ void __init bcm63xx_flash_detect(void)
 120
 121  int __init bcm63xx_flash_register(void)
 122  {
 123 +       struct device_node *np;
 124         u32 val;
 125
 126         switch (flash_type) {
 127 @@ -195,8 +254,14 @@ int __init bcm63xx_flash_register(void)
 128
 129                 return platform_device_register(&mtd_dev);
 130         case BCM63XX_FLASH_TYPE_SERIAL:
 131 -               pr_warn("unsupported serial flash detected\n");
 132 -               return -ENODEV;
 133 +               np = of_find_compatible_node(NULL, NULL, "jedec,spi-nor");
 134 +               if (np) {
 135 +                       bcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz);
 136 +                       of_node_put(np);
 137 +                       return 0;
 138 +               } else {
 139 +                       return -ENODEV;
 140 +               }
 141         case BCM63XX_FLASH_TYPE_NAND:
 142                 pr_warn("unsupported NAND flash detected\n");
 143                 return -ENODEV;
 144 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 145 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 146 @@ -708,6 +708,7 @@
 147  #define GPIO_STRAPBUS_REG              0x40
 148  #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
 149  #define STRAPBUS_6358_BOOT_SEL_SERIAL  (0 << 1)
 150 +#define STRAPBUS_6368_SPI_CLK_FAST     (1 << 6)
 151  #define STRAPBUS_6368_BOOT_SEL_MASK    0x3
 152  #define STRAPBUS_6368_BOOT_SEL_NAND    0
 153  #define STRAPBUS_6368_BOOT_SEL_SERIAL  1
 154 @@ -1564,6 +1565,7 @@
 155  #define IDDQ_CTRL_63268_USBH           (1 << 4)
 156
 157  #define MISC_STRAPBUS_6328_REG         0x240
 158 +#define STRAPBUS_6328_HSSPI_CLK_FAST   (1 << 4)
 159  #define STRAPBUS_6328_FCVO_SHIFT       7
 160  #define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 161  #define STRAPBUS_6328_BOOT_SEL_SERIAL  (1 << 28)