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[openwrt/openwrt.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c/at24.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <asm/setup.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/time.h>
44 #include <mach/cns3xxx.h>
45 #include <mach/irqs.h>
46 #include <mach/platform.h>
47 #include <mach/pm.h>
48 #include <mach/gpio.h>
49 #include <asm/hardware/gic.h>
50 #include "core.h"
51 #include "devices.h"
52
53 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
54
55 // Config 1 Bitmap
56 #define ETH0_LOAD BIT(0)
57 #define ETH1_LOAD BIT(1)
58 #define ETH2_LOAD BIT(2)
59 #define SATA0_LOAD BIT(3)
60 #define SATA1_LOAD BIT(4)
61 #define PCM_LOAD BIT(5)
62 #define I2S_LOAD BIT(6)
63 #define SPI0_LOAD BIT(7)
64 #define SPI1_LOAD BIT(8)
65 #define PCIE0_LOAD BIT(9)
66 #define PCIE1_LOAD BIT(10)
67 #define USB0_LOAD BIT(11)
68 #define USB1_LOAD BIT(12)
69 #define USB1_ROUTE BIT(13)
70 #define SD_LOAD BIT(14)
71 #define UART0_LOAD BIT(15)
72 #define UART1_LOAD BIT(16)
73 #define UART2_LOAD BIT(17)
74 #define MPCI0_LOAD BIT(18)
75 #define MPCI1_LOAD BIT(19)
76 #define MPCI2_LOAD BIT(20)
77 #define MPCI3_LOAD BIT(21)
78 #define FP_BUT_LOAD BIT(22)
79 #define FP_BUT_HEADER_LOAD BIT(23)
80 #define FP_LED_LOAD BIT(24)
81 #define FP_LED_HEADER_LOAD BIT(25)
82 #define FP_TAMPER_LOAD BIT(26)
83 #define HEADER_33V_LOAD BIT(27)
84 #define SATA_POWER_LOAD BIT(28)
85 #define FP_POWER_LOAD BIT(29)
86 #define GPIO_HEADER_LOAD BIT(30)
87 #define GSP_BAT_LOAD BIT(31)
88
89 // Config 2 Bitmap
90 #define FAN_LOAD BIT(0)
91 #define SPI_FLASH_LOAD BIT(1)
92 #define NOR_FLASH_LOAD BIT(2)
93 #define GPS_LOAD BIT(3)
94 #define SUPPLY_5V_LOAD BIT(6)
95 #define SUPPLY_33V_LOAD BIT(7)
96
97 struct laguna_board_info {
98 char model[16];
99 u32 config_bitmap;
100 u32 config2_bitmap;
101 u8 nor_flash_size;
102 u8 spi_flash_size;
103 };
104
105 static struct laguna_board_info laguna_info __initdata;
106
107 /*
108 * NOR Flash
109 */
110 static struct mtd_partition laguna_nor_partitions[] = {
111 {
112 .name = "uboot",
113 .size = SZ_256K,
114 .offset = 0,
115 .mask_flags = MTD_WRITEABLE,
116 }, {
117 .name = "params",
118 .size = SZ_128K,
119 .offset = SZ_256K,
120 }, {
121 .name = "kernel",
122 .size = SZ_2M,
123 .offset = SZ_256K + SZ_128K,
124 }, {
125 .name = "rootfs",
126 .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
127 .offset = SZ_256K + SZ_128K + SZ_2M,
128 },
129 };
130
131 static struct physmap_flash_data laguna_nor_pdata = {
132 .width = 2,
133 .parts = laguna_nor_partitions,
134 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
135 };
136
137 static struct resource laguna_nor_res = {
138 .start = CNS3XXX_FLASH_BASE,
139 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
140 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
141 };
142
143 static struct platform_device laguna_nor_pdev = {
144 .name = "physmap-flash",
145 .id = 0,
146 .resource = &laguna_nor_res,
147 .num_resources = 1,
148 .dev = {
149 .platform_data = &laguna_nor_pdata,
150 },
151 };
152
153 /*
154 * SPI
155 */
156 static struct mtd_partition laguna_spi_partitions[] = {
157 {
158 .name = "uboot",
159 .size = SZ_256K,
160 .offset = 0,
161 .mask_flags = MTD_WRITEABLE,
162 }, {
163 .name = "params",
164 .size = SZ_256K,
165 .offset = SZ_256K,
166 }, {
167 .name = "kernel",
168 .size = SZ_1M + SZ_512K,
169 .offset = SZ_512K,
170 }, {
171 .name = "rootfs",
172 .size = SZ_16M - SZ_2M,
173 .offset = SZ_2M,
174 },
175 };
176
177 static struct flash_platform_data laguna_spi_pdata = {
178 .parts = laguna_spi_partitions,
179 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
180 };
181
182 static struct spi_board_info __initdata laguna_spi_devices[] = {
183 {
184 .modalias = "m25p80",
185 .platform_data = &laguna_spi_pdata,
186 .max_speed_hz = 50000000,
187 .bus_num = 1,
188 .chip_select = 0,
189 },
190 };
191
192 static struct platform_device laguna_spi_controller = {
193 .name = "cns3xxx_spi",
194 };
195
196 /*
197 * LED's
198 */
199 static struct gpio_led laguna_gpio_leds[] = {
200 {
201 .name = "user1", /* Green Led */
202 .gpio = 115,
203 .active_low = 1,
204 },{
205 .name = "user2", /* Red Led */
206 .gpio = 114,
207 .active_low = 1,
208 },{
209 .name = "pwr1", /* Green Led */
210 .gpio = 116,
211 .active_low = 1,
212 },{
213 .name = "pwr2", /* Yellow Led */
214 .gpio = 117,
215 .active_low = 1,
216 },{
217 .name = "txd1", /* Green Led */
218 .gpio = 118,
219 .active_low = 1,
220 },{
221 .name = "txd2", /* Yellow Led */
222 .gpio = 119,
223 .active_low = 1,
224 },{
225 .name = "rxd1", /* Green Led */
226 .gpio = 120,
227 .active_low = 1,
228 },{
229 .name = "rxd2", /* Yellow Led */
230 .gpio = 121,
231 .active_low = 1,
232 },{
233 .name = "ser1", /* Green Led */
234 .gpio = 122,
235 .active_low = 1,
236 },{
237 .name = "ser2", /* Yellow Led */
238 .gpio = 123,
239 .active_low = 1,
240 },{
241 .name = "enet1", /* Green Led */
242 .gpio = 124,
243 .active_low = 1,
244 },{
245 .name = "enet2", /* Yellow Led */
246 .gpio = 125,
247 .active_low = 1,
248 },{
249 .name = "sig1_1", /* Green Led */
250 .gpio = 126,
251 .active_low = 1,
252 },{
253 .name = "sig1_2", /* Yellow Led */
254 .gpio = 127,
255 .active_low = 1,
256 },{
257 .name = "sig2_1", /* Green Led */
258 .gpio = 128,
259 .active_low = 1,
260 },{
261 .name = "sig2_2", /* Yellow Led */
262 .gpio = 129,
263 .active_low = 1,
264 },{
265 .name = "sig3_1", /* Green Led */
266 .gpio = 130,
267 .active_low = 1,
268 },{
269 .name = "sig3_2", /* Yellow Led */
270 .gpio = 131,
271 .active_low = 1,
272 },{
273 .name = "net1", /*Green Led */
274 .gpio = 109,
275 .active_low = 1,
276 },{
277 .name = "net2", /* Red Led */
278 .gpio = 110,
279 .active_low = 1,
280 },{
281 .name = "mod1", /* Green Led */
282 .gpio = 111,
283 .active_low = 1,
284 },{
285 .name = "mod2", /* Red Led */
286 .gpio = 112,
287 .active_low = 1,
288 },
289 };
290
291 static struct gpio_led_platform_data laguna_gpio_leds_data = {
292 .num_leds = 22,
293 .leds = laguna_gpio_leds,
294 };
295
296 static struct platform_device laguna_gpio_leds_device = {
297 .name = "leds-gpio",
298 .id = -1,
299 .dev.platform_data = &laguna_gpio_leds_data,
300 };
301
302 /*
303 * Ethernet
304 */
305 static struct cns3xxx_plat_info laguna_net_data = {
306 .ports = 0,
307 .phy = {
308 0,
309 1,
310 2,
311 },
312 };
313
314 static struct platform_device laguna_net_device = {
315 .name = "cns3xxx_eth",
316 .id = 0,
317 .dev.platform_data = &laguna_net_data,
318 };
319
320 /*
321 * UART
322 */
323 static void __init laguna_early_serial_setup(void)
324 {
325 #ifdef CONFIG_SERIAL_8250_CONSOLE
326 static struct uart_port laguna_serial_port = {
327 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
328 .mapbase = CNS3XXX_UART0_BASE,
329 .irq = IRQ_CNS3XXX_UART0,
330 .iotype = UPIO_MEM,
331 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
332 .regshift = 2,
333 .uartclk = 24000000,
334 .line = 0,
335 .type = PORT_16550A,
336 .fifosize = 16,
337 };
338
339 early_serial_setup(&laguna_serial_port);
340 #endif
341 }
342
343 static struct resource laguna_uart_resources[] = {
344 {
345 .start = CNS3XXX_UART0_BASE,
346 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
347 .flags = IORESOURCE_MEM
348 },{
349 .start = CNS3XXX_UART2_BASE,
350 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
351 .flags = IORESOURCE_MEM
352 },{
353 .start = CNS3XXX_UART2_BASE,
354 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
355 .flags = IORESOURCE_MEM
356 },
357 };
358
359 static struct plat_serial8250_port laguna_uart_data[] = {
360 {
361 .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
362 .mapbase = (CNS3XXX_UART0_BASE),
363 .irq = IRQ_CNS3XXX_UART0,
364 .iotype = UPIO_MEM,
365 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
366 .regshift = 2,
367 .uartclk = 24000000,
368 .type = PORT_16550A,
369 },{
370 .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
371 .mapbase = (CNS3XXX_UART1_BASE),
372 .irq = IRQ_CNS3XXX_UART1,
373 .iotype = UPIO_MEM,
374 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
375 .regshift = 2,
376 .uartclk = 24000000,
377 .type = PORT_16550A,
378 },{
379 .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
380 .mapbase = (CNS3XXX_UART2_BASE),
381 .irq = IRQ_CNS3XXX_UART2,
382 .iotype = UPIO_MEM,
383 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
384 .regshift = 2,
385 .uartclk = 24000000,
386 .type = PORT_16550A,
387 },
388 { },
389 };
390
391 static struct platform_device laguna_uart = {
392 .name = "serial8250",
393 .id = PLAT8250_DEV_PLATFORM,
394 .dev.platform_data = laguna_uart_data,
395 .num_resources = 3,
396 .resource = laguna_uart_resources
397 };
398
399 /*
400 * USB
401 */
402 static struct resource cns3xxx_usb_ehci_resources[] = {
403 [0] = {
404 .start = CNS3XXX_USB_BASE,
405 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = IRQ_CNS3XXX_USB_EHCI,
410 .flags = IORESOURCE_IRQ,
411 },
412 };
413
414 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
415
416 static struct platform_device cns3xxx_usb_ehci_device = {
417 .name = "cns3xxx-ehci",
418 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
419 .resource = cns3xxx_usb_ehci_resources,
420 .dev = {
421 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
422 .coherent_dma_mask = DMA_BIT_MASK(32),
423 },
424 };
425
426 static struct resource cns3xxx_usb_ohci_resources[] = {
427 [0] = {
428 .start = CNS3XXX_USB_OHCI_BASE,
429 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
430 .flags = IORESOURCE_MEM,
431 },
432 [1] = {
433 .start = IRQ_CNS3XXX_USB_OHCI,
434 .flags = IORESOURCE_IRQ,
435 },
436 };
437
438 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
439
440 static struct platform_device cns3xxx_usb_ohci_device = {
441 .name = "cns3xxx-ohci",
442 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
443 .resource = cns3xxx_usb_ohci_resources,
444 .dev = {
445 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
446 .coherent_dma_mask = DMA_BIT_MASK(32),
447 },
448 };
449
450 static struct resource cns3xxx_usb_otg_resources[] = {
451 [0] = {
452 .start = CNS3XXX_USBOTG_BASE,
453 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
454 .flags = IORESOURCE_MEM,
455 },
456 [1] = {
457 .start = IRQ_CNS3XXX_USB_OTG,
458 .flags = IORESOURCE_IRQ,
459 },
460 };
461
462 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
463
464 static struct platform_device cns3xxx_usb_otg_device = {
465 .name = "dwc_otg",
466 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
467 .resource = cns3xxx_usb_otg_resources,
468 .dev = {
469 .dma_mask = &cns3xxx_usb_otg_dma_mask,
470 .coherent_dma_mask = DMA_BIT_MASK(32),
471 },
472 };
473
474 /*
475 * I2C
476 */
477 static struct resource laguna_i2c_resource[] = {
478 {
479 .start = CNS3XXX_SSP_BASE + 0x20,
480 .end = 0x7100003f,
481 .flags = IORESOURCE_MEM,
482 },{
483 .start = IRQ_CNS3XXX_I2C,
484 .flags = IORESOURCE_IRQ,
485 },
486 };
487
488 static struct platform_device laguna_i2c_controller = {
489 .name = "cns3xxx-i2c",
490 .num_resources = 2,
491 .resource = laguna_i2c_resource,
492 };
493
494 static struct memory_accessor *at24_mem_acc;
495
496 static void at24_setup(struct memory_accessor *mem_acc, void *context)
497 {
498 char buf[16];
499
500 at24_mem_acc = mem_acc;
501
502 /* Read MAC addresses */
503 if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
504 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
505 if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
506 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
507 if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
508 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
509 if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
510 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
511
512 /* Read out Model Information */
513 if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
514 memcpy(&laguna_info.model, buf, 16);
515 if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
516 memcpy(&laguna_info.nor_flash_size, buf, 1);
517 if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
518 memcpy(&laguna_info.spi_flash_size, buf, 1);
519 if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
520 memcpy(&laguna_info.config_bitmap, buf, 4);
521 if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
522 memcpy(&laguna_info.config2_bitmap, buf, 4);
523 };
524
525 static struct at24_platform_data laguna_eeprom_info = {
526 .byte_len = 1024,
527 .page_size = 16,
528 .flags = AT24_FLAG_READONLY,
529 .setup = at24_setup,
530 };
531
532 static struct pca953x_platform_data laguna_pca_data = {
533 .gpio_base = 100,
534 .irq_base = -1,
535 };
536
537 static struct pca953x_platform_data laguna_pca2_data = {
538 .gpio_base = 116,
539 .irq_base = -1,
540 };
541
542 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
543 {
544 I2C_BOARD_INFO("pca9555", 0x23),
545 .platform_data = &laguna_pca_data,
546 },{
547 I2C_BOARD_INFO("pca9555", 0x27),
548 .platform_data = &laguna_pca2_data,
549 },{
550 I2C_BOARD_INFO("gsp", 0x29),
551 },{
552 I2C_BOARD_INFO ("24c08",0x50),
553 .platform_data = &laguna_eeprom_info,
554 },{
555 I2C_BOARD_INFO("ds1672", 0x68),
556 },
557 };
558
559 /*
560 * Watchdog
561 */
562
563 static struct resource laguna_watchdog_resources[] = {
564 [0] = {
565 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
566 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
567 .flags = IORESOURCE_MEM,
568 },
569 [1] = {
570 .start = IRQ_LOCALWDOG,
571 .end = IRQ_LOCALWDOG,
572 .flags = IORESOURCE_IRQ,
573 }
574 };
575
576 static struct platform_device laguna_watchdog = {
577 .name = "mpcore_wdt",
578 .id = -1,
579 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
580 .resource = laguna_watchdog_resources,
581 };
582
583 /*
584 * GPIO
585 */
586
587 static struct gpio laguna_gpio_gw2391[] = {
588 { 0, GPIOF_IN , "*GPS_PPS" },
589 { 1, GPIOF_IN , "*GSC_IRQ#" },
590 { 2, GPIOF_IN , "*USB_FAULT#" },
591 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
592 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
593 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
594 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
595 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
596 { 100, GPIOF_IN , "*USER_PB#" },
597 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
598 { 108, GPIOF_IN , "DIO0" },
599 { 109, GPIOF_IN , "DIO1" },
600 { 110, GPIOF_IN , "DIO2" },
601 { 111, GPIOF_IN , "DIO3" },
602 { 112, GPIOF_IN , "DIO4" },
603 };
604
605 static struct gpio laguna_gpio_gw2388[] = {
606 { 0, GPIOF_IN , "*GPS_PPS" },
607 { 1, GPIOF_IN , "*GSC_IRQ#" },
608 { 3, GPIOF_IN , "*USB_FAULT#" },
609 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
610 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
611 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
612 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
613 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
614 { 108, GPIOF_IN , "DIO0" },
615 { 109, GPIOF_IN , "DIO1" },
616 { 110, GPIOF_IN , "DIO2" },
617 { 111, GPIOF_IN , "DIO3" },
618 { 112, GPIOF_IN , "DIO4" },
619 };
620
621 static struct gpio laguna_gpio_gw2387[] = {
622 { 0, GPIOF_IN , "*GPS_PPS" },
623 { 1, GPIOF_IN , "*GSC_IRQ#" },
624 { 2, GPIOF_IN , "*USB_FAULT#" },
625 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
626 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
627 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
628 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
629 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
630 { 100, GPIOF_IN , "*USER_PB#" },
631 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
632 { 108, GPIOF_IN , "DIO0" },
633 { 109, GPIOF_IN , "DIO1" },
634 { 110, GPIOF_IN , "DIO2" },
635 { 111, GPIOF_IN , "DIO3" },
636 { 112, GPIOF_IN , "DIO4" },
637 { 113, GPIOF_IN , "DIO5" },
638 };
639
640 static struct gpio laguna_gpio_gw2384[] = {
641 { 0, GPIOF_IN , "*GSC_IRQ#" },
642 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
643 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
644 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
645 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
646 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
647 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
648 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
649 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
650 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
651 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
652 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
653 { 100, GPIOF_IN , "*USER_PB#" },
654 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
655 { 108, GPIOF_IN , "J9_DIOGSC0" },
656 };
657
658 static struct gpio laguna_gpio_gw2383[] = {
659 { 0, GPIOF_IN , "*GPS_PPS" },
660 { 1, GPIOF_IN , "*GSC_IRQ#" },
661 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
662 { 3, GPIOF_IN , "GPIO0" },
663 { 8, GPIOF_IN , "GPIO1" },
664 { 100, GPIOF_IN , "DIO0" },
665 { 101, GPIOF_IN , "DIO1" },
666 };
667
668 static struct gpio laguna_gpio_gw2382[] = {
669 { 0, GPIOF_IN , "*GPS_PPS" },
670 { 1, GPIOF_IN , "*GSC_IRQ#" },
671 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
672 { 3, GPIOF_IN , "GPIO0" },
673 { 4, GPIOF_IN , "GPIO1" },
674 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
675 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
676 { 100, GPIOF_IN , "DIO0" },
677 { 101, GPIOF_IN , "DIO1" },
678 };
679
680 static struct gpio laguna_gpio_gw2380[] = {
681 { 0, GPIOF_IN , "*GPS_PPS" },
682 { 1, GPIOF_IN , "*GSC_IRQ#" },
683 { 3, GPIOF_IN , "GPIO0" },
684 { 8, GPIOF_IN , "GPIO1" },
685 { 100, GPIOF_IN , "DIO0" },
686 { 101, GPIOF_IN , "DIO1" },
687 { 102, GPIOF_IN , "DIO2" },
688 { 103, GPIOF_IN , "DIO3" },
689 };
690
691 /*
692 * Initialization
693 */
694 static void __init laguna_init(void)
695 {
696 cns3xxx_l2x0_init();
697
698 platform_device_register(&laguna_watchdog);
699
700 platform_device_register(&laguna_i2c_controller);
701
702 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
703
704 pm_power_off = cns3xxx_power_off;
705 }
706
707 static struct map_desc laguna_io_desc[] __initdata = {
708 {
709 .virtual = CNS3XXX_UART0_BASE_VIRT,
710 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
711 .length = SZ_4K,
712 .type = MT_DEVICE,
713 },{
714 .virtual = CNS3XXX_UART1_BASE_VIRT,
715 .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
716 .length = SZ_4K,
717 .type = MT_DEVICE,
718 },{
719 .virtual = CNS3XXX_UART2_BASE_VIRT,
720 .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
721 .length = SZ_4K,
722 .type = MT_DEVICE,
723 },
724 };
725
726 static void __init laguna_map_io(void)
727 {
728 cns3xxx_common_init();
729 cns3xxx_pcie_iotable_init();
730 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
731 laguna_early_serial_setup();
732 }
733
734 static int laguna_register_gpio(struct gpio *array, size_t num)
735 {
736 int i, err, ret;
737
738 ret = 0;
739 for (i = 0; i < num; i++, array++) {
740 const char *label = array->label;
741 if (label[0] == '*')
742 label++;
743 err = gpio_request_one(array->gpio, array->flags, label);
744 if (err)
745 ret = err;
746 else {
747 err = gpio_export(array->gpio, array->label[0] != '*');
748 }
749 }
750 return ret;
751 }
752
753 static int __init laguna_pcie_init(void)
754 {
755 if (!machine_is_gw2388())
756 return 0;
757
758 return cns3xxx_pcie_init();
759 }
760 subsys_initcall(laguna_pcie_init);
761
762 static int __init laguna_model_setup(void)
763 {
764 u32 __iomem *mem;
765 u32 reg;
766
767 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
768 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
769 NR_IRQS_CNS3XXX);
770 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
771 NR_IRQS_CNS3XXX + 32);
772
773 if (strncmp(laguna_info.model, "GW", 2) == 0) {
774 if (laguna_info.config_bitmap & ETH0_LOAD)
775 laguna_net_data.ports |= BIT(0);
776 if (laguna_info.config_bitmap & ETH1_LOAD)
777 laguna_net_data.ports |= BIT(1);
778 if (laguna_info.config_bitmap & ETH2_LOAD)
779 laguna_net_data.ports |= BIT(2);
780 if (laguna_net_data.ports)
781 platform_device_register(&laguna_net_device);
782
783 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
784 (laguna_info.config_bitmap & SATA1_LOAD))
785 cns3xxx_ahci_init();
786
787 if (laguna_info.config_bitmap & (USB0_LOAD)) {
788 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
789
790 /* DRVVBUS pins share with GPIOA */
791 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
792 reg = __raw_readl(mem);
793 reg |= 0x8;
794 __raw_writel(reg, mem);
795
796 /* Enable OTG */
797 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
798 reg = __raw_readl(mem);
799 reg &= ~(1 << 10);
800 __raw_writel(reg, mem);
801
802 platform_device_register(&cns3xxx_usb_otg_device);
803 }
804
805 if (laguna_info.config_bitmap & (USB1_LOAD)) {
806 platform_device_register(&cns3xxx_usb_ehci_device);
807 platform_device_register(&cns3xxx_usb_ohci_device);
808 }
809
810 if (laguna_info.config_bitmap & (SD_LOAD))
811 cns3xxx_sdhci_init();
812
813 if (laguna_info.config_bitmap & (UART0_LOAD))
814 laguna_uart.num_resources = 1;
815 if (laguna_info.config_bitmap & (UART1_LOAD))
816 laguna_uart.num_resources = 2;
817 if (laguna_info.config_bitmap & (UART2_LOAD))
818 laguna_uart.num_resources = 3;
819 platform_device_register(&laguna_uart);
820
821 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
822 switch (laguna_info.nor_flash_size) {
823 case 1:
824 laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
825 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
826 break;
827 case 2:
828 laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
829 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
830 break;
831 case 3:
832 laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
833 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
834 break;
835 case 4:
836 laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
837 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
838 break;
839 case 5:
840 laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
841 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
842 break;
843 }
844 platform_device_register(&laguna_nor_pdev);
845 }
846
847 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
848 switch (laguna_info.spi_flash_size) {
849 case 1:
850 laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
851 break;
852 case 2:
853 laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
854 break;
855 case 3:
856 laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
857 break;
858 case 4:
859 laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
860 break;
861 case 5:
862 laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
863 break;
864 }
865 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
866 }
867
868 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
869 (laguna_info.config_bitmap & SPI1_LOAD))
870 platform_device_register(&laguna_spi_controller);
871
872 /*
873 * Do any model specific setup not known by the bitmap by matching
874 * the first 6 characters of the model name
875 */
876
877 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
878 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
879 {
880 // configure GPIO's
881 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
882 // configure LED's
883 laguna_gpio_leds_data.num_leds = 2;
884 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
885 // configure GPIO's
886 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
887 // configure LED's
888 laguna_gpio_leds_data.num_leds = 2;
889 } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
890 // configure GPIO's
891 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
892 // configure LED's
893 laguna_gpio_leds_data.num_leds = 1;
894 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
895 // configure GPIO's
896 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
897 // configure LED's
898 laguna_gpio_leds[0].gpio = 107;
899 laguna_gpio_leds_data.num_leds = 1;
900 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
901 // configure GPIO's
902 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
903 // configure LED's
904 laguna_gpio_leds[0].gpio = 107;
905 laguna_gpio_leds_data.num_leds = 1;
906 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
907 // configure GPIO's
908 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
909 // configure LED's
910 laguna_gpio_leds[0].gpio = 107;
911 laguna_gpio_leds[1].gpio = 106;
912 laguna_gpio_leds_data.num_leds = 2;
913 } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
914 // configure GPIO's
915 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
916 // configure LED's
917 laguna_gpio_leds_data.num_leds = 2;
918 }
919 platform_device_register(&laguna_gpio_leds_device);
920 } else {
921 // Do some defaults here, not sure what yet
922 }
923 return 0;
924 }
925 late_initcall(laguna_model_setup);
926
927 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
928 .atag_offset = 0x100,
929 .map_io = laguna_map_io,
930 .init_irq = cns3xxx_init_irq,
931 .timer = &cns3xxx_timer,
932 .handle_irq = gic_handle_irq,
933 .init_machine = laguna_init,
934 .restart = cns3xxx_restart,
935 MACHINE_END
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