target/linux/cns3xxx/patches-3.14/095-gpio_support.patch

   1 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
   2 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
   3 @@ -245,6 +245,10 @@ static void __init cns3420_init(void)
   4
   5         cns3xxx_ahci_init();
   6         cns3xxx_sdhci_init();
   7 +       cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
   8 +               NR_IRQS_CNS3XXX);
   9 +       cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
  10 +               NR_IRQS_CNS3XXX + 32);
  11
  12         pm_power_off = cns3xxx_power_off;
  13  }
  14 --- a/arch/arm/mach-cns3xxx/core.h
  15 +++ b/arch/arm/mach-cns3xxx/core.h
  16 @@ -17,12 +17,6 @@ extern struct smp_operations cns3xxx_smp
  17  extern void cns3xxx_timer_init(void);
  18  extern void cns3xxx_pcie_iotable_init(void);
  19
  20 -#ifdef CONFIG_CACHE_L2X0
  21 -void __init cns3xxx_l2x0_init(void);
  22 -#else
  23 -static inline void cns3xxx_l2x0_init(void) {}
  24 -#endif /* CONFIG_CACHE_L2X0 */
  25 -
  26  void __init cns3xxx_map_io(void);
  27  void __init cns3xxx_init_irq(void);
  28  int  __init cns3xxx_pcie_init(void);
  29 --- a/arch/arm/mach-cns3xxx/Kconfig
  30 +++ b/arch/arm/mach-cns3xxx/Kconfig
  31 @@ -2,6 +2,8 @@ config ARCH_CNS3XXX
  32         bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
  33         select ARM_GIC
  34         select CPU_V6K
  35 +       select ARCH_REQUIRE_GPIOLIB
  36 +       select GENERIC_IRQ_CHIP
  37         select GENERIC_CLOCKEVENTS
  38         select MIGHT_HAVE_CACHE_L2X0
  39         select MIGHT_HAVE_PCI
  40 --- a/arch/arm/mach-cns3xxx/Makefile
  41 +++ b/arch/arm/mach-cns3xxx/Makefile
  42 @@ -1,7 +1,7 @@
  43  ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
  44
  45  obj-$(CONFIG_ARCH_CNS3XXX)             += cns3xxx.o
  46 -cns3xxx-y                              += core.o pm.o
  47 +cns3xxx-y                              += core.o pm.o gpio.o
  48  cns3xxx-$(CONFIG_ATAGS)                        += devices.o
  49  cns3xxx-$(CONFIG_PCI)                  += pcie.o
  50  cns3xxx-$(CONFIG_MACH_CNS3420VB)       += cns3420vb.o
  51 --- a/arch/arm/mach-cns3xxx/cns3xxx.h
  52 +++ b/arch/arm/mach-cns3xxx/cns3xxx.h
  53 @@ -68,8 +68,10 @@
  54  #define SMC_PCELL_ID_3_OFFSET                  0xFFC
  55
  56  #define CNS3XXX_GPIOA_BASE                     0x74000000      /* GPIO port A */
  57 +#define CNS3XXX_GPIOA_BASE_VIRT                        0xFB006000
  58
  59  #define CNS3XXX_GPIOB_BASE                     0x74800000      /* GPIO port B */
  60 +#define CNS3XXX_GPIOB_BASE_VIRT                        0xFB007000
  61
  62  #define CNS3XXX_RTC_BASE                       0x75000000      /* Real Time Clock */
  63
  64 --- a/arch/arm/mach-cns3xxx/core.c
  65 +++ b/arch/arm/mach-cns3xxx/core.c
  66 @@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[]
  67                 .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
  68                 .length         = SZ_16M,
  69                 .type           = MT_DEVICE,
  70 +       }, {
  71 +               .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
  72 +               .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
  73 +               .length         = SZ_4K,
  74 +               .type           = MT_DEVICE,
  75 +       }, {
  76 +               .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
  77 +               .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
  78 +               .length         = SZ_4K,
  79 +               .type           = MT_DEVICE,
  80         },
  81  };
  82