target/linux/cns3xxx/patches-3.14/120-backport_pcie_topology_fix.patch

   1 --- a/arch/arm/mach-cns3xxx/pcie.c
   2 +++ b/arch/arm/mach-cns3xxx/pcie.c
   3 @@ -71,7 +71,7 @@ static void __iomem *cns3xxx_pci_cfg_bas
   4         void __iomem *base;
   5
   6         /* If there is no link, just show the CNS PCI bridge. */
   7 -       if (!cnspci->linked && (busno > 0 || slot > 0))
   8 +       if (!cnspci->linked && (busno > 0))
   9                 return NULL;
  10
  11         /*
  12 @@ -80,15 +80,19 @@ static void __iomem *cns3xxx_pci_cfg_bas
  13          * the first device on the same bus as the CNS PCI bridge.
  14          */
  15         if (busno == 0) {
  16 -               if (slot > 1)
  17 +               type = CNS3XXX_HOST_TYPE;
  18 +               if (devfn)
  19 +                       return NULL;
  20 +       } else if (busno == 1) {
  21 +               type = CNS3XXX_CFG0_TYPE;
  22 +               if (slot)
  23                         return NULL;
  24 -               type = slot;
  25         } else {
  26                 type = CNS3XXX_CFG1_TYPE;
  27         }
  28
  29         base = (void __iomem *)cnspci->cfg_bases[type].virtual;
  30 -       offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
  31 +       offset = (devfn << 12) | (where & 0xffc);
  32
  33         return base + offset;
  34  }
  35 @@ -256,7 +260,7 @@ static struct pci_ops cns3xxx_pcie_ops =
  36  static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  37  {
  38         struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
  39 -       int irq = cnspci->irqs[slot+pin-1];
  40 +       int irq = cnspci->irqs[!!dev->bus->number+pin-1];
  41
  42         pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
  43                 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
  44 @@ -434,7 +438,8 @@ static void __init cns3xxx_pcie_hw_init(
  45                 return;
  46
  47         /* Set Device Max_Read_Request_Size to 128 byte */
  48 -       devfn = PCI_DEVFN(1, 0);
  49 +       bus.number = 1;
  50 +       devfn = PCI_DEVFN(0, 0);
  51         pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
  52         pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
  53         dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */