projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mac80211: make it work with 3.18.12+
[openwrt/openwrt.git] / target / linux / gemini / patches-3.18 / 120-net-add-gemini-gmac-driver.patch
1 --- /dev/null
2 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
3 @@ -0,0 +1,21 @@
4 +/*
5 + * Gemini GMAC specific defines
6 + *
7 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@gmail.com>
8 + *
9 + * This program is free software; you can redistribute it and/or modify
10 + * it under the terms of the GNU General Public License as published by
11 + * the Free Software Foundation; either version 2 of the License, or
12 + * (at your option) any later version.
13 + */
14 +#ifndef __NET_GEMINI_PLATFORM_H__
15 +#define __NET_GEMINI_PLATFORM_H__
16 +
17 +#include <linux/phy.h>
18 +
19 +struct gemini_gmac_platform_data {
20 + char *bus_id[2]; /* NULL means that this port is not used */
21 + phy_interface_t interface[2];
22 +};
23 +
24 +#endif /* __NET_GEMINI_PLATFORM_H__ */
25 --- a/arch/arm/mach-gemini/common.h 2011-04-19 03:05:29.446367900 +0200
26 +++ b/arch/arm/mach-gemini/common.h 2011-04-19 03:07:02.191154293 +0200
27 @@ -13,6 +13,7 @@
28 #define __GEMINI_COMMON_H__
29
30 struct mtd_partition;
31 +struct gemini_gmac_platform_data;
32
33 extern void gemini_map_io(void);
34 extern void gemini_init_irq(void);
35 @@ -26,6 +27,7 @@
36 struct mtd_partition *parts,
37 unsigned int nr_parts);
38 extern int platform_register_watchdog(void);
39 +extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
40
41 extern void gemini_restart(enum reboot_mode mode, const char *cmd);
42
43 --- a/arch/arm/mach-gemini/devices.c 2011-04-21 13:01:53.578121892 +0200
44 +++ b/arch/arm/mach-gemini/devices.c 2011-04-21 13:14:27.643158445 +0200
45 @@ -17,6 +17,7 @@
46 #include <mach/irqs.h>
47 #include <mach/hardware.h>
48 #include <mach/global_reg.h>
49 +#include <mach/gmac.h>
50 #include "common.h"
51
52 static struct plat_serial8250_port serial_platform_data[] = {
53 @@ -134,3 +134,56 @@
54 {
55 return platform_device_register(&wdt_device);
56 }
57 +
58 +static struct resource gmac_resources[] = {
59 + {
60 + .start = GEMINI_TOE_BASE,
61 + .end = GEMINI_TOE_BASE + 0xffff,
62 + .flags = IORESOURCE_MEM,
63 + },
64 + {
65 + .start = IRQ_GMAC0,
66 + .end = IRQ_GMAC0,
67 + .flags = IORESOURCE_IRQ,
68 + },
69 + {
70 + .start = IRQ_GMAC1,
71 + .end = IRQ_GMAC1,
72 + .flags = IORESOURCE_IRQ,
73 + },
74 +};
75 +
76 +static u64 gmac_dmamask = 0xffffffffUL;
77 +
78 +static struct platform_device ethernet_device = {
79 + .name = "gmac-gemini",
80 + .id = 0,
81 + .dev = {
82 + .dma_mask = &gmac_dmamask,
83 + .coherent_dma_mask = 0xffffffff,
84 + },
85 + .num_resources = ARRAY_SIZE(gmac_resources),
86 + .resource = gmac_resources,
87 +};
88 +
89 +int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
90 +{
91 + unsigned int reg;
92 +
93 + reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
94 + GLOBAL_MISC_CTRL));
95 +
96 + reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
97 +
98 + if (pdata->bus_id[1])
99 + reg |= GMAC_1_ENABLE;
100 + else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
101 + reg |= GMAC_GMII;
102 +
103 + writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
104 + GLOBAL_MISC_CTRL));
105 +
106 + ethernet_device.dev.platform_data = pdata;
107 +
108 + return platform_device_register(&ethernet_device);
109 +}
110
111 --- a/drivers/net/ethernet/Kconfig 2012-01-25 22:19:43.633736456 +0100
112 +++ b/drivers/net/ethernet/Kconfig 2012-01-25 22:20:28.582730742 +0100
113 @@ -70,6 +70,7 @@
114 source "drivers/net/ethernet/faraday/Kconfig"
115 source "drivers/net/ethernet/freescale/Kconfig"
116 source "drivers/net/ethernet/fujitsu/Kconfig"
117 +source "drivers/net/ethernet/gemini/Kconfig"
118 source "drivers/net/ethernet/hisilicon/Kconfig"
119 source "drivers/net/ethernet/hp/Kconfig"
120 source "drivers/net/ethernet/ibm/Kconfig"
121 --- a/drivers/net/ethernet/Makefile 2012-01-27 01:37:10.839114389 +0100
122 +++ b/drivers/net/ethernet/Makefile 2012-01-27 01:39:06.102105027 +0100
123 @@ -33,6 +33,7 @@
124 obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/
125 obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/
126 obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/
127 +obj-$(CONFIG_NET_VENDOR_GEMINI) += gemini/
128 obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/
129 obj-$(CONFIG_NET_VENDOR_HP) += hp/
130 obj-$(CONFIG_NET_VENDOR_IBM) += ibm/
131 --- /dev/null 2012-01-23 21:36:48.249769447 +0100
132 +++ b/drivers/net/ethernet/gemini/Kconfig 2012-01-25 22:16:44.285740226 +0100
133 @@ -0,0 +1,31 @@
134 +#
135 +# Gemini device configuration
136 +#
137 +
138 +config NET_VENDOR_GEMINI
139 + bool "Cortina Gemini devices"
140 + default y
141 + depends on ARCH_GEMINI
142 + ---help---
143 + If you have a network (Ethernet) card belonging to this class, say Y
144 + and read the Ethernet-HOWTO, available from
145 + <http://www.tldp.org/docs.html#howto>.
146 +
147 + Note that the answer to this question doesn't directly affect the
148 + kernel: saying N will just cause the configurator to skip all
149 + the questions about D-Link devices. If you say Y, you will be asked for
150 + your specific card in the following questions.
151 +
152 +if NET_VENDOR_GEMINI
153 +
154 +config GEMINI_SL351X
155 + tristate "StorLink SL351x Gigabit Ethernet support"
156 + depends on ARCH_GEMINI
157 + select PHYLIB
158 + select MDIO_BITBANG
159 + select MDIO_GPIO
160 + select CRC32
161 + ---help---
162 + This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
163 +
164 +endif # NET_VENDOR_GEMINI
165 --- /dev/null 2012-01-23 21:36:48.249769447 +0100
166 +++ b/drivers/net/ethernet/gemini/Makefile 2012-01-25 22:17:29.698741496 +0100
167 @@ -0,0 +1,5 @@
168 +#
169 +# Makefile for the Cortina Gemini network device drivers.
170 +#
171 +
172 +obj-$(CONFIG_GEMINI_SL351X) += sl351x.o
173 --- /dev/null 2012-01-23 21:36:48.249769447 +0100
174 +++ b/drivers/net/ethernet/gemini/sl351x.c 2012-01-27 17:09:51.000000000 +0100
175 @@ -0,0 +1,2340 @@
176 +/*
177 + * Ethernet device driver for Gemini SoC (SL351x GMAC).
178 + *
179 + * Copyright (C) 2011, Tobias Waldvogel <tobias.waldvogel@gmail.com>
180 + *
181 + * Based on work by Michał Mirosław <mirq-linux@rere.qmqm.pl> and
182 + * Paulius Zaleckas <paulius.zaleckas@gmail.com> and
183 + * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it> and
184 + * GPLd spaghetti code from Raidsonic and other Gemini-based NAS vendors.
185 + *
186 + * This program is free software; you can redistribute it and/or modify
187 + * it under the terms of the GNU General Public License as published by
188 + * the Free Software Foundation; either version 2 of the License, or
189 + * (at your option) any later version.
190 + */
191 +
192 +#include <linux/module.h>
193 +#include <linux/kernel.h>
194 +#include <linux/init.h>
195 +
196 +#include <linux/spinlock.h>
197 +#include <linux/slab.h>
198 +#include <linux/dma-mapping.h>
199 +#include <linux/cache.h>
200 +#include <linux/interrupt.h>
201 +
202 +#include <linux/platform_device.h>
203 +#include <linux/etherdevice.h>
204 +#include <linux/if_vlan.h>
205 +#include <linux/skbuff.h>
206 +#include <linux/phy.h>
207 +#include <linux/crc32.h>
208 +#include <linux/ethtool.h>
209 +#include <linux/tcp.h>
210 +#include <linux/u64_stats_sync.h>
211 +
212 +#include <linux/in.h>
213 +#include <linux/ip.h>
214 +#include <linux/ipv6.h>
215 +
216 +#include <mach/hardware.h>
217 +#include <mach/global_reg.h>
218 +
219 +#include <mach/gmac.h>
220 +#include "sl351x_hw.h"
221 +
222 +#define DRV_NAME "gmac-gemini"
223 +#define DRV_VERSION "1.0"
224 +
225 +#define HSIZE_8 0b00
226 +#define HSIZE_16 0b01
227 +#define HSIZE_32 0b10
228 +
229 +#define HBURST_SINGLE 0b00
230 +#define HBURST_INCR 0b01
231 +#define HBURST_INCR4 0b10
232 +#define HBURST_INCR8 0b11
233 +
234 +#define HPROT_DATA_CACHE BIT(0)
235 +#define HPROT_PRIVILIGED BIT(1)
236 +#define HPROT_BUFFERABLE BIT(2)
237 +#define HPROT_CACHABLE BIT(3)
238 +
239 +#define DEFAULT_RX_COALESCE_NSECS 0
240 +#define DEFAULT_GMAC_RXQ_ORDER 9
241 +#define DEFAULT_GMAC_TXQ_ORDER 8
242 +#define DEFAULT_RX_BUF_ORDER 11
243 +#define DEFAULT_NAPI_WEIGHT 64
244 +#define TX_MAX_FRAGS 16
245 +#define TX_QUEUE_NUM 1 /* max: 6 */
246 +#define RX_MAX_ALLOC_ORDER 2
247 +
248 +#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \
249 + GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT)
250 +#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT| \
251 + GMAC0_SWTQ00_FIN_INT_BIT)
252 +#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT|GMAC0_RX_OVERRUN_INT_BIT)
253 +
254 +#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
255 + NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
256 + NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
257 +
258 +MODULE_AUTHOR("Tobias Waldvogel");
259 +MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
260 +MODULE_LICENSE("GPL");
261 +MODULE_ALIAS("platform:" DRV_NAME);
262 +
263 +struct toe_private {
264 + void __iomem *iomem;
265 + spinlock_t irq_lock;
266 +
267 + struct net_device *netdev[2];
268 + __le32 mac_addr[2][3];
269 +
270 + struct device *dev;
271 + int irq;
272 +
273 + unsigned int freeq_order;
274 + unsigned int freeq_frag_order;
275 + GMAC_RXDESC_T *freeq_ring;
276 + dma_addr_t freeq_dma_base;
277 + struct page **freeq_page_tab;
278 + spinlock_t freeq_lock;
279 +};
280 +
281 +struct gmac_txq {
282 + GMAC_TXDESC_T *ring;
283 + struct sk_buff **skb;
284 + unsigned int cptr;
285 + unsigned int noirq_packets;
286 +};
287 +
288 +struct gmac_private {
289 + unsigned int num;
290 + struct toe_private *toe;
291 + void __iomem *ctl_iomem;
292 + void __iomem *dma_iomem;
293 +
294 + void __iomem *rxq_rwptr;
295 + GMAC_RXDESC_T *rxq_ring;
296 + unsigned int rxq_order;
297 +
298 + struct napi_struct napi;
299 + struct hrtimer rx_coalesce_timer;
300 + unsigned int rx_coalesce_nsecs;
301 + unsigned int freeq_refill;
302 + struct gmac_txq txq[TX_QUEUE_NUM];
303 + unsigned int txq_order;
304 + unsigned int irq_every_tx_packets;
305 +
306 + dma_addr_t rxq_dma_base;
307 + dma_addr_t txq_dma_base;
308 +
309 + unsigned int msg_enable;
310 + spinlock_t config_lock;
311 +
312 + struct u64_stats_sync tx_stats_syncp;
313 + struct u64_stats_sync rx_stats_syncp;
314 + struct u64_stats_sync ir_stats_syncp;
315 +
316 + struct rtnl_link_stats64 stats;
317 + u64 hw_stats[RX_STATS_NUM];
318 + u64 rx_stats[RX_STATUS_NUM];
319 + u64 rx_csum_stats[RX_CHKSUM_NUM];
320 + u64 rx_napi_exits;
321 + u64 tx_frag_stats[TX_MAX_FRAGS];
322 + u64 tx_frags_linearized;
323 + u64 tx_hw_csummed;
324 +};
325 +
326 +#define GMAC_STATS_NUM ( \
327 + RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
328 + TX_MAX_FRAGS + 2)
329 +
330 +static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
331 + "GMAC_IN_DISCARDS",
332 + "GMAC_IN_ERRORS",
333 + "GMAC_IN_MCAST",
334 + "GMAC_IN_BCAST",
335 + "GMAC_IN_MAC1",
336 + "GMAC_IN_MAC2",
337 + "RX_STATUS_GOOD_FRAME",
338 + "RX_STATUS_TOO_LONG_GOOD_CRC",
339 + "RX_STATUS_RUNT_FRAME",
340 + "RX_STATUS_SFD_NOT_FOUND",
341 + "RX_STATUS_CRC_ERROR",
342 + "RX_STATUS_TOO_LONG_BAD_CRC",
343 + "RX_STATUS_ALIGNMENT_ERROR",
344 + "RX_STATUS_TOO_LONG_BAD_ALIGN",
345 + "RX_STATUS_RX_ERR",
346 + "RX_STATUS_DA_FILTERED",
347 + "RX_STATUS_BUFFER_FULL",
348 + "RX_STATUS_11",
349 + "RX_STATUS_12",
350 + "RX_STATUS_13",
351 + "RX_STATUS_14",
352 + "RX_STATUS_15",
353 + "RX_CHKSUM_IP_UDP_TCP_OK",
354 + "RX_CHKSUM_IP_OK_ONLY",
355 + "RX_CHKSUM_NONE",
356 + "RX_CHKSUM_3",
357 + "RX_CHKSUM_IP_ERR_UNKNOWN",
358 + "RX_CHKSUM_IP_ERR",
359 + "RX_CHKSUM_TCP_UDP_ERR",
360 + "RX_CHKSUM_7",
361 + "RX_NAPI_EXITS",
362 + "TX_FRAGS[1]",
363 + "TX_FRAGS[2]",
364 + "TX_FRAGS[3]",
365 + "TX_FRAGS[4]",
366 + "TX_FRAGS[5]",
367 + "TX_FRAGS[6]",
368 + "TX_FRAGS[7]",
369 + "TX_FRAGS[8]",
370 + "TX_FRAGS[9]",
371 + "TX_FRAGS[10]",
372 + "TX_FRAGS[11]",
373 + "TX_FRAGS[12]",
374 + "TX_FRAGS[13]",
375 + "TX_FRAGS[14]",
376 + "TX_FRAGS[15]",
377 + "TX_FRAGS[16+]",
378 + "TX_FRAGS_LINEARIZED",
379 + "TX_HW_CSUMMED",
380 +};
381 +
382 +static void gmac_dump_dma_state(struct net_device *dev);
383 +
384 +static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask)
385 +{
386 + struct gmac_private *gmac = netdev_priv(dev);
387 + unsigned long flags;
388 + u32 reg;
389 +
390 + spin_lock_irqsave(&gmac->config_lock, flags);
391 +
392 + reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
393 + reg = (reg & ~vmask) | val;
394 + writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
395 +
396 + spin_unlock_irqrestore(&gmac->config_lock, flags);
397 +}
398 +
399 +static void gmac_enable_tx_rx(struct net_device *dev)
400 +{
401 + struct gmac_private *gmac = netdev_priv(dev);
402 + void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
403 + unsigned long flags;
404 + u32 reg;
405 +
406 + spin_lock_irqsave(&gmac->config_lock, flags);
407 +
408 + reg = readl(config0);
409 + reg &= ~CONFIG0_TX_RX_DISABLE;
410 + writel(reg, config0);
411 +
412 + spin_unlock_irqrestore(&gmac->config_lock, flags);
413 +}
414 +
415 +static void gmac_disable_tx_rx(struct net_device *dev)
416 +{
417 + struct gmac_private *gmac = netdev_priv(dev);
418 + void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
419 + unsigned long flags;
420 + u32 reg;
421 +
422 + spin_lock_irqsave(&gmac->config_lock, flags);
423 +
424 + reg = readl(config0);
425 + reg |= CONFIG0_TX_RX_DISABLE;
426 + writel(reg, config0);
427 +
428 + spin_unlock_irqrestore(&gmac->config_lock, flags);
429 +
430 + mdelay(10); /* let GMAC consume packet */
431 +}
432 +
433 +static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx)
434 +{
435 + struct gmac_private *gmac = netdev_priv(dev);
436 + void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
437 + unsigned long flags;
438 + u32 reg;
439 +
440 + spin_lock_irqsave(&gmac->config_lock, flags);
441 +
442 + reg = readl(config0);
443 + reg &= ~CONFIG0_FLOW_CTL;
444 + if (tx)
445 + reg |= CONFIG0_FLOW_TX;
446 + if (rx)
447 + reg |= CONFIG0_FLOW_RX;
448 + writel(reg, config0);
449 +
450 + spin_unlock_irqrestore(&gmac->config_lock, flags);
451 +}
452 +
453 +static void gmac_update_link_state(struct net_device *dev)
454 +{
455 + struct gmac_private *gmac = netdev_priv(dev);
456 + void __iomem *status_reg = gmac->ctl_iomem + GMAC_STATUS;
457 + struct phy_device *phydev = dev->phydev;
458 + GMAC_STATUS_T status, old_status;
459 + int pause_tx=0, pause_rx=0;
460 +
461 + old_status.bits32 = status.bits32 = readl(status_reg);
462 +
463 + status.bits.link = phydev->link;
464 + status.bits.duplex = phydev->duplex;
465 +
466 + switch (phydev->speed) {
467 + case 1000:
468 + status.bits.speed = GMAC_SPEED_1000;
469 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
470 + status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
471 + break;
472 + case 100:
473 + status.bits.speed = GMAC_SPEED_100;
474 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
475 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
476 + break;
477 + case 10:
478 + status.bits.speed = GMAC_SPEED_10;
479 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
480 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
481 + break;
482 + default:
483 + netdev_warn(dev, "Not supported PHY speed (%d)\n",
484 + phydev->speed);
485 + }
486 +
487 + if (phydev->duplex == DUPLEX_FULL) {
488 + u16 lcladv = phy_read(phydev, MII_ADVERTISE);
489 + u16 rmtadv = phy_read(phydev, MII_LPA);
490 + u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
491 +
492 + if (cap & FLOW_CTRL_RX)
493 + pause_rx=1;
494 + if (cap & FLOW_CTRL_TX)
495 + pause_tx=1;
496 + }
497 +
498 + gmac_set_flow_control(dev, pause_tx, pause_rx);
499 +
500 + if (old_status.bits32 == status.bits32)
501 + return;
502 +
503 + if (netif_msg_link(gmac)) {
504 + phy_print_status(phydev);
505 + netdev_info(dev, "link flow control: %s\n",
506 + phydev->pause
507 + ? (phydev->asym_pause ? "tx" : "both")
508 + : (phydev->asym_pause ? "rx" : "none")
509 + );
510 + }
511 +
512 + gmac_disable_tx_rx(dev);
513 + writel(status.bits32, status_reg);
514 + gmac_enable_tx_rx(dev);
515 +}
516 +
517 +static int gmac_setup_phy(struct net_device *dev)
518 +{
519 + struct gmac_private *gmac = netdev_priv(dev);
520 + struct toe_private *toe = gmac->toe;
521 + struct gemini_gmac_platform_data *pdata = toe->dev->platform_data;
522 + GMAC_STATUS_T status = { .bits32 = 0 };
523 + int num = dev->dev_id;
524 +
525 + dev->phydev = phy_connect(dev, pdata->bus_id[num],
526 + &gmac_update_link_state, pdata->interface[num]);
527 +
528 + if (IS_ERR(dev->phydev)) {
529 + int err = PTR_ERR(dev->phydev);
530 + dev->phydev = NULL;
531 + return err;
532 + }
533 +
534 + dev->phydev->supported &= PHY_GBIT_FEATURES;
535 + dev->phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
536 + dev->phydev->advertising = dev->phydev->supported;
537 +
538 + /* set PHY interface type */
539 + switch (dev->phydev->interface) {
540 + case PHY_INTERFACE_MODE_MII:
541 + status.bits.mii_rmii = GMAC_PHY_MII;
542 + break;
543 + case PHY_INTERFACE_MODE_GMII:
544 + status.bits.mii_rmii = GMAC_PHY_GMII;
545 + break;
546 + case PHY_INTERFACE_MODE_RGMII:
547 + status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
548 + break;
549 + default:
550 + netdev_err(dev, "Unsupported MII interface\n");
551 + phy_disconnect(dev->phydev);
552 + dev->phydev = NULL;
553 + return -EINVAL;
554 + }
555 + writel(status.bits32, gmac->ctl_iomem + GMAC_STATUS);
556 +
557 + return 0;
558 +}
559 +
560 +static int gmac_pick_rx_max_len(int max_l3_len)
561 +{
562 + /* index = CONFIG_MAXLEN_XXX values */
563 + static const int max_len[8] = {
564 + 1536, 1518, 1522, 1542,
565 + 9212, 10236, 1518, 1518
566 + };
567 + int i, n = 5;
568 +
569 + max_l3_len += ETH_HLEN + VLAN_HLEN;
570 +
571 + if (max_l3_len > max_len[n])
572 + return -1;
573 +
574 + for (i = 0; i < 5; ++i) {
575 + if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
576 + n = i;
577 + }
578 +
579 + return n;
580 +}
581 +
582 +static int gmac_init(struct net_device *dev)
583 +{
584 + struct gmac_private *gmac = netdev_priv(dev);
585 + u32 val;
586 +
587 + GMAC_CONFIG0_T config0 = { .bits = {
588 + .dis_tx = 1,
589 + .dis_rx = 1,
590 + .ipv4_rx_chksum = 1,
591 + .ipv6_rx_chksum = 1,
592 + .rx_err_detect = 1,
593 + .rgmm_edge = 1,
594 + .port0_chk_hwq = 1,
595 + .port1_chk_hwq = 1,
596 + .port0_chk_toeq = 1,
597 + .port1_chk_toeq = 1,
598 + .port0_chk_classq = 1,
599 + .port1_chk_classq = 1,
600 + } };
601 + GMAC_AHB_WEIGHT_T ahb_weight = { .bits = {
602 + .rx_weight = 1,
603 + .tx_weight = 1,
604 + .hash_weight = 1,
605 + .pre_req = 0x1f,
606 + .tqDV_threshold = 0,
607 + } };
608 + GMAC_TX_WCR0_T hw_weigh = { .bits = {
609 + .hw_tq3 = 1,
610 + .hw_tq2 = 1,
611 + .hw_tq1 = 1,
612 + .hw_tq0 = 1,
613 + } };
614 + GMAC_TX_WCR1_T sw_weigh = { .bits = {
615 + .sw_tq5 = 1,
616 + .sw_tq4 = 1,
617 + .sw_tq3 = 1,
618 + .sw_tq2 = 1,
619 + .sw_tq1 = 1,
620 + .sw_tq0 = 1,
621 + } };
622 + GMAC_CONFIG1_T config1 = { .bits = {
623 + .set_threshold = 16,
624 + .rel_threshold = 24,
625 + } };
626 + GMAC_CONFIG2_T config2 = { .bits = {
627 + .set_threshold = 16,
628 + .rel_threshold = 32,
629 + } };
630 + GMAC_CONFIG3_T config3 = { .bits = {
631 + .set_threshold = 0,
632 + .rel_threshold = 0,
633 + } };
634 +
635 + config0.bits.max_len = gmac_pick_rx_max_len(dev->mtu);
636 +
637 + val = readl(gmac->ctl_iomem + GMAC_CONFIG0);
638 + config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved;
639 + writel(config0.bits32, gmac->ctl_iomem + GMAC_CONFIG0);
640 + writel(config1.bits32, gmac->ctl_iomem + GMAC_CONFIG1);
641 + writel(config2.bits32, gmac->ctl_iomem + GMAC_CONFIG2);
642 + writel(config3.bits32, gmac->ctl_iomem + GMAC_CONFIG3);
643 +
644 + val = readl(gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
645 + writel(ahb_weight.bits32, gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
646 +
647 + writel(hw_weigh.bits32,
648 + gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_0_REG);
649 + writel(sw_weigh.bits32,
650 + gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_1_REG);
651 +
652 + gmac->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
653 + gmac->txq_order = DEFAULT_GMAC_TXQ_ORDER;
654 + gmac->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
655 +
656 + /* Mark every quarter of the queue a packet for interrupt
657 + in order to be able to wake up the queue if it was stopped */
658 + gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
659 +
660 + return 0;
661 +}
662 +
663 +static void gmac_uninit(struct net_device *dev)
664 +{
665 + if (dev->phydev)
666 + phy_disconnect(dev->phydev);
667 +}
668 +
669 +static int gmac_setup_txqs(struct net_device *dev)
670 +{
671 + struct gmac_private *gmac = netdev_priv(dev);
672 + struct toe_private *toe = gmac->toe;
673 + void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
674 + void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
675 +
676 + unsigned int n_txq = dev->num_tx_queues;
677 + size_t entries = 1 <<gmac->txq_order;
678 + size_t len = n_txq * entries;
679 + struct gmac_txq *txq = gmac->txq;
680 + GMAC_TXDESC_T *desc_ring;
681 + struct sk_buff **skb_tab;
682 + unsigned int r;
683 + int i;
684 +
685 + skb_tab = kzalloc(len * sizeof(*skb_tab), GFP_KERNEL);
686 + if (!skb_tab)
687 + return -ENOMEM;
688 +
689 + desc_ring = dma_alloc_coherent(toe->dev, len * sizeof(*desc_ring),
690 + &gmac->txq_dma_base, GFP_KERNEL);
691 +
692 + if (!desc_ring) {
693 + kfree(skb_tab);
694 + return -ENOMEM;
695 + }
696 +
697 + BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK);
698 +
699 + writel(gmac->txq_dma_base | gmac->txq_order, base_reg);
700 +
701 + for (i = 0; i < n_txq; i++) {
702 + txq->ring = desc_ring;
703 + txq->skb = skb_tab;
704 + txq->noirq_packets = 0;
705 +
706 + r = readw(rwptr_reg);
707 + rwptr_reg += 2;
708 + writew(r, rwptr_reg);
709 + rwptr_reg +=2;
710 + txq->cptr = r;
711 +
712 + txq++;
713 + desc_ring += entries;
714 + skb_tab += entries;
715 + }
716 +
717 + return 0;
718 +}
719 +
720 +static void gmac_clean_txq(struct net_device *dev, struct gmac_txq *txq,
721 + unsigned int r)
722 +{
723 + struct gmac_private *gmac = netdev_priv(dev);
724 + struct toe_private *toe = gmac->toe;
725 + unsigned int errs = 0;
726 + unsigned int pkts = 0;
727 + unsigned int hwchksum = 0;
728 + unsigned long bytes = 0;
729 + unsigned int m = (1 << gmac->txq_order) - 1;
730 + unsigned int c = txq->cptr;
731 + GMAC_TXDESC_0_T word0;
732 + GMAC_TXDESC_1_T word1;
733 + unsigned int word3;
734 + dma_addr_t mapping;
735 + GMAC_TXDESC_T *txd;
736 + unsigned short nfrags;
737 +
738 + if (unlikely(c == r))
739 + return;
740 +
741 + rmb();
742 + while (c != r) {
743 + txd = txq->ring + c;
744 + word0 = txd->word0;
745 + word1 = txd->word1;
746 + mapping = txd->word2.buf_adr;
747 + word3 = txd->word3.bits32;
748 +
749 + dma_unmap_single(toe->dev, mapping, word0.bits.buffer_size, DMA_TO_DEVICE);
750 +
751 + if (word3 & EOF_BIT)
752 + dev_kfree_skb(txq->skb[c]);
753 +
754 + c++;
755 + c &= m;
756 +
757 + if (!(word3 & SOF_BIT))
758 + continue;
759 +
760 + if (!word0.bits.status_tx_ok) {
761 + errs++;
762 + continue;
763 + }
764 +
765 + pkts++;
766 + bytes += txd->word1.bits.byte_count;
767 +
768 + if (word1.bits32 & TSS_CHECKUM_ENABLE)
769 + hwchksum++;
770 +
771 + nfrags = word0.bits.desc_count - 1;
772 + if (nfrags) {
773 + if (nfrags >= TX_MAX_FRAGS)
774 + nfrags = TX_MAX_FRAGS - 1;
775 +
776 + u64_stats_update_begin(&gmac->tx_stats_syncp);
777 + gmac->tx_frag_stats[nfrags]++;
778 + u64_stats_update_end(&gmac->ir_stats_syncp);
779 + }
780 + }
781 +
782 + u64_stats_update_begin(&gmac->ir_stats_syncp);
783 + gmac->stats.tx_errors += errs;
784 + gmac->stats.tx_packets += pkts;
785 + gmac->stats.tx_bytes += bytes;
786 + gmac->tx_hw_csummed += hwchksum;
787 + u64_stats_update_end(&gmac->ir_stats_syncp);
788 +
789 + txq->cptr = c;
790 +}
791 +
792 +static void gmac_cleanup_txqs(struct net_device *dev)
793 +{
794 + struct gmac_private *gmac = netdev_priv(dev);
795 + struct toe_private *toe = gmac->toe;
796 + void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
797 + void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
798 +
799 + unsigned n_txq = dev->num_tx_queues;
800 + unsigned int r, i;
801 +
802 + for (i = 0; i < n_txq; i++) {
803 + r = readw(rwptr_reg);
804 + rwptr_reg += 2;
805 + writew(r, rwptr_reg);
806 + rwptr_reg += 2;
807 +
808 + gmac_clean_txq(dev, gmac->txq + i, r);
809 + }
810 + writel(0, base_reg);
811 +
812 + kfree(gmac->txq->skb);
813 + dma_free_coherent(toe->dev,
814 + n_txq * sizeof(*gmac->txq->ring) << gmac->txq_order,
815 + gmac->txq->ring, gmac->txq_dma_base);
816 +}
817 +
818 +static int gmac_setup_rxq(struct net_device *dev)
819 +{
820 + struct gmac_private *gmac = netdev_priv(dev);
821 + struct toe_private *toe = gmac->toe;
822 + NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
823 +
824 + gmac->rxq_rwptr = &qhdr->word1;
825 + gmac->rxq_ring = dma_alloc_coherent(toe->dev,
826 + sizeof(*gmac->rxq_ring) << gmac->rxq_order,
827 + &gmac->rxq_dma_base, GFP_KERNEL);
828 + if (!gmac->rxq_ring)
829 + return -ENOMEM;
830 +
831 + BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK);
832 +
833 + writel(gmac->rxq_dma_base | gmac->rxq_order, &qhdr->word0);
834 + writel(0, gmac->rxq_rwptr);
835 + return 0;
836 +}
837 +
838 +static void gmac_cleanup_rxq(struct net_device *dev)
839 +{
840 + struct gmac_private *gmac = netdev_priv(dev);
841 + struct toe_private *toe = gmac->toe;
842 +
843 + NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
844 + void __iomem *dma_reg = &qhdr->word0;
845 + void __iomem *ptr_reg = &qhdr->word1;
846 + GMAC_RXDESC_T *rxd = gmac->rxq_ring;
847 + DMA_RWPTR_T rw;
848 + unsigned int r, w;
849 + unsigned int m = (1 <<gmac->rxq_order) - 1;
850 + struct page *page;
851 + dma_addr_t mapping;
852 +
853 + rw.bits32 = readl(ptr_reg);
854 + r = rw.bits.rptr;
855 + w = rw.bits.wptr;
856 + writew(r, ptr_reg + 2);
857 +
858 + writel(0, dma_reg);
859 +
860 + rmb();
861 + while (r != w) {
862 + mapping = rxd[r].word2.buf_adr;
863 + r++;
864 + r &= m;
865 +
866 + if (!mapping)
867 + continue;
868 +
869 + page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
870 + put_page(page);
871 + }
872 +
873 + dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_order,
874 + gmac->rxq_ring, gmac->rxq_dma_base);
875 +}
876 +
877 +static struct page *toe_freeq_alloc_map_page(struct toe_private *toe, int pn)
878 +{
879 + unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
880 + unsigned int frag_len = 1 << toe->freeq_frag_order;
881 + GMAC_RXDESC_T *freeq_entry;
882 + dma_addr_t mapping;
883 + struct page *page;
884 + int i;
885 +
886 + page = alloc_page(__GFP_COLD | GFP_ATOMIC);
887 + if (!page)
888 + return NULL;
889 +
890 + mapping = dma_map_single(toe->dev, page_address(page),
891 + PAGE_SIZE, DMA_FROM_DEVICE);
892 +
893 + if (unlikely(dma_mapping_error(toe->dev, mapping) || !mapping)) {
894 + put_page(page);
895 + return NULL;
896 + }
897 +
898 + freeq_entry = toe->freeq_ring + (pn << fpp_order);
899 + for (i = 1 << fpp_order; i > 0; --i) {
900 + freeq_entry->word2.buf_adr = mapping;
901 + freeq_entry++;
902 + mapping += frag_len;
903 + }
904 +
905 + if (toe->freeq_page_tab[pn]) {
906 + mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
907 + dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
908 + put_page(toe->freeq_page_tab[pn]);
909 + }
910 +
911 + toe->freeq_page_tab[pn] = page;
912 + return page;
913 +}
914 +
915 +static unsigned int toe_fill_freeq(struct toe_private *toe, int reset)
916 +{
917 + void __iomem *rwptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
918 +
919 + DMA_RWPTR_T rw;
920 + unsigned int pn, epn;
921 + unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
922 + unsigned int m_pn = (1 << (toe->freeq_order - fpp_order)) - 1;
923 + struct page *page;
924 + unsigned int count = 0;
925 + unsigned long flags;
926 +
927 + spin_lock_irqsave(&toe->freeq_lock, flags);
928 +
929 + rw.bits32 = readl(rwptr_reg);
930 + pn = (reset ? rw.bits.rptr : rw.bits.wptr) >> fpp_order;
931 + epn = (rw.bits.rptr >> fpp_order) - 1;
932 + epn &= m_pn;
933 +
934 + while (pn != epn) {
935 + page = toe->freeq_page_tab[pn];
936 +
937 + if (atomic_read(&page->_count) > 1) {
938 + unsigned int fl = (pn -epn) & m_pn;
939 +
940 + if (fl > 64 >> fpp_order)
941 + break;
942 +
943 + page = toe_freeq_alloc_map_page(toe, pn);
944 + if (!page)
945 + break;
946 + }
947 +
948 + atomic_add(1 << fpp_order, &page->_count);
949 + count += 1 << fpp_order;
950 + pn++;
951 + pn &= m_pn;
952 + }
953 +
954 + wmb();
955 + writew(pn << fpp_order, rwptr_reg+2);
956 +
957 + spin_unlock_irqrestore(&toe->freeq_lock, flags);
958 + return count;
959 +}
960 +
961 +static int toe_setup_freeq(struct toe_private *toe)
962 +{
963 + void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
964 + QUEUE_THRESHOLD_T qt;
965 + DMA_SKB_SIZE_T skbsz;
966 + unsigned int filled;
967 + unsigned int frag_len = 1 << toe->freeq_frag_order;
968 + unsigned int len = 1 << toe->freeq_order;
969 + unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
970 + unsigned int pages = len >> fpp_order;
971 + dma_addr_t mapping;
972 + unsigned int pn;
973 +
974 + toe->freeq_ring = dma_alloc_coherent(toe->dev,
975 + sizeof(*toe->freeq_ring) << toe->freeq_order,
976 + &toe->freeq_dma_base, GFP_KERNEL);
977 + if (!toe->freeq_ring)
978 + return -ENOMEM;
979 +
980 + BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK);
981 +
982 + toe->freeq_page_tab = kzalloc(pages * sizeof(*toe->freeq_page_tab),
983 + GFP_KERNEL);
984 + if (!toe->freeq_page_tab)
985 + goto err_freeq;
986 +
987 + for (pn = 0; pn < pages; pn++)
988 + if (!toe_freeq_alloc_map_page(toe, pn))
989 + goto err_freeq_alloc;
990 +
991 + filled = toe_fill_freeq(toe, 1);
992 + if (!filled)
993 + goto err_freeq_alloc;
994 +
995 + qt.bits32 = readl(toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
996 + qt.bits.swfq_empty = 32;
997 + writel(qt.bits32, toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
998 +
999 + skbsz.bits.sw_skb_size = 1 << toe->freeq_frag_order;
1000 + writel(skbsz.bits32, toe->iomem + GLOBAL_DMA_SKB_SIZE_REG);
1001 + writel(toe->freeq_dma_base | toe->freeq_order, dma_reg);
1002 +
1003 + return 0;
1004 +
1005 +err_freeq_alloc:
1006 + while (pn > 0) {
1007 + --pn;
1008 + mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
1009 + dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
1010 + put_page(toe->freeq_page_tab[pn]);
1011 + }
1012 +
1013 +err_freeq:
1014 + dma_free_coherent(toe->dev,
1015 + sizeof(*toe->freeq_ring) << toe->freeq_order,
1016 + toe->freeq_ring, toe->freeq_dma_base);
1017 + toe->freeq_ring = NULL;
1018 + return -ENOMEM;
1019 +}
1020 +
1021 +static void toe_cleanup_freeq(struct toe_private *toe)
1022 +{
1023 + void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
1024 + void __iomem *ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
1025 +
1026 + unsigned int frag_len = 1 << toe->freeq_frag_order;
1027 + unsigned int len = 1 << toe->freeq_order;
1028 + unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
1029 + unsigned int pages = len >> fpp_order;
1030 + struct page *page;
1031 + dma_addr_t mapping;
1032 + unsigned int pn;
1033 +
1034 + writew(readw(ptr_reg), ptr_reg + 2);
1035 + writel(0, dma_reg);
1036 +
1037 + for (pn = 0; pn < pages; pn++) {
1038 + mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
1039 + dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
1040 +
1041 + page = toe->freeq_page_tab[pn];
1042 + while (atomic_read(&page->_count) > 0)
1043 + put_page(page);
1044 + }
1045 +
1046 + kfree(toe->freeq_page_tab);
1047 +
1048 + dma_free_coherent(toe->dev,
1049 + sizeof(*toe->freeq_ring) << toe->freeq_order,
1050 + toe->freeq_ring, toe->freeq_dma_base);
1051 +}
1052 +
1053 +static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id)
1054 +{
1055 + void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
1056 + struct gmac_private *gmac;
1057 + struct net_device *other = toe->netdev[1 - changing_dev_id];
1058 + unsigned new_size = 0;
1059 + unsigned new_order;
1060 + int err;
1061 + unsigned long flags;
1062 + unsigned en;
1063 +
1064 + if (other && netif_running(other))
1065 + return -EBUSY;
1066 +
1067 + if (toe->netdev[0]) {
1068 + gmac = netdev_priv(toe->netdev[0]);
1069 + new_size = 1 << (gmac->rxq_order + 1);
1070 + }
1071 +
1072 + if (toe->netdev[1]) {
1073 + gmac = netdev_priv(toe->netdev[1]);
1074 + new_size += 1 << (gmac->rxq_order + 1);
1075 + }
1076 +
1077 + new_order = min(15, ilog2(new_size - 1) + 1);
1078 + if (toe->freeq_order == new_order)
1079 + return 0;
1080 +
1081 + spin_lock_irqsave(&toe->irq_lock, flags);
1082 + en = readl(irqen_reg);
1083 + en &= ~SWFQ_EMPTY_INT_BIT;
1084 + writel(en, irqen_reg);
1085 +
1086 + if (toe->freeq_ring)
1087 + toe_cleanup_freeq(toe);
1088 +
1089 + toe->freeq_order = new_order;
1090 + err = toe_setup_freeq(toe);
1091 +
1092 + en |= SWFQ_EMPTY_INT_BIT;
1093 + writel(en, irqen_reg);
1094 + spin_unlock_irqrestore(&toe->irq_lock, flags);
1095 +
1096 + return err;
1097 +}
1098 +
1099 +static void gmac_tx_irq_enable(struct net_device *dev, unsigned txq, int en)
1100 +{
1101 + struct gmac_private *gmac = netdev_priv(dev);
1102 + struct toe_private *toe = gmac->toe;
1103 + unsigned val, mask;
1104 +
1105 + mask = GMAC0_IRQ0_TXQ0_INTS << (6 * dev->dev_id + txq);
1106 +
1107 + if (en)
1108 + writel(mask, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
1109 +
1110 + val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1111 + val = en ? val | mask : val & ~mask;
1112 + writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1113 +}
1114 +
1115 +
1116 +static void gmac_tx_irq(struct net_device *dev, unsigned txq_num)
1117 +{
1118 + struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num);
1119 +
1120 + gmac_tx_irq_enable(dev, txq_num, 0);
1121 + netif_tx_wake_queue(ntxq);
1122 +}
1123 +
1124 +static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb,
1125 + struct gmac_txq *txq, unsigned short *desc)
1126 +{
1127 + struct gmac_private *gmac = netdev_priv(dev);
1128 + struct toe_private *toe = gmac->toe;
1129 + struct skb_shared_info *skb_si = skb_shinfo(skb);
1130 + skb_frag_t *skb_frag;
1131 + short frag, last_frag = skb_si->nr_frags - 1;
1132 + unsigned short m = (1 << gmac->txq_order) -1;
1133 + unsigned short w = *desc;
1134 + unsigned word1, word3, buflen;
1135 + dma_addr_t mapping;
1136 + void *buffer;
1137 + unsigned short mtu;
1138 + GMAC_TXDESC_T *txd;
1139 +
1140 + mtu = ETH_HLEN;
1141 + mtu += dev->mtu;
1142 + if (skb->protocol == htons(ETH_P_8021Q))
1143 + mtu += VLAN_HLEN;
1144 +
1145 + word1 = skb->len;
1146 + word3 = SOF_BIT;
1147 +
1148 + if (word1 > mtu) {
1149 + word1 |= TSS_MTU_ENABLE_BIT;
1150 + word3 += mtu;
1151 + }
1152 +
1153 + if (skb->ip_summed != CHECKSUM_NONE) {
1154 + int tcp = 0;
1155 + if (skb->protocol == htons(ETH_P_IP)) {
1156 + word1 |= TSS_IP_CHKSUM_BIT;
1157 + tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1158 + } else { /* IPv6 */
1159 + word1 |= TSS_IPV6_ENABLE_BIT;
1160 + tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1161 + }
1162 +
1163 + word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1164 + }
1165 +
1166 + frag = -1;
1167 + while (frag <= last_frag) {
1168 + if (frag == -1) {
1169 + buffer = skb->data;
1170 + buflen = skb_headlen(skb);
1171 + } else {
1172 + skb_frag = skb_si->frags + frag;
1173 + buffer = page_address(skb_frag_page(skb_frag)) +
1174 + skb_frag->page_offset;
1175 + buflen = skb_frag->size;
1176 + }
1177 +
1178 + if (frag == last_frag) {
1179 + word3 |= EOF_BIT;
1180 + txq->skb[w] = skb;
1181 + }
1182 +
1183 + mapping = dma_map_single(toe->dev, buffer, buflen,
1184 + DMA_TO_DEVICE);
1185 + if (dma_mapping_error(toe->dev, mapping) ||
1186 + !(mapping & PAGE_MASK))
1187 + goto map_error;
1188 +
1189 + txd = txq->ring + w;
1190 + txd->word0.bits32 = buflen;
1191 + txd->word1.bits32 = word1;
1192 + txd->word2.buf_adr = mapping;
1193 + txd->word3.bits32 = word3;
1194 +
1195 + word3 &= MTU_SIZE_BIT_MASK;
1196 + w++;
1197 + w &= m;
1198 + frag++;
1199 + }
1200 +
1201 + *desc = w;
1202 + return 0;
1203 +
1204 +map_error:
1205 + while (w != *desc) {
1206 + w--;
1207 + w &= m;
1208 +
1209 + dma_unmap_page(toe->dev, txq->ring[w].word2.buf_adr,
1210 + txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE);
1211 + }
1212 + return ENOMEM;
1213 +}
1214 +
1215 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1216 +{
1217 + struct gmac_private *gmac = netdev_priv(dev);
1218 +
1219 + void __iomem *ptr_reg;
1220 + struct gmac_txq *txq;
1221 + struct netdev_queue *ntxq;
1222 + int txq_num, nfrags;
1223 + DMA_RWPTR_T rw;
1224 + unsigned short r, w, d;
1225 + unsigned short m = (1 << gmac->txq_order) - 1;
1226 +
1227 + SKB_FRAG_ASSERT(skb);
1228 +
1229 + if (unlikely(skb->len >= 0x10000))
1230 + goto out_drop_free;
1231 +
1232 + txq_num = skb_get_queue_mapping(skb);
1233 + ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1234 + txq = &gmac->txq[txq_num];
1235 + ntxq = netdev_get_tx_queue(dev, txq_num);
1236 + nfrags = skb_shinfo(skb)->nr_frags;
1237 +
1238 + rw.bits32 = readl(ptr_reg);
1239 + r = rw.bits.rptr;
1240 + w = rw.bits.wptr;
1241 +
1242 + d = txq->cptr - w - 1;
1243 + d &= m;
1244 +
1245 + if (unlikely(d < nfrags+2))
1246 + {
1247 + gmac_clean_txq(dev, txq, r);
1248 + d = txq->cptr - w - 1;
1249 + d &= m;
1250 +
1251 + if (unlikely(d < nfrags+2)) {
1252 + netif_tx_stop_queue(ntxq);
1253 +
1254 + d = txq->cptr + nfrags + 16;
1255 + d &= m;
1256 + txq->ring[d].word3.bits.eofie = 1;
1257 + gmac_tx_irq_enable(dev, txq_num, 1);
1258 +
1259 + u64_stats_update_begin(&gmac->tx_stats_syncp);
1260 + dev->stats.tx_fifo_errors++;
1261 + u64_stats_update_end(&gmac->tx_stats_syncp);
1262 + return NETDEV_TX_BUSY;
1263 + }
1264 + }
1265 +
1266 + if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) {
1267 + if (skb_linearize(skb))
1268 + goto out_drop;
1269 +
1270 + if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w)))
1271 + goto out_drop_free;
1272 +
1273 + u64_stats_update_begin(&gmac->tx_stats_syncp);
1274 + gmac->tx_frags_linearized++;
1275 + u64_stats_update_end(&gmac->tx_stats_syncp);
1276 + }
1277 +
1278 + writew(w, ptr_reg+2);
1279 +
1280 + gmac_clean_txq(dev, txq, r);
1281 + return NETDEV_TX_OK;
1282 +
1283 +out_drop_free:
1284 + dev_kfree_skb(skb);
1285 +out_drop:
1286 + u64_stats_update_begin(&gmac->tx_stats_syncp);
1287 + gmac->stats.tx_dropped++;
1288 + u64_stats_update_end(&gmac->tx_stats_syncp);
1289 + return NETDEV_TX_OK;
1290 +}
1291 +
1292 +static void gmac_tx_timeout(struct net_device *dev)
1293 +{
1294 + netdev_err(dev, "Tx timeout\n");
1295 + gmac_dump_dma_state(dev);
1296 +}
1297 +
1298 +static void gmac_enable_irq(struct net_device *dev, int enable)
1299 +{
1300 + struct gmac_private *gmac = netdev_priv(dev);
1301 + struct toe_private *toe = gmac->toe;
1302 + unsigned long flags;
1303 + unsigned val, mask;
1304 +
1305 + spin_lock_irqsave(&toe->irq_lock, flags);
1306 +
1307 + mask = GMAC0_IRQ0_2 << (dev->dev_id * 2);
1308 + val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1309 + val = enable ? (val | mask) : (val & ~mask);
1310 + writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1311 +
1312 + mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
1313 + val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1314 + val = enable ? (val | mask) : (val & ~mask);
1315 + writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1316 +
1317 + mask = GMAC0_IRQ4_8 << (dev->dev_id * 8);
1318 + val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1319 + val = enable ? (val | mask) : (val & ~mask);
1320 + writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1321 +
1322 + spin_unlock_irqrestore(&toe->irq_lock, flags);
1323 +}
1324 +
1325 +static void gmac_enable_rx_irq(struct net_device *dev, int enable)
1326 +{
1327 + struct gmac_private *gmac = netdev_priv(dev);
1328 + struct toe_private *toe = gmac->toe;
1329 + unsigned long flags;
1330 + unsigned val, mask;
1331 +
1332 + spin_lock_irqsave(&toe->irq_lock, flags);
1333 + mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
1334 +
1335 + val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1336 + val = enable ? (val | mask) : (val & ~mask);
1337 + writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1338 +
1339 + spin_unlock_irqrestore(&toe->irq_lock, flags);
1340 +}
1341 +
1342 +static struct sk_buff *gmac_skb_if_good_frame(struct gmac_private *gmac,
1343 + GMAC_RXDESC_0_T word0, unsigned frame_len)
1344 +{
1345 + struct sk_buff *skb = NULL;
1346 + unsigned rx_status = word0.bits.status;
1347 + unsigned rx_csum = word0.bits.chksum_status;
1348 +
1349 + gmac->rx_stats[rx_status]++;
1350 + gmac->rx_csum_stats[rx_csum]++;
1351 +
1352 + if (word0.bits.derr || word0.bits.perr ||
1353 + rx_status || frame_len < ETH_ZLEN ||
1354 + rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1355 + gmac->stats.rx_errors++;
1356 +
1357 + if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1358 + gmac->stats.rx_length_errors++;
1359 + if (RX_ERROR_OVER(rx_status))
1360 + gmac->stats.rx_over_errors++;
1361 + if (RX_ERROR_CRC(rx_status))
1362 + gmac->stats.rx_crc_errors++;
1363 + if (RX_ERROR_FRAME(rx_status))
1364 + gmac->stats.rx_frame_errors++;
1365 +
1366 + return NULL;
1367 + }
1368 +
1369 + skb = napi_get_frags(&gmac->napi);
1370 + if (!skb)
1371 + return NULL;
1372 +
1373 + if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1374 + skb->ip_summed = CHECKSUM_UNNECESSARY;
1375 +
1376 + gmac->stats.rx_bytes += frame_len;
1377 + gmac->stats.rx_packets++;
1378 + return skb;
1379 +}
1380 +
1381 +static unsigned gmac_rx(struct net_device *dev, unsigned budget)
1382 +{
1383 + struct gmac_private *gmac = netdev_priv(dev);
1384 + struct toe_private *toe = gmac->toe;
1385 + void __iomem *ptr_reg = gmac->rxq_rwptr;
1386 +
1387 + static struct sk_buff *skb;
1388 +
1389 + DMA_RWPTR_T rw;
1390 + unsigned short r, w;
1391 + unsigned short m = (1 << gmac->rxq_order) -1;
1392 + GMAC_RXDESC_T *rx = NULL;
1393 + struct page* page = NULL;
1394 + unsigned page_offs;
1395 + unsigned int frame_len, frag_len;
1396 + int frag_nr = 0;
1397 +
1398 + GMAC_RXDESC_0_T word0;
1399 + GMAC_RXDESC_1_T word1;
1400 + dma_addr_t mapping;
1401 + GMAC_RXDESC_3_T word3;
1402 +
1403 + rw.bits32 = readl(ptr_reg);
1404 + /* Reset interrupt as all packages until here are taken into account */
1405 + writel(DEFAULT_Q0_INT_BIT << dev->dev_id,
1406 + toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
1407 + r = rw.bits.rptr;
1408 + w = rw.bits.wptr;
1409 +
1410 + while (budget && w != r) {
1411 + rx = gmac->rxq_ring + r;
1412 + word0 = rx->word0;
1413 + word1 = rx->word1;
1414 + mapping = rx->word2.buf_adr;
1415 + word3 = rx->word3;
1416 +
1417 + r++;
1418 + r &= m;
1419 +
1420 + frag_len = word0.bits.buffer_size;
1421 + frame_len =word1.bits.byte_count;
1422 + page_offs = mapping & ~PAGE_MASK;
1423 +
1424 + if (unlikely(!mapping)) {
1425 + netdev_err(dev, "rxq[%u]: HW BUG: zero DMA desc\n", r);
1426 + goto err_drop;
1427 + }
1428 +
1429 + page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
1430 +
1431 + if (word3.bits32 & SOF_BIT) {
1432 + if (unlikely(skb)) {
1433 + napi_free_frags(&gmac->napi);
1434 + gmac->stats.rx_dropped++;
1435 + }
1436 +
1437 + skb = gmac_skb_if_good_frame(gmac, word0, frame_len);
1438 + if (unlikely(!skb))
1439 + goto err_drop;
1440 +
1441 + page_offs += NET_IP_ALIGN;
1442 + frag_len -= NET_IP_ALIGN;
1443 + frag_nr = 0;
1444 +
1445 + } else if (!skb) {
1446 + put_page(page);
1447 + continue;
1448 + }
1449 +
1450 + if (word3.bits32 & EOF_BIT)
1451 + frag_len = frame_len - skb->len;
1452 +
1453 + /* append page frag to skb */
1454 + if (unlikely(frag_nr == MAX_SKB_FRAGS))
1455 + goto err_drop;
1456 +
1457 + if (frag_len == 0)
1458 + netdev_err(dev, "Received fragment with len = 0\n");
1459 +
1460 + skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1461 + skb->len += frag_len;
1462 + skb->data_len += frag_len;
1463 + skb->truesize += frag_len;
1464 + frag_nr++;
1465 +
1466 + if (word3.bits32 & EOF_BIT) {
1467 + napi_gro_frags(&gmac->napi);
1468 + skb = NULL;
1469 + --budget;
1470 + }
1471 + continue;
1472 +
1473 +err_drop:
1474 + if (skb) {
1475 + napi_free_frags(&gmac->napi);
1476 + skb = NULL;
1477 + }
1478 +
1479 + if (mapping)
1480 + put_page(page);
1481 +
1482 + gmac->stats.rx_dropped++;
1483 + }
1484 +
1485 + writew(r, ptr_reg);
1486 + return budget;
1487 +}
1488 +
1489 +static int gmac_napi_poll(struct napi_struct *napi, int budget)
1490 +{
1491 + struct gmac_private *gmac = netdev_priv(napi->dev);
1492 + struct toe_private *toe = gmac->toe;
1493 + unsigned rx;
1494 + unsigned freeq_threshold = 1 << (toe->freeq_order - 1);
1495 +
1496 + u64_stats_update_begin(&gmac->rx_stats_syncp);
1497 +
1498 + rx = budget - gmac_rx(napi->dev, budget);
1499 +
1500 + if (rx == 0) {
1501 + napi_gro_flush(napi, false);
1502 + __napi_complete(napi);
1503 + gmac_enable_rx_irq(napi->dev, 1);
1504 + ++gmac->rx_napi_exits;
1505 + }
1506 +
1507 + gmac->freeq_refill += rx;
1508 + if (gmac->freeq_refill > freeq_threshold) {
1509 + gmac->freeq_refill -= freeq_threshold;
1510 + toe_fill_freeq(toe, 0);
1511 + }
1512 +
1513 + u64_stats_update_end(&gmac->rx_stats_syncp);
1514 + return rx;
1515 +}
1516 +
1517 +static void gmac_dump_dma_state(struct net_device *dev)
1518 +{
1519 + struct gmac_private *gmac = netdev_priv(dev);
1520 + struct toe_private *toe = gmac->toe;
1521 + void __iomem *ptr_reg;
1522 + unsigned reg[5];
1523 +
1524 + /* Interrupt status */
1525 + reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
1526 + reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
1527 + reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
1528 + reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
1529 + reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1530 + netdev_err(dev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1531 + reg[0], reg[1], reg[2], reg[3], reg[4]);
1532 +
1533 + /* Interrupt enable */
1534 + reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1535 + reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1536 + reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
1537 + reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
1538 + reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1539 + netdev_err(dev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1540 + reg[0], reg[1], reg[2], reg[3], reg[4]);
1541 +
1542 + /* RX DMA status */
1543 + reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_FIRST_DESC_REG);
1544 + reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_CURR_DESC_REG);
1545 + reg[2] = GET_RPTR(gmac->rxq_rwptr);
1546 + reg[3] = GET_WPTR(gmac->rxq_rwptr);
1547 + netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1548 + reg[0], reg[1], reg[2], reg[3]);
1549 +
1550 + reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD0_REG);
1551 + reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD1_REG);
1552 + reg[2] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD2_REG);
1553 + reg[3] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD3_REG);
1554 + netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1555 + reg[0], reg[1], reg[2], reg[3]);
1556 +
1557 + /* TX DMA status */
1558 + ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
1559 +
1560 + reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_FIRST_DESC_REG);
1561 + reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_CURR_DESC_REG);
1562 + reg[2] = GET_RPTR(ptr_reg);
1563 + reg[3] = GET_WPTR(ptr_reg);
1564 + netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1565 + reg[0], reg[1], reg[2], reg[3]);
1566 +
1567 + reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD0_REG);
1568 + reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD1_REG);
1569 + reg[2] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD2_REG);
1570 + reg[3] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD3_REG);
1571 + netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1572 + reg[0], reg[1], reg[2], reg[3]);
1573 +
1574 + /* FREE queues status */
1575 + ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
1576 +
1577 + reg[0] = GET_RPTR(ptr_reg);
1578 + reg[1] = GET_WPTR(ptr_reg);
1579 +
1580 + ptr_reg = toe->iomem + GLOBAL_HWFQ_RWPTR_REG;
1581 +
1582 + reg[2] = GET_RPTR(ptr_reg);
1583 + reg[3] = GET_WPTR(ptr_reg);
1584 + netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1585 + reg[0], reg[1], reg[2], reg[3]);
1586 +}
1587 +
1588 +static void gmac_update_hw_stats(struct net_device *dev)
1589 +{
1590 + struct gmac_private *gmac = netdev_priv(dev);
1591 + struct toe_private *toe = gmac->toe;
1592 + unsigned long flags;
1593 + unsigned int rx_discards, rx_mcast, rx_bcast;
1594 +
1595 + spin_lock_irqsave(&toe->irq_lock, flags);
1596 + u64_stats_update_begin(&gmac->ir_stats_syncp);
1597 +
1598 + gmac->hw_stats[0] += rx_discards = readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
1599 + gmac->hw_stats[1] += readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
1600 + gmac->hw_stats[2] += rx_mcast = readl(gmac->ctl_iomem + GMAC_IN_MCAST);
1601 + gmac->hw_stats[3] += rx_bcast = readl(gmac->ctl_iomem + GMAC_IN_BCAST);
1602 + gmac->hw_stats[4] += readl(gmac->ctl_iomem + GMAC_IN_MAC1);
1603 + gmac->hw_stats[5] += readl(gmac->ctl_iomem + GMAC_IN_MAC2);
1604 +
1605 + gmac->stats.rx_missed_errors += rx_discards;
1606 + gmac->stats.multicast += rx_mcast;
1607 + gmac->stats.multicast += rx_bcast;
1608 +
1609 + writel(GMAC0_MIB_INT_BIT << (dev->dev_id * 8),
1610 + toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1611 +
1612 + u64_stats_update_end(&gmac->ir_stats_syncp);
1613 + spin_unlock_irqrestore(&toe->irq_lock, flags);
1614 +}
1615 +
1616 +static inline unsigned gmac_get_intr_flags(struct net_device *dev, int i)
1617 +{
1618 + struct gmac_private *gmac = netdev_priv(dev);
1619 + struct toe_private *toe = gmac->toe;
1620 + void __iomem *irqif_reg, *irqen_reg;
1621 + unsigned offs, val;
1622 +
1623 + offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - GLOBAL_INTERRUPT_STATUS_0_REG);
1624 +
1625 + irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1626 + irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1627 +
1628 + val = readl(irqif_reg) & readl(irqen_reg);
1629 + return val;
1630 +}
1631 +
1632 +enum hrtimer_restart gmac_coalesce_delay_expired( struct hrtimer *timer )
1633 +{
1634 + struct gmac_private *gmac = container_of(timer, struct gmac_private, rx_coalesce_timer);
1635 +
1636 + napi_schedule(&gmac->napi);
1637 + return HRTIMER_NORESTART;
1638 +}
1639 +
1640 +static irqreturn_t gmac_irq(int irq, void *data)
1641 +{
1642 + struct net_device *dev = data;
1643 + struct gmac_private *gmac = netdev_priv(dev);
1644 + struct toe_private *toe = gmac->toe;
1645 + unsigned val, orr = 0;
1646 +
1647 + orr |= val = gmac_get_intr_flags(dev, 0);
1648 +
1649 + if (unlikely(val & (GMAC0_IRQ0_2 << (dev->dev_id * 2)))) {
1650 + /* oh, crap. */
1651 + netdev_err(dev, "hw failure/sw bug\n");
1652 + gmac_dump_dma_state(dev);
1653 +
1654 + /* don't know how to recover, just reduce losses */
1655 + gmac_enable_irq(dev, 0);
1656 + return IRQ_HANDLED;
1657 + }
1658 +
1659 + if (val & (GMAC0_IRQ0_TXQ0_INTS << (dev->dev_id * 6)))
1660 + gmac_tx_irq(dev, 0);
1661 +
1662 + orr |= val = gmac_get_intr_flags(dev, 1);
1663 +
1664 + if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id)) {
1665 +
1666 + gmac_enable_rx_irq(dev, 0);
1667 +
1668 + if (!gmac->rx_coalesce_nsecs)
1669 + napi_schedule(&gmac->napi);
1670 + else {
1671 + ktime_t ktime;
1672 + ktime = ktime_set(0, gmac->rx_coalesce_nsecs);
1673 + hrtimer_start(&gmac->rx_coalesce_timer, ktime, HRTIMER_MODE_REL);
1674 + }
1675 + }
1676 +
1677 + orr |= val = gmac_get_intr_flags(dev, 4);
1678 +
1679 + if (unlikely(val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8))))
1680 + gmac_update_hw_stats(dev);
1681 +
1682 + if (unlikely(val & (GMAC0_RX_OVERRUN_INT_BIT << (dev->dev_id * 8)))) {
1683 + writel(GMAC0_RXDERR_INT_BIT << (dev->dev_id * 8),
1684 + toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1685 +
1686 + spin_lock(&toe->irq_lock);
1687 + u64_stats_update_begin(&gmac->ir_stats_syncp);
1688 + ++gmac->stats.rx_fifo_errors;
1689 + u64_stats_update_end(&gmac->ir_stats_syncp);
1690 + spin_unlock(&toe->irq_lock);
1691 + }
1692 +
1693 + return orr ? IRQ_HANDLED : IRQ_NONE;
1694 +}
1695 +
1696 +static void gmac_start_dma(struct gmac_private *gmac)
1697 +{
1698 + void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
1699 + GMAC_DMA_CTRL_T dma_ctrl;
1700 +
1701 + dma_ctrl.bits32 = readl(dma_ctrl_reg);
1702 + dma_ctrl.bits.rd_enable = 1;
1703 + dma_ctrl.bits.td_enable = 1;
1704 + dma_ctrl.bits.loopback = 0;
1705 + dma_ctrl.bits.drop_small_ack = 0;
1706 + dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1707 + dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1708 + dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1709 + dma_ctrl.bits.rd_bus = HSIZE_8;
1710 + dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1711 + dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1712 + dma_ctrl.bits.td_bus = HSIZE_8;
1713 +
1714 + writel(dma_ctrl.bits32, dma_ctrl_reg);
1715 +}
1716 +
1717 +static void gmac_stop_dma(struct gmac_private *gmac)
1718 +{
1719 + void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
1720 + GMAC_DMA_CTRL_T dma_ctrl;
1721 +
1722 + dma_ctrl.bits32 = readl(dma_ctrl_reg);
1723 + dma_ctrl.bits.rd_enable = 0;
1724 + dma_ctrl.bits.td_enable = 0;
1725 + writel(dma_ctrl.bits32, dma_ctrl_reg);
1726 +}
1727 +
1728 +static int gmac_open(struct net_device *dev)
1729 +{
1730 + struct gmac_private *gmac = netdev_priv(dev);
1731 + int err;
1732 +
1733 + if (!dev->phydev) {
1734 + err = gmac_setup_phy(dev);
1735 + if (err) {
1736 + netif_err(gmac, ifup, dev,
1737 + "PHY init failed: %d\n", err);
1738 + return err;
1739 + }
1740 + }
1741 +
1742 + err = request_irq(dev->irq, gmac_irq,
1743 + IRQF_SHARED, dev->name, dev);
1744 + if (unlikely(err))
1745 + return err;
1746 +
1747 + netif_carrier_off(dev);
1748 + phy_start(dev->phydev);
1749 +
1750 + err = toe_resize_freeq(gmac->toe, dev->dev_id);
1751 + if (unlikely(err))
1752 + goto err_stop_phy;
1753 +
1754 + err = gmac_setup_rxq(dev);
1755 + if (unlikely(err))
1756 + goto err_stop_phy;
1757 +
1758 + err = gmac_setup_txqs(dev);
1759 + if (unlikely(err)) {
1760 + gmac_cleanup_rxq(dev);
1761 + goto err_stop_phy;
1762 + }
1763 +
1764 + napi_enable(&gmac->napi);
1765 +
1766 + gmac_start_dma(gmac);
1767 + gmac_enable_irq(dev, 1);
1768 + gmac_enable_tx_rx(dev);
1769 + netif_tx_start_all_queues(dev);
1770 +
1771 + hrtimer_init(&gmac->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1772 + gmac->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1773 + return 0;
1774 +
1775 +err_stop_phy:
1776 + phy_stop(dev->phydev);
1777 + free_irq(dev->irq, dev);
1778 + return err;
1779 +}
1780 +
1781 +static int gmac_stop(struct net_device *dev)
1782 +{
1783 + struct gmac_private *gmac = netdev_priv(dev);
1784 +
1785 + hrtimer_cancel(&gmac->rx_coalesce_timer);
1786 + netif_tx_stop_all_queues(dev);
1787 + gmac_disable_tx_rx(dev);
1788 + gmac_stop_dma(gmac);
1789 + napi_disable(&gmac->napi);
1790 +
1791 + gmac_enable_irq(dev, 0);
1792 + gmac_cleanup_rxq(dev);
1793 + gmac_cleanup_txqs(dev);
1794 +
1795 + phy_stop(dev->phydev);
1796 + free_irq(dev->irq, dev);
1797 +
1798 + gmac_update_hw_stats(dev);
1799 + return 0;
1800 +}
1801 +
1802 +static void gmac_set_rx_mode(struct net_device *dev)
1803 +{
1804 + struct gmac_private *gmac = netdev_priv(dev);
1805 + struct netdev_hw_addr *ha;
1806 + __u32 mc_filter[2];
1807 + unsigned bit_nr;
1808 + GMAC_RX_FLTR_T filter = { .bits = {
1809 + .broadcast = 1,
1810 + .multicast = 1,
1811 + .unicast = 1,
1812 + } };
1813 +
1814 + mc_filter[1] = mc_filter[0] = 0;
1815 +
1816 + if (dev->flags & IFF_PROMISC) {
1817 + filter.bits.error = 1;
1818 + filter.bits.promiscuous = 1;
1819 + } else if (!(dev->flags & IFF_ALLMULTI)) {
1820 + mc_filter[1] = mc_filter[0] = 0;
1821 + netdev_for_each_mc_addr(ha, dev) {
1822 + bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1823 + mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1824 + }
1825 + }
1826 +
1827 + writel(mc_filter[0], gmac->ctl_iomem + GMAC_MCAST_FIL0);
1828 + writel(mc_filter[1], gmac->ctl_iomem + GMAC_MCAST_FIL1);
1829 + writel(filter.bits32, gmac->ctl_iomem + GMAC_RX_FLTR);
1830 +}
1831 +
1832 +static void __gmac_set_mac_address(struct net_device *dev)
1833 +{
1834 + struct gmac_private *gmac = netdev_priv(dev);
1835 + __le32 addr[3];
1836 +
1837 + memset(addr, 0, sizeof(addr));
1838 + memcpy(addr, dev->dev_addr, ETH_ALEN);
1839 +
1840 + writel(le32_to_cpu(addr[0]), gmac->ctl_iomem + GMAC_STA_ADD0);
1841 + writel(le32_to_cpu(addr[1]), gmac->ctl_iomem + GMAC_STA_ADD1);
1842 + writel(le32_to_cpu(addr[2]), gmac->ctl_iomem + GMAC_STA_ADD2);
1843 +}
1844 +
1845 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
1846 +{
1847 + struct sockaddr *sa = addr;
1848 +
1849 + memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1850 + __gmac_set_mac_address(dev);
1851 +
1852 + return 0;
1853 +}
1854 +
1855 +static void gmac_clear_hw_stats(struct net_device *dev)
1856 +{
1857 + struct gmac_private *gmac = netdev_priv(dev);
1858 +
1859 + readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
1860 + readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
1861 + readl(gmac->ctl_iomem + GMAC_IN_MCAST);
1862 + readl(gmac->ctl_iomem + GMAC_IN_BCAST);
1863 + readl(gmac->ctl_iomem + GMAC_IN_MAC1);
1864 + readl(gmac->ctl_iomem + GMAC_IN_MAC2);
1865 +}
1866 +
1867 +static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev,
1868 + struct rtnl_link_stats64 *storage)
1869 +{
1870 + struct gmac_private *gmac = netdev_priv(dev);
1871 + unsigned int start;
1872 +
1873 + gmac_update_hw_stats(dev);
1874 +
1875 + /* racing with RX NAPI */
1876 + do {
1877 + start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
1878 +
1879 + storage->rx_packets = gmac->stats.rx_packets;
1880 + storage->rx_bytes = gmac->stats.rx_bytes;
1881 + storage->rx_errors = gmac->stats.rx_errors;
1882 + storage->rx_dropped = gmac->stats.rx_dropped;
1883 +
1884 + storage->rx_length_errors = gmac->stats.rx_length_errors;
1885 + storage->rx_over_errors = gmac->stats.rx_over_errors;
1886 + storage->rx_crc_errors = gmac->stats.rx_crc_errors;
1887 + storage->rx_frame_errors = gmac->stats.rx_frame_errors;
1888 +
1889 + } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
1890 +
1891 + /* racing with MIB and TX completion interrupts */
1892 + do {
1893 + start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
1894 +
1895 + storage->tx_errors = gmac->stats.tx_errors;
1896 + storage->tx_packets = gmac->stats.tx_packets;
1897 + storage->tx_bytes = gmac->stats.tx_bytes;
1898 +
1899 + storage->multicast = gmac->stats.multicast;
1900 + storage->rx_missed_errors = gmac->stats.rx_missed_errors;
1901 + storage->rx_fifo_errors = gmac->stats.rx_fifo_errors;
1902 +
1903 + } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
1904 +
1905 + /* racing with hard_start_xmit */
1906 + do {
1907 + start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
1908 +
1909 + storage->tx_dropped = gmac->stats.tx_dropped;
1910 +
1911 + } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
1912 +
1913 + storage->rx_dropped += storage->rx_missed_errors;
1914 +
1915 + return storage;
1916 +}
1917 +
1918 +static int gmac_change_mtu(struct net_device *dev, int new_mtu)
1919 +{
1920 + int max_len = gmac_pick_rx_max_len(new_mtu);
1921 +
1922 + if (max_len < 0)
1923 + return -EINVAL;
1924 +
1925 + gmac_disable_tx_rx(dev);
1926 +
1927 + dev->mtu = new_mtu;
1928 + gmac_update_config0_reg(dev,
1929 + max_len << CONFIG0_MAXLEN_SHIFT,
1930 + CONFIG0_MAXLEN_MASK);
1931 +
1932 + netdev_update_features(dev);
1933 +
1934 + gmac_enable_tx_rx(dev);
1935 +
1936 + return 0;
1937 +}
1938 +
1939 +static netdev_features_t gmac_fix_features(struct net_device *dev, netdev_features_t features)
1940 +{
1941 + if (dev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1942 + features &= ~GMAC_OFFLOAD_FEATURES;
1943 +
1944 + return features;
1945 +}
1946 +
1947 +static int gmac_set_features(struct net_device *dev, netdev_features_t features)
1948 +{
1949 + struct gmac_private *gmac = netdev_priv(dev);
1950 + int enable = features & NETIF_F_RXCSUM;
1951 + unsigned long flags;
1952 + u32 reg;
1953 +
1954 + spin_lock_irqsave(&gmac->config_lock, flags);
1955 +
1956 + reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
1957 + reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
1958 + writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
1959 +
1960 + spin_unlock_irqrestore(&gmac->config_lock, flags);
1961 + return 0;
1962 +}
1963 +
1964 +static int gmac_get_sset_count(struct net_device *dev, int sset)
1965 +{
1966 + return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
1967 +}
1968 +
1969 +static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1970 +{
1971 + if (stringset != ETH_SS_STATS)
1972 + return;
1973 +
1974 + memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
1975 +}
1976 +
1977 +static void gmac_get_ethtool_stats(struct net_device *dev,
1978 + struct ethtool_stats *estats, u64 *values)
1979 +{
1980 + struct gmac_private *gmac = netdev_priv(dev);
1981 + unsigned int start;
1982 + u64 *p;
1983 + int i;
1984 +
1985 + gmac_update_hw_stats(dev);
1986 +
1987 + /* racing with MIB interrupt */
1988 + do {
1989 + p = values;
1990 + start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
1991 +
1992 + for (i = 0; i < RX_STATS_NUM; ++i)
1993 + *p++ = gmac->hw_stats[i];
1994 +
1995 + } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
1996 + values = p;
1997 +
1998 + /* racing with RX NAPI */
1999 + do {
2000 + p = values;
2001 + start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
2002 +
2003 + for (i = 0; i < RX_STATUS_NUM; ++i)
2004 + *p++ = gmac->rx_stats[i];
2005 + for (i = 0; i < RX_CHKSUM_NUM; ++i)
2006 + *p++ = gmac->rx_csum_stats[i];
2007 + *p++ = gmac->rx_napi_exits;
2008 +
2009 + } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
2010 + values = p;
2011 +
2012 + /* racing with TX start_xmit */
2013 + do {
2014 + p = values;
2015 + start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
2016 +
2017 + for (i = 0; i < TX_MAX_FRAGS; ++i) {
2018 + *values++ = gmac->tx_frag_stats[i];
2019 + gmac->tx_frag_stats[i] = 0;
2020 + }
2021 + *values++ = gmac->tx_frags_linearized;
2022 + *values++ = gmac->tx_hw_csummed;
2023 +
2024 + } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
2025 +}
2026 +
2027 +static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2028 +{
2029 + if (!dev->phydev)
2030 + return -ENXIO;
2031 + return phy_ethtool_gset(dev->phydev, cmd);
2032 +}
2033 +
2034 +static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2035 +{
2036 + if (!dev->phydev)
2037 + return -ENXIO;
2038 + return phy_ethtool_sset(dev->phydev, cmd);
2039 +}
2040 +
2041 +static int gmac_nway_reset(struct net_device *dev)
2042 +{
2043 + if (!dev->phydev)
2044 + return -ENXIO;
2045 + return phy_start_aneg(dev->phydev);
2046 +}
2047 +
2048 +static void gmac_get_pauseparam(struct net_device *dev,
2049 + struct ethtool_pauseparam *pparam)
2050 +{
2051 + struct gmac_private *gmac = netdev_priv(dev);
2052 + GMAC_CONFIG0_T config0;
2053 +
2054 + config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
2055 +
2056 + pparam->rx_pause = config0.bits.rx_fc_en;
2057 + pparam->tx_pause = config0.bits.tx_fc_en;
2058 + pparam->autoneg = true;
2059 +}
2060 +
2061 +static void gmac_get_ringparam(struct net_device *dev,
2062 + struct ethtool_ringparam *rp)
2063 +{
2064 + struct gmac_private *gmac = netdev_priv(dev);
2065 + GMAC_CONFIG0_T config0;
2066 +
2067 + config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
2068 +
2069 + rp->rx_max_pending = 1 << 15;
2070 + rp->rx_mini_max_pending = 0;
2071 + rp->rx_jumbo_max_pending = 0;
2072 + rp->tx_max_pending = 1 << 15;
2073 +
2074 + rp->rx_pending = 1 << gmac->rxq_order;
2075 + rp->rx_mini_pending = 0;
2076 + rp->rx_jumbo_pending = 0;
2077 + rp->tx_pending = 1 << gmac->txq_order;
2078 +}
2079 +
2080 +static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id);
2081 +
2082 +static int gmac_set_ringparam(struct net_device *dev,
2083 + struct ethtool_ringparam *rp)
2084 +{
2085 + struct gmac_private *gmac = netdev_priv(dev);
2086 + struct toe_private *toe = gmac->toe;
2087 + int err = 0;
2088 +
2089 + if (netif_running(dev))
2090 + return -EBUSY;
2091 +
2092 + if (rp->rx_pending) {
2093 + gmac->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2094 + err = toe_resize_freeq(toe, dev->dev_id);
2095 + }
2096 +
2097 + if (rp->tx_pending)
2098 + {
2099 + gmac->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2100 + gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
2101 + }
2102 +
2103 + return err;
2104 +}
2105 +
2106 +static int gmac_get_coalesce(struct net_device *dev,
2107 + struct ethtool_coalesce *ecmd)
2108 +{
2109 + struct gmac_private *gmac = netdev_priv(dev);
2110 +
2111 + ecmd->rx_max_coalesced_frames = 1;
2112 + ecmd->tx_max_coalesced_frames = gmac->irq_every_tx_packets;
2113 + ecmd->rx_coalesce_usecs = gmac->rx_coalesce_nsecs/1000;
2114 +
2115 + return 0;
2116 +}
2117 +
2118 +static int gmac_set_coalesce(struct net_device *dev,
2119 + struct ethtool_coalesce *ecmd)
2120 +{
2121 + struct gmac_private *gmac = netdev_priv(dev);
2122 +
2123 + if (ecmd->tx_max_coalesced_frames < 1)
2124 + return -EINVAL;
2125 + if (ecmd->tx_max_coalesced_frames >= 1 << gmac->txq_order)
2126 + return -EINVAL;
2127 +
2128 + gmac->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2129 + gmac->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2130 +
2131 + return 0;
2132 +}
2133 +
2134 +static u32 gmac_get_msglevel(struct net_device *dev)
2135 +{
2136 + struct gmac_private *gmac = netdev_priv(dev);
2137 + return gmac->msg_enable;
2138 +}
2139 +
2140 +static void gmac_set_msglevel(struct net_device *dev, u32 level)
2141 +{
2142 + struct gmac_private *gmac = netdev_priv(dev);
2143 + gmac->msg_enable = level;
2144 +}
2145 +
2146 +static void gmac_get_drvinfo(struct net_device *dev,
2147 + struct ethtool_drvinfo *info)
2148 +{
2149 + strcpy(info->driver, DRV_NAME);
2150 + strcpy(info->version, DRV_VERSION);
2151 + strcpy(info->bus_info, dev->dev_id ? "1" : "0");
2152 +}
2153 +
2154 +static const struct net_device_ops gmac_351x_ops = {
2155 + .ndo_init = gmac_init,
2156 + .ndo_uninit = gmac_uninit,
2157 + .ndo_open = gmac_open,
2158 + .ndo_stop = gmac_stop,
2159 + .ndo_start_xmit = gmac_start_xmit,
2160 + .ndo_tx_timeout = gmac_tx_timeout,
2161 + .ndo_set_rx_mode = gmac_set_rx_mode,
2162 + .ndo_set_mac_address = gmac_set_mac_address,
2163 + .ndo_get_stats64 = gmac_get_stats64,
2164 + .ndo_change_mtu = gmac_change_mtu,
2165 + .ndo_fix_features = gmac_fix_features,
2166 + .ndo_set_features = gmac_set_features,
2167 +};
2168 +
2169 +static const struct ethtool_ops gmac_351x_ethtool_ops = {
2170 + .get_sset_count = gmac_get_sset_count,
2171 + .get_strings = gmac_get_strings,
2172 + .get_ethtool_stats = gmac_get_ethtool_stats,
2173 + .get_settings = gmac_get_settings,
2174 + .set_settings = gmac_set_settings,
2175 + .get_link = ethtool_op_get_link,
2176 + .nway_reset = gmac_nway_reset,
2177 + .get_pauseparam = gmac_get_pauseparam,
2178 + .get_ringparam = gmac_get_ringparam,
2179 + .set_ringparam = gmac_set_ringparam,
2180 + .get_coalesce = gmac_get_coalesce,
2181 + .set_coalesce = gmac_set_coalesce,
2182 + .get_msglevel = gmac_get_msglevel,
2183 + .set_msglevel = gmac_set_msglevel,
2184 + .get_drvinfo = gmac_get_drvinfo,
2185 +};
2186 +
2187 +static int gmac_init_netdev(struct toe_private *toe, int num,
2188 + struct platform_device *pdev)
2189 +{
2190 + struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2191 + struct gmac_private *gmac;
2192 + struct net_device *dev;
2193 + int irq, err;
2194 +
2195 + if (!pdata->bus_id[num])
2196 + return 0;
2197 +
2198 + irq = platform_get_irq(pdev, num);
2199 + if (irq < 0) {
2200 + dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num);
2201 + return irq;
2202 + }
2203 +
2204 + dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM);
2205 + if (!dev) {
2206 + dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num);
2207 + return -ENOMEM;
2208 + }
2209 +
2210 + gmac = netdev_priv(dev);
2211 + gmac->num = num;
2212 + gmac->toe = toe;
2213 + SET_NETDEV_DEV(dev, toe->dev);
2214 +
2215 + toe->netdev[num] = dev;
2216 + dev->dev_id = num;
2217 +
2218 + gmac->ctl_iomem = toe->iomem + TOE_GMAC_BASE(num);
2219 + gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num);
2220 + dev->irq = irq;
2221 +
2222 + dev->netdev_ops = &gmac_351x_ops;
2223 + dev->ethtool_ops = &gmac_351x_ethtool_ops;
2224 +
2225 + spin_lock_init(&gmac->config_lock);
2226 + gmac_clear_hw_stats(dev);
2227 +
2228 + dev->hw_features = GMAC_OFFLOAD_FEATURES;
2229 + dev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2230 +
2231 + gmac->freeq_refill = 0;
2232 + netif_napi_add(dev, &gmac->napi, gmac_napi_poll, DEFAULT_NAPI_WEIGHT);
2233 +
2234 + if (is_valid_ether_addr((void *)toe->mac_addr[num]))
2235 + memcpy(dev->dev_addr, toe->mac_addr[num], ETH_ALEN);
2236 + else
2237 + random_ether_addr(dev->dev_addr);
2238 + __gmac_set_mac_address(dev);
2239 +
2240 + err = gmac_setup_phy(dev);
2241 + if (err)
2242 + netif_warn(gmac, probe, dev,
2243 + "PHY init failed: %d, deferring to ifup time\n", err);
2244 +
2245 + err = register_netdev(dev);
2246 + if (!err)
2247 + {
2248 + pr_info(DRV_NAME " %s: irq %d, dma base 0x%p, io base 0x%p\n",
2249 + dev->name, irq, gmac->dma_iomem, gmac->ctl_iomem);
2250 + return 0;
2251 + }
2252 +
2253 + toe->netdev[num] = NULL;
2254 + free_netdev(dev);
2255 + return err;
2256 +}
2257 +
2258 +static irqreturn_t toe_irq_thread(int irq, void *data)
2259 +{
2260 + struct toe_private *toe = data;
2261 + void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
2262 + void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
2263 + unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2264 + unsigned long flags;
2265 +
2266 + toe_fill_freeq(toe, 0);
2267 +
2268 + /* Ack and enable interrupt */
2269 + spin_lock_irqsave(&toe->irq_lock, flags);
2270 + writel(irqmask, irqif_reg);
2271 + irqmask |= readl(irqen_reg);
2272 + writel(irqmask, irqen_reg);
2273 + spin_unlock_irqrestore(&toe->irq_lock, flags);
2274 +
2275 + return IRQ_HANDLED;
2276 +}
2277 +
2278 +static irqreturn_t toe_irq(int irq, void *data)
2279 +{
2280 + struct toe_private *toe = data;
2281 + void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
2282 + void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
2283 + unsigned long val, en;
2284 + irqreturn_t ret = IRQ_NONE;
2285 +
2286 + spin_lock(&toe->irq_lock);
2287 +
2288 + val = readl(irqif_reg);
2289 + en = readl(irqen_reg);
2290 +
2291 + if (val & en & SWFQ_EMPTY_INT_BIT) {
2292 + en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2293 + | GMAC1_RX_OVERRUN_INT_BIT);
2294 + writel(en, irqen_reg);
2295 + ret = IRQ_WAKE_THREAD;
2296 + }
2297 +
2298 + spin_unlock(&toe->irq_lock);
2299 + return ret;
2300 +}
2301 +
2302 +static int toe_init(struct toe_private *toe,
2303 + struct platform_device *pdev)
2304 +{
2305 + int err;
2306 +
2307 + writel(0, toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2308 + writel(0, toe->iomem + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2309 + writel(0, toe->iomem + GLOBAL_SWFQ_RWPTR_REG);
2310 + writel(0, toe->iomem + GLOBAL_HWFQ_RWPTR_REG);
2311 +
2312 + toe->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2313 + toe->freeq_order = ~0;
2314 +
2315 + err = request_threaded_irq(toe->irq, toe_irq,
2316 + toe_irq_thread, IRQF_SHARED, DRV_NAME " toe", toe);
2317 + if (err)
2318 + goto err_freeq;
2319 +
2320 + return 0;
2321 +
2322 +err_freeq:
2323 + toe_cleanup_freeq(toe);
2324 + return err;
2325 +}
2326 +
2327 +static void toe_deinit(struct toe_private *toe)
2328 +{
2329 + free_irq(toe->irq, toe);
2330 + toe_cleanup_freeq(toe);
2331 +}
2332 +
2333 +static int toe_reset(struct toe_private *toe)
2334 +{
2335 + unsigned int reg = 0, retry = 5;
2336 +
2337 + reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
2338 + GLOBAL_RESET));
2339 + reg |= RESET_GMAC1 | RESET_GMAC0;
2340 + writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
2341 + GLOBAL_RESET));
2342 +
2343 + do {
2344 + udelay(2);
2345 + reg = readl((void __iomem*)(toe->iomem +
2346 + GLOBAL_TOE_VERSION_REG));
2347 + barrier();
2348 + } while (!reg && --retry);
2349 +
2350 + return reg ? 0 : -EIO;
2351 +}
2352 +
2353 +/*
2354 + * Interrupt config:
2355 + *
2356 + * GMAC0 intr bits ------> int0 ----> eth0
2357 + * GMAC1 intr bits ------> int1 ----> eth1
2358 + * TOE intr -------------> int1 ----> eth1
2359 + * Classification Intr --> int0 ----> eth0
2360 + * Default Q0 -----------> int0 ----> eth0
2361 + * Default Q1 -----------> int1 ----> eth1
2362 + * FreeQ intr -----------> int1 ----> eth1
2363 + */
2364 +static void toe_init_irq(struct toe_private *toe)
2365 +{
2366 + writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
2367 + writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
2368 + writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
2369 + writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
2370 + writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
2371 +
2372 + writel(0xCCFC0FC0, toe->iomem + GLOBAL_INTERRUPT_SELECT_0_REG);
2373 + writel(0x00F00002, toe->iomem + GLOBAL_INTERRUPT_SELECT_1_REG);
2374 + writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_2_REG);
2375 + writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_3_REG);
2376 + writel(0xFF000003, toe->iomem + GLOBAL_INTERRUPT_SELECT_4_REG);
2377 +
2378 + /* edge-triggered interrupts packed to level-triggered one... */
2379 + writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
2380 + writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
2381 + writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
2382 + writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
2383 + writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
2384 +}
2385 +
2386 +static void toe_save_mac_addr(struct toe_private *toe,
2387 + struct platform_device *pdev)
2388 +{
2389 + struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2390 + void __iomem *ctl;
2391 + int i;
2392 +
2393 + for (i = 0; i < 2; i++) {
2394 + if (pdata->bus_id[i]) {
2395 + ctl = toe->iomem + TOE_GMAC_BASE(i);
2396 + toe->mac_addr[i][0] = cpu_to_le32(readl(ctl + GMAC_STA_ADD0));
2397 + toe->mac_addr[i][1] = cpu_to_le32(readl(ctl + GMAC_STA_ADD1));
2398 + toe->mac_addr[i][2] = cpu_to_le32(readl(ctl + GMAC_STA_ADD2));
2399 + }
2400 + }
2401 +}
2402 +
2403 +static int gemini_gmac_probe(struct platform_device *pdev)
2404 +{
2405 + struct resource *res;
2406 + struct toe_private *toe;
2407 + int irq, retval;
2408 +
2409 + if (!pdev->dev.platform_data)
2410 + return -EINVAL;
2411 +
2412 + irq = platform_get_irq(pdev, 1);
2413 + if (irq < 0)
2414 + return irq;
2415 +
2416 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2417 + if (!res) {
2418 + dev_err(&pdev->dev, "can't get device resources\n");
2419 + return -ENODEV;
2420 + }
2421 +
2422 + toe = kzalloc(sizeof(*toe), GFP_KERNEL);
2423 + if (!toe)
2424 + return -ENOMEM;
2425 +
2426 + platform_set_drvdata(pdev, toe);
2427 + toe->dev = &pdev->dev;
2428 + toe->irq = irq;
2429 +
2430 + toe->iomem = ioremap(res->start, resource_size(res));
2431 + if (!toe->iomem) {
2432 + dev_err(toe->dev, "ioremap failed\n");
2433 + retval = -EIO;
2434 + goto err_data;
2435 + }
2436 +
2437 + toe_save_mac_addr(toe, pdev);
2438 +
2439 + retval = toe_reset(toe);
2440 + if (retval < 0)
2441 + goto err_unmap;
2442 +
2443 + pr_info(DRV_NAME " toe: irq %d, io base 0x%08x, version %d\n",
2444 + irq, res->start, retval);
2445 +
2446 + spin_lock_init(&toe->irq_lock);
2447 + spin_lock_init(&toe->freeq_lock);
2448 +
2449 + toe_init_irq(toe);
2450 +
2451 + retval = toe_init(toe, pdev);
2452 + if (retval)
2453 + goto err_unmap;
2454 +
2455 + retval = gmac_init_netdev(toe, 0, pdev);
2456 + if (retval)
2457 + goto err_uninit;
2458 +
2459 + retval = gmac_init_netdev(toe, 1, pdev);
2460 + if (retval)
2461 + goto err_uninit;
2462 +
2463 + return 0;
2464 +
2465 +err_uninit:
2466 + if (toe->netdev[0])
2467 + unregister_netdev(toe->netdev[0]);
2468 + toe_deinit(toe);
2469 +err_unmap:
2470 + iounmap(toe->iomem);
2471 +err_data:
2472 + kfree(toe);
2473 + return retval;
2474 +}
2475 +
2476 +static int gemini_gmac_remove(struct platform_device *pdev)
2477 +{
2478 + struct toe_private *toe = platform_get_drvdata(pdev);
2479 + int i;
2480 +
2481 + for (i = 0; i < 2; i++)
2482 + if (toe->netdev[i])
2483 + unregister_netdev(toe->netdev[i]);
2484 +
2485 + toe_init_irq(toe);
2486 + toe_deinit(toe);
2487 +
2488 + iounmap(toe->iomem);
2489 + kfree(toe);
2490 +
2491 + return 0;
2492 +}
2493 +
2494 +static struct platform_driver gemini_gmac_driver = {
2495 + .probe = gemini_gmac_probe,
2496 + .remove = gemini_gmac_remove,
2497 + .driver.name = DRV_NAME,
2498 + .driver.owner = THIS_MODULE,
2499 +};
2500 +
2501 +static int __init gemini_gmac_init(void)
2502 +{
2503 +#ifdef CONFIG_MDIO_GPIO_MODULE
2504 + request_module("mdio-gpio");
2505 +#endif
2506 + return platform_driver_register(&gemini_gmac_driver);
2507 +}
2508 +
2509 +static void __exit gemini_gmac_exit(void)
2510 +{
2511 + platform_driver_unregister(&gemini_gmac_driver);
2512 +}
2513 +
2514 +module_init(gemini_gmac_init);
2515 +module_exit(gemini_gmac_exit);
2516 --- /dev/null
2517 +++ b/drivers/net/ethernet/gemini/sl351x_hw.h
2518 @@ -0,0 +1,1436 @@
2519 +/*
2520 + * Register definitions for Gemini LEPUS GMAC Ethernet device driver.
2521 + *
2522 + * Copyright (C) 2006, Storlink, Corp.
2523 + * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2524 + * Copyright (C) 2010, Michał Mirosław <mirq-linux@rere.qmqm.pl>
2525 + *
2526 + * This program is free software; you can redistribute it and/or modify
2527 + * it under the terms of the GNU General Public License as published by
2528 + * the Free Software Foundation; either version 2 of the License, or
2529 + * (at your option) any later version.
2530 + */
2531 +#ifndef _GMAC_HW_H
2532 +#define _GMAC_HW_H
2533 +
2534 +#include <linux/bitops.h>
2535 +
2536 +/*
2537 + * Base Registers
2538 + */
2539 +#define TOE_NONTOE_QUE_HDR_BASE 0x2000
2540 +#define TOE_TOE_QUE_HDR_BASE 0x3000
2541 +#define TOE_V_BIT_BASE 0x4000
2542 +#define TOE_A_BIT_BASE 0x6000
2543 +#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
2544 +#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
2545 +
2546 +/*
2547 + * Queue ID
2548 + */
2549 +#define TOE_SW_FREE_QID 0x00
2550 +#define TOE_HW_FREE_QID 0x01
2551 +#define TOE_GMAC0_SW_TXQ0_QID 0x02
2552 +#define TOE_GMAC0_SW_TXQ1_QID 0x03
2553 +#define TOE_GMAC0_SW_TXQ2_QID 0x04
2554 +#define TOE_GMAC0_SW_TXQ3_QID 0x05
2555 +#define TOE_GMAC0_SW_TXQ4_QID 0x06
2556 +#define TOE_GMAC0_SW_TXQ5_QID 0x07
2557 +#define TOE_GMAC0_HW_TXQ0_QID 0x08
2558 +#define TOE_GMAC0_HW_TXQ1_QID 0x09
2559 +#define TOE_GMAC0_HW_TXQ2_QID 0x0A
2560 +#define TOE_GMAC0_HW_TXQ3_QID 0x0B
2561 +#define TOE_GMAC1_SW_TXQ0_QID 0x12
2562 +#define TOE_GMAC1_SW_TXQ1_QID 0x13
2563 +#define TOE_GMAC1_SW_TXQ2_QID 0x14
2564 +#define TOE_GMAC1_SW_TXQ3_QID 0x15
2565 +#define TOE_GMAC1_SW_TXQ4_QID 0x16
2566 +#define TOE_GMAC1_SW_TXQ5_QID 0x17
2567 +#define TOE_GMAC1_HW_TXQ0_QID 0x18
2568 +#define TOE_GMAC1_HW_TXQ1_QID 0x19
2569 +#define TOE_GMAC1_HW_TXQ2_QID 0x1A
2570 +#define TOE_GMAC1_HW_TXQ3_QID 0x1B
2571 +#define TOE_GMAC0_DEFAULT_QID 0x20
2572 +#define TOE_GMAC1_DEFAULT_QID 0x21
2573 +#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
2574 +#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
2575 +
2576 +/*
2577 + * old info:
2578 + * TOE DMA Queue Size should be 2^n, n = 6...12
2579 + * TOE DMA Queues are the following queue types:
2580 + * SW Free Queue, HW Free Queue,
2581 + * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
2582 + * The base address and descriptor number are configured at
2583 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2584 + */
2585 +
2586 +#define GET_WPTR(addr) __raw_readw((addr) + 2)
2587 +#define GET_RPTR(addr) __raw_readw((addr))
2588 +#define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2)
2589 +#define SET_RPTR(addr, data) __raw_writew((data), (addr))
2590 +#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
2591 +#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
2592 +#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
2593 +#define __RWPTR_MASK(order) ((1 << (order)) - 1)
2594 +#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
2595 +#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
2596 +#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
2597 + __RWPTR_MASK((order)))
2598 +
2599 +/*
2600 + * Global registers
2601 + * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
2602 + * Base 0x60000000
2603 + */
2604 +#define GLOBAL_TOE_VERSION_REG 0x0000
2605 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
2606 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
2607 +#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
2608 +#define GLOBAL_SWFQ_RWPTR_REG 0x0014
2609 +#define GLOBAL_HWFQ_RWPTR_REG 0x0018
2610 +#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
2611 +#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
2612 +#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
2613 +#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
2614 +#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
2615 +#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
2616 +#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
2617 +#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
2618 +#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
2619 +#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
2620 +#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
2621 +#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
2622 +#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
2623 +#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
2624 +#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
2625 +#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
2626 +#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
2627 +
2628 +/*
2629 + * GMAC 0/1 DMA/TOE register
2630 + * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
2631 + * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
2632 + * Base 0x60008000 or 0x6000C000
2633 + */
2634 +#define GMAC_DMA_CTRL_REG 0x0000
2635 +#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
2636 +#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
2637 +#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
2638 +#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
2639 +#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
2640 +#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
2641 +#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
2642 +#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
2643 +#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
2644 +#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
2645 +#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
2646 +#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
2647 +#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
2648 +#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
2649 +#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
2650 +#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
2651 +#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
2652 +#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
2653 +#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
2654 +#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
2655 +#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
2656 +#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
2657 +#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
2658 +#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
2659 +#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
2660 +#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
2661 +#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
2662 +#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
2663 +#define GMAC_HASH_ENGINE_REG0 0x0070
2664 +#define GMAC_HASH_ENGINE_REG1 0x0074
2665 +/* matching rule 0 Control register 0 */
2666 +#define GMAC_MR0CR0 0x0078
2667 +#define GMAC_MR0CR1 0x007C
2668 +#define GMAC_MR0CR2 0x0080
2669 +#define GMAC_MR1CR0 0x0084
2670 +#define GMAC_MR1CR1 0x0088
2671 +#define GMAC_MR1CR2 0x008C
2672 +#define GMAC_MR2CR0 0x0090
2673 +#define GMAC_MR2CR1 0x0094
2674 +#define GMAC_MR2CR2 0x0098
2675 +#define GMAC_MR3CR0 0x009C
2676 +#define GMAC_MR3CR1 0x00A0
2677 +#define GMAC_MR3CR2 0x00A4
2678 +/* Support Protocol Regsister 0 */
2679 +#define GMAC_SPR0 0x00A8
2680 +#define GMAC_SPR1 0x00AC
2681 +#define GMAC_SPR2 0x00B0
2682 +#define GMAC_SPR3 0x00B4
2683 +#define GMAC_SPR4 0x00B8
2684 +#define GMAC_SPR5 0x00BC
2685 +#define GMAC_SPR6 0x00C0
2686 +#define GMAC_SPR7 0x00C4
2687 +/* GMAC Hash/Rx/Tx AHB Weighting register */
2688 +#define GMAC_AHB_WEIGHT_REG 0x00C8
2689 +
2690 +/*
2691 + * TOE GMAC 0/1 register
2692 + * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
2693 + * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
2694 + * Base 0x6000A000 or 0x6000E000
2695 + */
2696 +enum GMAC_REGISTER {
2697 + GMAC_STA_ADD0 = 0x0000,
2698 + GMAC_STA_ADD1 = 0x0004,
2699 + GMAC_STA_ADD2 = 0x0008,
2700 + GMAC_RX_FLTR = 0x000c,
2701 + GMAC_MCAST_FIL0 = 0x0010,
2702 + GMAC_MCAST_FIL1 = 0x0014,
2703 + GMAC_CONFIG0 = 0x0018,
2704 + GMAC_CONFIG1 = 0x001c,
2705 + GMAC_CONFIG2 = 0x0020,
2706 + GMAC_CONFIG3 = 0x0024,
2707 + GMAC_RESERVED = 0x0028,
2708 + GMAC_STATUS = 0x002c,
2709 + GMAC_IN_DISCARDS= 0x0030,
2710 + GMAC_IN_ERRORS = 0x0034,
2711 + GMAC_IN_MCAST = 0x0038,
2712 + GMAC_IN_BCAST = 0x003c,
2713 + GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
2714 + GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
2715 +};
2716 +
2717 +#define RX_STATS_NUM 6
2718 +
2719 +/*
2720 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
2721 + */
2722 +typedef union {
2723 + unsigned int bits32;
2724 + unsigned int base_size;
2725 +} DMA_Q_BASE_SIZE_T;
2726 +#define DMA_Q_BASE_MASK (~0x0f)
2727 +
2728 +/*
2729 + * DMA SKB Buffer register (offset 0x0008)
2730 + */
2731 +typedef union {
2732 + unsigned int bits32;
2733 + struct bit_0008 {
2734 + unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
2735 + unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
2736 + } bits;
2737 +} DMA_SKB_SIZE_T;
2738 +
2739 +/*
2740 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
2741 + */
2742 +typedef union {
2743 + unsigned int bits32;
2744 + struct bit_000c {
2745 + unsigned int rptr : 16; /* Read Ptr, RO */
2746 + unsigned int wptr : 16; /* Write Ptr, RW */
2747 + } bits;
2748 +} DMA_RWPTR_T;
2749 +
2750 +/*
2751 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
2752 + * see DMA_RWPTR_T structure
2753 + */
2754 +
2755 +/*
2756 + * Interrupt Status Register 0 (offset 0x0020)
2757 + * Interrupt Mask Register 0 (offset 0x0024)
2758 + * Interrupt Select Register 0 (offset 0x0028)
2759 + */
2760 +typedef union {
2761 + unsigned int bits32;
2762 + struct bit_0020 {
2763 + /* GMAC0 SW Tx Queue 0 EOF Interrupt */
2764 + unsigned int swtq00_eof : 1;
2765 + unsigned int swtq01_eof : 1;
2766 + unsigned int swtq02_eof : 1;
2767 + unsigned int swtq03_eof : 1;
2768 + unsigned int swtq04_eof : 1;
2769 + unsigned int swtq05_eof : 1;
2770 + /* GMAC1 SW Tx Queue 0 EOF Interrupt */
2771 + unsigned int swtq10_eof : 1;
2772 + unsigned int swtq11_eof : 1;
2773 + unsigned int swtq12_eof : 1;
2774 + unsigned int swtq13_eof : 1;
2775 + unsigned int swtq14_eof : 1;
2776 + unsigned int swtq15_eof : 1;
2777 + /* GMAC0 SW Tx Queue 0 Finish Interrupt */
2778 + unsigned int swtq00_fin : 1;
2779 + unsigned int swtq01_fin : 1;
2780 + unsigned int swtq02_fin : 1;
2781 + unsigned int swtq03_fin : 1;
2782 + unsigned int swtq04_fin : 1;
2783 + unsigned int swtq05_fin : 1;
2784 + /* GMAC1 SW Tx Queue 0 Finish Interrupt */
2785 + unsigned int swtq10_fin : 1;
2786 + unsigned int swtq11_fin : 1;
2787 + unsigned int swtq12_fin : 1;
2788 + unsigned int swtq13_fin : 1;
2789 + unsigned int swtq14_fin : 1;
2790 + unsigned int swtq15_fin : 1;
2791 + /* GMAC0 Rx Descriptor Protocol Error */
2792 + unsigned int rxPerr0 : 1;
2793 + /* GMAC0 AHB Bus Error while Rx */
2794 + unsigned int rxDerr0 : 1;
2795 + /* GMAC1 Rx Descriptor Protocol Error */
2796 + unsigned int rxPerr1 : 1;
2797 + /* GMAC1 AHB Bus Error while Rx */
2798 + unsigned int rxDerr1 : 1;
2799 + /* GMAC0 Tx Descriptor Protocol Error */
2800 + unsigned int txPerr0 : 1;
2801 + /* GMAC0 AHB Bus Error while Tx */
2802 + unsigned int txDerr0 : 1;
2803 + /* GMAC1 Tx Descriptor Protocol Error */
2804 + unsigned int txPerr1 : 1;
2805 + /* GMAC1 AHB Bus Error while Tx */
2806 + unsigned int txDerr1 : 1;
2807 + } bits;
2808 +} INTR_REG0_T;
2809 +
2810 +#define GMAC1_TXDERR_INT_BIT BIT(31)
2811 +#define GMAC1_TXPERR_INT_BIT BIT(30)
2812 +#define GMAC0_TXDERR_INT_BIT BIT(29)
2813 +#define GMAC0_TXPERR_INT_BIT BIT(28)
2814 +#define GMAC1_RXDERR_INT_BIT BIT(27)
2815 +#define GMAC1_RXPERR_INT_BIT BIT(26)
2816 +#define GMAC0_RXDERR_INT_BIT BIT(25)
2817 +#define GMAC0_RXPERR_INT_BIT BIT(24)
2818 +#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
2819 +#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
2820 +#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
2821 +#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
2822 +#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
2823 +#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
2824 +#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
2825 +#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
2826 +#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
2827 +#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
2828 +#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
2829 +#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
2830 +#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
2831 +#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
2832 +#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
2833 +#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
2834 +#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
2835 +#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
2836 +#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
2837 +#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
2838 +#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
2839 +#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
2840 +#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
2841 +#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
2842 +
2843 +/*
2844 + * Interrupt Status Register 1 (offset 0x0030)
2845 + * Interrupt Mask Register 1 (offset 0x0034)
2846 + * Interrupt Select Register 1 (offset 0x0038)
2847 + */
2848 +typedef union {
2849 + unsigned int bits32;
2850 + struct bit_0030 {
2851 + unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
2852 + unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
2853 + unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
2854 + unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
2855 + unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
2856 + unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
2857 + unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
2858 + unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
2859 + unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
2860 + unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
2861 + unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
2862 + unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
2863 + unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
2864 + unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
2865 + unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
2866 + unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
2867 + unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
2868 + unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
2869 + unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
2870 + } bits;
2871 +} INTR_REG1_T;
2872 +
2873 +#define TOE_IQ3_FULL_INT_BIT BIT(31)
2874 +#define TOE_IQ2_FULL_INT_BIT BIT(30)
2875 +#define TOE_IQ1_FULL_INT_BIT BIT(29)
2876 +#define TOE_IQ0_FULL_INT_BIT BIT(28)
2877 +#define TOE_IQ3_INT_BIT BIT(27)
2878 +#define TOE_IQ2_INT_BIT BIT(26)
2879 +#define TOE_IQ1_INT_BIT BIT(25)
2880 +#define TOE_IQ0_INT_BIT BIT(24)
2881 +#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
2882 +#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
2883 +#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
2884 +#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
2885 +#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
2886 +#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
2887 +#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
2888 +#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
2889 +#define CLASS_RX_INT_BIT(x) BIT((x + 2))
2890 +#define DEFAULT_Q1_INT_BIT BIT(1)
2891 +#define DEFAULT_Q0_INT_BIT BIT(0)
2892 +
2893 +#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
2894 + TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
2895 +#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
2896 + TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
2897 +#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
2898 +#define TOE_CLASS_RX_INT_BITS 0xfffc
2899 +
2900 +/*
2901 + * Interrupt Status Register 2 (offset 0x0040)
2902 + * Interrupt Mask Register 2 (offset 0x0044)
2903 + * Interrupt Select Register 2 (offset 0x0048)
2904 + */
2905 +typedef union {
2906 + unsigned int bits32;
2907 + struct bit_0040 {
2908 + unsigned int toe_q0_full : 1; /* bit 0 TOE Queue 0 Full Interrupt */
2909 + unsigned int toe_q1_full : 1; /* bit 1 TOE Queue 1 Full Interrupt */
2910 + unsigned int toe_q2_full : 1; /* bit 2 TOE Queue 2 Full Interrupt */
2911 + unsigned int toe_q3_full : 1; /* bit 3 TOE Queue 3 Full Interrupt */
2912 + unsigned int toe_q4_full : 1; /* bit 4 TOE Queue 4 Full Interrupt */
2913 + unsigned int toe_q5_full : 1; /* bit 5 TOE Queue 5 Full Interrupt */
2914 + unsigned int toe_q6_full : 1; /* bit 6 TOE Queue 6 Full Interrupt */
2915 + unsigned int toe_q7_full : 1; /* bit 7 TOE Queue 7 Full Interrupt */
2916 + unsigned int toe_q8_full : 1; /* bit 8 TOE Queue 8 Full Interrupt */
2917 + unsigned int toe_q9_full : 1; /* bit 9 TOE Queue 9 Full Interrupt */
2918 + unsigned int toe_q10_full : 1; /* bit 10 TOE Queue 10 Full Interrupt */
2919 + unsigned int toe_q11_full : 1; /* bit 11 TOE Queue 11 Full Interrupt */
2920 + unsigned int toe_q12_full : 1; /* bit 12 TOE Queue 12 Full Interrupt */
2921 + unsigned int toe_q13_full : 1; /* bit 13 TOE Queue 13 Full Interrupt */
2922 + unsigned int toe_q14_full : 1; /* bit 14 TOE Queue 14 Full Interrupt */
2923 + unsigned int toe_q15_full : 1; /* bit 15 TOE Queue 15 Full Interrupt */
2924 + unsigned int toe_q16_full : 1; /* bit 16 TOE Queue 16 Full Interrupt */
2925 + unsigned int toe_q17_full : 1; /* bit 17 TOE Queue 17 Full Interrupt */
2926 + unsigned int toe_q18_full : 1; /* bit 18 TOE Queue 18 Full Interrupt */
2927 + unsigned int toe_q19_full : 1; /* bit 19 TOE Queue 19 Full Interrupt */
2928 + unsigned int toe_q20_full : 1; /* bit 20 TOE Queue 20 Full Interrupt */
2929 + unsigned int toe_q21_full : 1; /* bit 21 TOE Queue 21 Full Interrupt */
2930 + unsigned int toe_q22_full : 1; /* bit 22 TOE Queue 22 Full Interrupt */
2931 + unsigned int toe_q23_full : 1; /* bit 23 TOE Queue 23 Full Interrupt */
2932 + unsigned int toe_q24_full : 1; /* bit 24 TOE Queue 24 Full Interrupt */
2933 + unsigned int toe_q25_full : 1; /* bit 25 TOE Queue 25 Full Interrupt */
2934 + unsigned int toe_q26_full : 1; /* bit 26 TOE Queue 26 Full Interrupt */
2935 + unsigned int toe_q27_full : 1; /* bit 27 TOE Queue 27 Full Interrupt */
2936 + unsigned int toe_q28_full : 1; /* bit 28 TOE Queue 28 Full Interrupt */
2937 + unsigned int toe_q29_full : 1; /* bit 29 TOE Queue 29 Full Interrupt */
2938 + unsigned int toe_q30_full : 1; /* bit 30 TOE Queue 30 Full Interrupt */
2939 + unsigned int toe_q31_full : 1; /* bit 31 TOE Queue 31 Full Interrupt */
2940 + } bits;
2941 +} INTR_REG2_T;
2942 +
2943 +#define TOE_QL_FULL_INT_BIT(x) BIT(x)
2944 +
2945 +/*
2946 + * Interrupt Status Register 3 (offset 0x0050)
2947 + * Interrupt Mask Register 3 (offset 0x0054)
2948 + * Interrupt Select Register 3 (offset 0x0058)
2949 + */
2950 +typedef union {
2951 + unsigned int bits32;
2952 + struct bit_0050 {
2953 + unsigned int toe_q32_full : 1; /* bit 32 TOE Queue 32 Full Interrupt */
2954 + unsigned int toe_q33_full : 1; /* bit 33 TOE Queue 33 Full Interrupt */
2955 + unsigned int toe_q34_full : 1; /* bit 34 TOE Queue 34 Full Interrupt */
2956 + unsigned int toe_q35_full : 1; /* bit 35 TOE Queue 35 Full Interrupt */
2957 + unsigned int toe_q36_full : 1; /* bit 36 TOE Queue 36 Full Interrupt */
2958 + unsigned int toe_q37_full : 1; /* bit 37 TOE Queue 37 Full Interrupt */
2959 + unsigned int toe_q38_full : 1; /* bit 38 TOE Queue 38 Full Interrupt */
2960 + unsigned int toe_q39_full : 1; /* bit 39 TOE Queue 39 Full Interrupt */
2961 + unsigned int toe_q40_full : 1; /* bit 40 TOE Queue 40 Full Interrupt */
2962 + unsigned int toe_q41_full : 1; /* bit 41 TOE Queue 41 Full Interrupt */
2963 + unsigned int toe_q42_full : 1; /* bit 42 TOE Queue 42 Full Interrupt */
2964 + unsigned int toe_q43_full : 1; /* bit 43 TOE Queue 43 Full Interrupt */
2965 + unsigned int toe_q44_full : 1; /* bit 44 TOE Queue 44 Full Interrupt */
2966 + unsigned int toe_q45_full : 1; /* bit 45 TOE Queue 45 Full Interrupt */
2967 + unsigned int toe_q46_full : 1; /* bit 46 TOE Queue 46 Full Interrupt */
2968 + unsigned int toe_q47_full : 1; /* bit 47 TOE Queue 47 Full Interrupt */
2969 + unsigned int toe_q48_full : 1; /* bit 48 TOE Queue 48 Full Interrupt */
2970 + unsigned int toe_q49_full : 1; /* bit 49 TOE Queue 49 Full Interrupt */
2971 + unsigned int toe_q50_full : 1; /* bit 50 TOE Queue 50 Full Interrupt */
2972 + unsigned int toe_q51_full : 1; /* bit 51 TOE Queue 51 Full Interrupt */
2973 + unsigned int toe_q52_full : 1; /* bit 52 TOE Queue 52 Full Interrupt */
2974 + unsigned int toe_q53_full : 1; /* bit 53 TOE Queue 53 Full Interrupt */
2975 + unsigned int toe_q54_full : 1; /* bit 54 TOE Queue 54 Full Interrupt */
2976 + unsigned int toe_q55_full : 1; /* bit 55 TOE Queue 55 Full Interrupt */
2977 + unsigned int toe_q56_full : 1; /* bit 56 TOE Queue 56 Full Interrupt */
2978 + unsigned int toe_q57_full : 1; /* bit 57 TOE Queue 57 Full Interrupt */
2979 + unsigned int toe_q58_full : 1; /* bit 58 TOE Queue 58 Full Interrupt */
2980 + unsigned int toe_q59_full : 1; /* bit 59 TOE Queue 59 Full Interrupt */
2981 + unsigned int toe_q60_full : 1; /* bit 60 TOE Queue 60 Full Interrupt */
2982 + unsigned int toe_q61_full : 1; /* bit 61 TOE Queue 61 Full Interrupt */
2983 + unsigned int toe_q62_full : 1; /* bit 62 TOE Queue 62 Full Interrupt */
2984 + unsigned int toe_q63_full : 1; /* bit 63 TOE Queue 63 Full Interrupt */
2985 + } bits;
2986 +} INTR_REG3_T;
2987 +
2988 +#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
2989 +
2990 +/*
2991 + * Interrupt Status Register 4 (offset 0x0060)
2992 + * Interrupt Mask Register 4 (offset 0x0064)
2993 + * Interrupt Select Register 4 (offset 0x0068)
2994 + */
2995 +typedef union {
2996 + unsigned char byte;
2997 + struct bit_0060 {
2998 + unsigned char status_changed : 1; /* Status Changed Intr for RGMII Mode */
2999 + unsigned char rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */
3000 + unsigned char tx_pause_off : 1; /* received pause off frame interrupt */
3001 + unsigned char rx_pause_off : 1; /* received pause off frame interrupt */
3002 + unsigned char tx_pause_on : 1; /* transmit pause on frame interrupt */
3003 + unsigned char rx_pause_on : 1; /* received pause on frame interrupt */
3004 + unsigned char cnt_full : 1; /* MIB counters half full interrupt */
3005 + unsigned char reserved : 1; /* */
3006 + } __packed bits;
3007 +} __packed GMAC_INTR_T;
3008 +
3009 +typedef union {
3010 + unsigned int bits32;
3011 + struct bit_0060_2 {
3012 + unsigned int swfq_empty : 1; /* bit 0 Software Free Queue Empty Intr. */
3013 + unsigned int hwfq_empty : 1; /* bit 1 Hardware Free Queue Empty Intr. */
3014 + unsigned int class_qf_int : 14; /* bit 15:2 Classification Rx Queue13-0 Full Intr. */
3015 + GMAC_INTR_T gmac0;
3016 + GMAC_INTR_T gmac1;
3017 + } bits;
3018 +} INTR_REG4_T;
3019 +
3020 +#define GMAC1_RESERVED_INT_BIT BIT(31)
3021 +#define GMAC1_MIB_INT_BIT BIT(30)
3022 +#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
3023 +#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
3024 +#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
3025 +#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
3026 +#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
3027 +#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
3028 +#define GMAC0_RESERVED_INT_BIT BIT(23)
3029 +#define GMAC0_MIB_INT_BIT BIT(22)
3030 +#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
3031 +#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
3032 +#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
3033 +#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
3034 +#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
3035 +#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
3036 +#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
3037 +#define HWFQ_EMPTY_INT_BIT BIT(1)
3038 +#define SWFQ_EMPTY_INT_BIT BIT(0)
3039 +
3040 +#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
3041 + GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
3042 + GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
3043 + GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
3044 +#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
3045 + GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
3046 + GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
3047 + GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
3048 +
3049 +#define CLASS_RX_FULL_INT_BITS 0xfffc
3050 +
3051 +/*
3052 + * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
3053 + */
3054 +typedef union {
3055 + unsigned int bits32;
3056 + struct bit_0070_2 {
3057 + unsigned int swfq_empty : 8; /* 7:0 Software Free Queue Empty Threshold */
3058 + unsigned int hwfq_empty : 8; /* 15:8 Hardware Free Queue Empty Threshold */
3059 + unsigned int intrq : 8; /* 23:16 */
3060 + unsigned int toe_class : 8; /* 31:24 */
3061 + } bits;
3062 +} QUEUE_THRESHOLD_T;
3063 +
3064 +
3065 +/*
3066 + * GMAC DMA Control Register
3067 + * GMAC0 offset 0x8000
3068 + * GMAC1 offset 0xC000
3069 + */
3070 +typedef union {
3071 + unsigned int bits32;
3072 + struct bit_8000 {
3073 + unsigned int td_bus : 2; /* bit 1:0 Peripheral Bus Width */
3074 + unsigned int td_burst_size : 2; /* bit 3:2 TxDMA max burst size for every AHB request */
3075 + unsigned int td_prot : 4; /* bit 7:4 TxDMA protection control */
3076 + unsigned int rd_bus : 2; /* bit 9:8 Peripheral Bus Width */
3077 + unsigned int rd_burst_size : 2; /* bit 11:10 DMA max burst size for every AHB request */
3078 + unsigned int rd_prot : 4; /* bit 15:12 DMA Protection Control */
3079 + unsigned int rd_insert_bytes : 2; /* bit 17:16 */
3080 + unsigned int reserved : 10; /* bit 27:18 */
3081 + unsigned int drop_small_ack : 1; /* bit 28 1: Drop, 0: Accept */
3082 + unsigned int loopback : 1; /* bit 29 Loopback TxDMA to RxDMA */
3083 + unsigned int td_enable : 1; /* bit 30 Tx DMA Enable */
3084 + unsigned int rd_enable : 1; /* bit 31 Rx DMA Enable */
3085 + } bits;
3086 +} GMAC_DMA_CTRL_T;
3087 +
3088 +/*
3089 + * GMAC Tx Weighting Control Register 0
3090 + * GMAC0 offset 0x8004
3091 + * GMAC1 offset 0xC004
3092 + */
3093 +typedef union {
3094 + unsigned int bits32;
3095 + struct bit_8004 {
3096 + unsigned int hw_tq0 : 6; /* bit 5:0 HW TX Queue 3 */
3097 + unsigned int hw_tq1 : 6; /* bit 11:6 HW TX Queue 2 */
3098 + unsigned int hw_tq2 : 6; /* bit 17:12 HW TX Queue 1 */
3099 + unsigned int hw_tq3 : 6; /* bit 23:18 HW TX Queue 0 */
3100 + unsigned int reserved : 8; /* bit 31:24 */
3101 + } bits;
3102 +} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
3103 +
3104 +/*
3105 + * GMAC Tx Weighting Control Register 1
3106 + * GMAC0 offset 0x8008
3107 + * GMAC1 offset 0xC008
3108 + */
3109 +typedef union {
3110 + unsigned int bits32;
3111 + struct bit_8008 {
3112 + unsigned int sw_tq0 : 5; /* bit 4:0 SW TX Queue 0 */
3113 + unsigned int sw_tq1 : 5; /* bit 9:5 SW TX Queue 1 */
3114 + unsigned int sw_tq2 : 5; /* bit 14:10 SW TX Queue 2 */
3115 + unsigned int sw_tq3 : 5; /* bit 19:15 SW TX Queue 3 */
3116 + unsigned int sw_tq4 : 5; /* bit 24:20 SW TX Queue 4 */
3117 + unsigned int sw_tq5 : 5; /* bit 29:25 SW TX Queue 5 */
3118 + unsigned int reserved : 2; /* bit 31:30 */
3119 + } bits;
3120 +} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
3121 +
3122 +/*
3123 + * Queue Read/Write Pointer
3124 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
3125 + * GMAC0 offset 0x800C ~ 0x8020
3126 + * GMAC1 offset 0xC00C ~ 0xC020
3127 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
3128 + * GMAC0 offset 0x8024 ~ 0x8030
3129 + * GMAC1 offset 0xC024 ~ 0xC030
3130 + *
3131 + * see DMA_RWPTR_T structure
3132 + */
3133 +
3134 +/*
3135 + * GMAC DMA Tx First Description Address Register
3136 + * GMAC0 offset 0x8038
3137 + * GMAC1 offset 0xC038
3138 + */
3139 +typedef union {
3140 + unsigned int bits32;
3141 + struct bit_8038 {
3142 + unsigned int reserved : 3;
3143 + unsigned int td_busy : 1; /* bit 3 1: TxDMA busy; 0: TxDMA idle */
3144 + unsigned int td_first_des_ptr : 28; /* bit 31:4 first descriptor address */
3145 + } bits;
3146 +} GMAC_TXDMA_FIRST_DESC_T;
3147 +
3148 +/*
3149 + * GMAC DMA Tx Current Description Address Register
3150 + * GMAC0 offset 0x803C
3151 + * GMAC1 offset 0xC03C
3152 + */
3153 +typedef union {
3154 + unsigned int bits32;
3155 + struct bit_803C {
3156 + unsigned int reserved : 4;
3157 + unsigned int td_curr_desc_ptr : 28; /* bit 31:4 current descriptor address */
3158 + } bits;
3159 +} GMAC_TXDMA_CURR_DESC_T;
3160 +
3161 +/*
3162 + * GMAC DMA Tx Description Word 0 Register
3163 + * GMAC0 offset 0x8040
3164 + * GMAC1 offset 0xC040
3165 + */
3166 +typedef union {
3167 + unsigned int bits32;
3168 + struct bit_8040 {
3169 + unsigned int buffer_size : 16; /* bit 15:0 Transfer size */
3170 + unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
3171 + unsigned int status_tx_ok : 1; /* bit 22 Tx Status, 1: Successful 0: Failed */
3172 + unsigned int status_rvd : 6; /* bit 28:23 Tx Status, Reserved bits */
3173 + unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
3174 + unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
3175 + unsigned int reserved : 1; /* bit 31 */
3176 + } bits;
3177 +} GMAC_TXDESC_0_T;
3178 +
3179 +/*
3180 + * GMAC DMA Tx Description Word 1 Register
3181 + * GMAC0 offset 0x8044
3182 + * GMAC1 offset 0xC044
3183 + */
3184 +typedef union {
3185 + unsigned int bits32;
3186 + struct txdesc_word1 {
3187 + unsigned int byte_count : 16; /* bit 15: 0 Tx Frame Byte Count */
3188 + unsigned int mtu_enable : 1; /* bit 16 TSS segmentation use MTU setting */
3189 + unsigned int ip_chksum : 1; /* bit 17 IPV4 Header Checksum Enable */
3190 + unsigned int ipv6_enable : 1; /* bit 18 IPV6 Tx Enable */
3191 + unsigned int tcp_chksum : 1; /* bit 19 TCP Checksum Enable */
3192 + unsigned int udp_chksum : 1; /* bit 20 UDP Checksum Enable */
3193 + unsigned int bypass_tss : 1; /* bit 21 Bypass HW offload engine */
3194 + unsigned int ip_fixed_len : 1; /* bit 22 Don't update IP length field */
3195 + unsigned int reserved : 9; /* bit 31:23 Tx Flag, Reserved */
3196 + } bits;
3197 +} GMAC_TXDESC_1_T;
3198 +
3199 +#define TSS_IP_FIXED_LEN_BIT BIT(22)
3200 +#define TSS_BYPASS_BIT BIT(21)
3201 +#define TSS_UDP_CHKSUM_BIT BIT(20)
3202 +#define TSS_TCP_CHKSUM_BIT BIT(19)
3203 +#define TSS_IPV6_ENABLE_BIT BIT(18)
3204 +#define TSS_IP_CHKSUM_BIT BIT(17)
3205 +#define TSS_MTU_ENABLE_BIT BIT(16)
3206 +
3207 +#define TSS_CHECKUM_ENABLE \
3208 + (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \
3209 + TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT)
3210 +
3211 +/*
3212 + * GMAC DMA Tx Description Word 2 Register
3213 + * GMAC0 offset 0x8048
3214 + * GMAC1 offset 0xC048
3215 + */
3216 +typedef union {
3217 + unsigned int bits32;
3218 + unsigned int buf_adr;
3219 +} GMAC_TXDESC_2_T;
3220 +
3221 +/*
3222 + * GMAC DMA Tx Description Word 3 Register
3223 + * GMAC0 offset 0x804C
3224 + * GMAC1 offset 0xC04C
3225 + */
3226 +typedef union {
3227 + unsigned int bits32;
3228 + struct txdesc_word3 {
3229 + unsigned int mtu_size : 13; /* bit 12: 0 Tx Frame Byte Count */
3230 + unsigned int reserved : 16; /* bit 28:13 */
3231 + unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
3232 + unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
3233 + } bits;
3234 +} GMAC_TXDESC_3_T;
3235 +#define SOF_EOF_BIT_MASK 0x3fffffff
3236 +#define SOF_BIT 0x80000000
3237 +#define EOF_BIT 0x40000000
3238 +#define EOFIE_BIT BIT(29)
3239 +#define MTU_SIZE_BIT_MASK 0x1fff
3240 +
3241 +/*
3242 + * GMAC Tx Descriptor
3243 + */
3244 +typedef struct {
3245 + GMAC_TXDESC_0_T word0;
3246 + GMAC_TXDESC_1_T word1;
3247 + GMAC_TXDESC_2_T word2;
3248 + GMAC_TXDESC_3_T word3;
3249 +} GMAC_TXDESC_T;
3250 +
3251 +/*
3252 + * GMAC DMA Rx First Description Address Register
3253 + * GMAC0 offset 0x8058
3254 + * GMAC1 offset 0xC058
3255 + */
3256 +typedef union {
3257 + unsigned int bits32;
3258 + struct bit_8058 {
3259 + unsigned int reserved : 3; /* bit 2:0 */
3260 + unsigned int rd_busy : 1; /* bit 3 1-RxDMA busy; 0-RxDMA idle */
3261 + unsigned int rd_first_des_ptr : 28; /* bit 31:4 first descriptor address */
3262 + } bits;
3263 +} GMAC_RXDMA_FIRST_DESC_T;
3264 +
3265 +/*
3266 + * GMAC DMA Rx Current Description Address Register
3267 + * GMAC0 offset 0x805C
3268 + * GMAC1 offset 0xC05C
3269 + */
3270 +typedef union {
3271 + unsigned int bits32;
3272 + struct bit_805C {
3273 + unsigned int reserved : 4; /* bit 3:0 */
3274 + unsigned int rd_curr_des_ptr : 28; /* bit 31:4 current descriptor address */
3275 + } bits;
3276 +} GMAC_RXDMA_CURR_DESC_T;
3277 +
3278 +/*
3279 + * GMAC DMA Rx Description Word 0 Register
3280 + * GMAC0 offset 0x8060
3281 + * GMAC1 offset 0xC060
3282 + */
3283 +typedef union {
3284 + unsigned int bits32;
3285 + struct bit_8060 {
3286 + unsigned int buffer_size : 16; /* bit 15:0 number of descriptors used for the current frame */
3287 + unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
3288 + unsigned int status : 4; /* bit 24:22 Status of rx frame */
3289 + unsigned int chksum_status : 3; /* bit 28:26 Check Sum Status */
3290 + unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
3291 + unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
3292 + unsigned int drop : 1; /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
3293 + } bits;
3294 +} GMAC_RXDESC_0_T;
3295 +
3296 +#define GMAC_RXDESC_0_T_derr BIT(30)
3297 +#define GMAC_RXDESC_0_T_perr BIT(29)
3298 +#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
3299 +#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
3300 +#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
3301 +
3302 +#define RX_CHKSUM_IP_UDP_TCP_OK 0
3303 +#define RX_CHKSUM_IP_OK_ONLY 1
3304 +#define RX_CHKSUM_NONE 2
3305 +#define RX_CHKSUM_IP_ERR_UNKNOWN 4
3306 +#define RX_CHKSUM_IP_ERR 5
3307 +#define RX_CHKSUM_TCP_UDP_ERR 6
3308 +#define RX_CHKSUM_NUM 8
3309 +
3310 +#define RX_STATUS_GOOD_FRAME 0
3311 +#define RX_STATUS_TOO_LONG_GOOD_CRC 1
3312 +#define RX_STATUS_RUNT_FRAME 2
3313 +#define RX_STATUS_SFD_NOT_FOUND 3
3314 +#define RX_STATUS_CRC_ERROR 4
3315 +#define RX_STATUS_TOO_LONG_BAD_CRC 5
3316 +#define RX_STATUS_ALIGNMENT_ERROR 6
3317 +#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
3318 +#define RX_STATUS_RX_ERR 8
3319 +#define RX_STATUS_DA_FILTERED 9
3320 +#define RX_STATUS_BUFFER_FULL 10
3321 +#define RX_STATUS_NUM 16
3322 +
3323 +#define RX_ERROR_LENGTH(s) \
3324 + ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
3325 + (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
3326 + (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
3327 +#define RX_ERROR_OVER(s) \
3328 + ((s) == RX_STATUS_BUFFER_FULL)
3329 +#define RX_ERROR_CRC(s) \
3330 + ((s) == RX_STATUS_CRC_ERROR || \
3331 + (s) == RX_STATUS_TOO_LONG_BAD_CRC)
3332 +#define RX_ERROR_FRAME(s) \
3333 + ((s) == RX_STATUS_ALIGNMENT_ERROR || \
3334 + (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
3335 +#define RX_ERROR_FIFO(s) \
3336 + (0)
3337 +
3338 +/*
3339 + * GMAC DMA Rx Description Word 1 Register
3340 + * GMAC0 offset 0x8064
3341 + * GMAC1 offset 0xC064
3342 + */
3343 +typedef union {
3344 + unsigned int bits32;
3345 + struct rxdesc_word1 {
3346 + unsigned int byte_count : 16; /* bit 15: 0 Rx Frame Byte Count */
3347 + unsigned int sw_id : 16; /* bit 31:16 Software ID */
3348 + } bits;
3349 +} GMAC_RXDESC_1_T;
3350 +
3351 +/*
3352 + * GMAC DMA Rx Description Word 2 Register
3353 + * GMAC0 offset 0x8068
3354 + * GMAC1 offset 0xC068
3355 + */
3356 +typedef union {
3357 + unsigned int bits32;
3358 + unsigned int buf_adr;
3359 +} GMAC_RXDESC_2_T;
3360 +
3361 +#define RX_INSERT_NONE 0
3362 +#define RX_INSERT_1_BYTE 1
3363 +#define RX_INSERT_2_BYTE 2
3364 +#define RX_INSERT_3_BYTE 3
3365 +
3366 +/*
3367 + * GMAC DMA Rx Description Word 3 Register
3368 + * GMAC0 offset 0x806C
3369 + * GMAC1 offset 0xC06C
3370 + */
3371 +typedef union {
3372 + unsigned int bits32;
3373 + struct rxdesc_word3 {
3374 + unsigned int l3_offset : 8; /* bit 7: 0 L3 data offset */
3375 + unsigned int l4_offset : 8; /* bit 15: 8 L4 data offset */
3376 + unsigned int l7_offset : 8; /* bit 23: 16 L7 data offset */
3377 + unsigned int dup_ack : 1; /* bit 24 Duplicated ACK detected */
3378 + unsigned int abnormal : 1; /* bit 25 abnormal case found */
3379 + unsigned int option : 1; /* bit 26 IPV4 option or IPV6 extension header */
3380 + unsigned int out_of_seq : 1; /* bit 27 Out of Sequence packet */
3381 + unsigned int ctrl_flag : 1; /* bit 28 Control Flag is present */
3382 + unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
3383 + unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
3384 + } bits;
3385 +} GMAC_RXDESC_3_T;
3386 +
3387 +/*
3388 + * GMAC Rx Descriptor
3389 + */
3390 +typedef struct {
3391 + GMAC_RXDESC_0_T word0;
3392 + GMAC_RXDESC_1_T word1;
3393 + GMAC_RXDESC_2_T word2;
3394 + GMAC_RXDESC_3_T word3;
3395 +} GMAC_RXDESC_T;
3396 +
3397 +/*
3398 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
3399 + * GMAC0 offset 0x8070
3400 + * GMAC1 offset 0xC070
3401 + */
3402 +typedef union {
3403 + unsigned int bits32;
3404 + struct bit_8070 {
3405 + unsigned int mr0hel : 6; /* bit 5:0 match rule 0 hash entry size */
3406 + unsigned int mr0_action : 5; /* bit 10:6 Matching Rule 0 action offset */
3407 + unsigned int reserved0 : 4; /* bit 14:11 */
3408 + unsigned int mr0en : 1; /* bit 15 Enable Matching Rule 0 */
3409 + unsigned int mr1hel : 6; /* bit 21:16 match rule 1 hash entry size */
3410 + unsigned int mr1_action : 5; /* bit 26:22 Matching Rule 1 action offset */
3411 + unsigned int timing : 3; /* bit 29:27 */
3412 + unsigned int reserved1 : 1; /* bit 30 */
3413 + unsigned int mr1en : 1; /* bit 31 Enable Matching Rule 1 */
3414 + } bits;
3415 +} GMAC_HASH_ENABLE_REG0_T;
3416 +
3417 +/*
3418 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
3419 + * GMAC0 offset 0x8074
3420 + * GMAC1 offset 0xC074
3421 + */
3422 +typedef union {
3423 + unsigned int bits32;
3424 + struct bit_8074 {
3425 + unsigned int mr2hel : 6; /* bit 5:0 match rule 2 hash entry size */
3426 + unsigned int mr2_action : 5; /* bit 10:6 Matching Rule 2 action offset */
3427 + unsigned int reserved2 : 4; /* bit 14:11 */
3428 + unsigned int mr2en : 1; /* bit 15 Enable Matching Rule 2 */
3429 + unsigned int mr3hel : 6; /* bit 21:16 match rule 3 hash entry size */
3430 + unsigned int mr3_action : 5; /* bit 26:22 Matching Rule 3 action offset */
3431 + unsigned int reserved1 : 4; /* bit 30:27 */
3432 + unsigned int mr3en : 1; /* bit 31 Enable Matching Rule 3 */
3433 + } bits;
3434 +} GMAC_HASH_ENABLE_REG1_T;
3435 +
3436 +/*
3437 + * GMAC Matching Rule Control Register 0
3438 + * GMAC0 offset 0x8078
3439 + * GMAC1 offset 0xC078
3440 + */
3441 +typedef union {
3442 + unsigned int bits32;
3443 + struct bit_8078 {
3444 + unsigned int sprx : 8; /* bit 7:0 Support Protocol Register 7:0 */
3445 + unsigned int reserved2 : 4; /* bit 11:8 */
3446 + unsigned int tos_traffic : 1; /* bit 12 IPV4 TOS or IPV6 Traffice Class */
3447 + unsigned int flow_lable : 1; /* bit 13 IPV6 Flow label */
3448 + unsigned int ip_hdr_len : 1; /* bit 14 IPV4 Header length */
3449 + unsigned int ip_version : 1; /* bit 15 0: IPV4, 1: IPV6 */
3450 + unsigned int reserved1 : 3; /* bit 18:16 */
3451 + unsigned int pppoe : 1; /* bit 19 PPPoE Session ID enable */
3452 + unsigned int vlan : 1; /* bit 20 VLAN ID enable */
3453 + unsigned int ether_type : 1; /* bit 21 Ethernet type enable */
3454 + unsigned int sa : 1; /* bit 22 MAC SA enable */
3455 + unsigned int da : 1; /* bit 23 MAC DA enable */
3456 + unsigned int priority : 3; /* bit 26:24 priority if multi-rules matched */
3457 + unsigned int port : 1; /* bit 27 PORT ID matching enable */
3458 + unsigned int l7 : 1; /* bit 28 L7 matching enable */
3459 + unsigned int l4 : 1; /* bit 29 L4 matching enable */
3460 + unsigned int l3 : 1; /* bit 30 L3 matching enable */
3461 + unsigned int l2 : 1; /* bit 31 L2 matching enable */
3462 + } bits;
3463 +} GMAC_MRxCR0_T;
3464 +
3465 +#define MR_L2_BIT BIT(31)
3466 +#define MR_L3_BIT BIT(30)
3467 +#define MR_L4_BIT BIT(29)
3468 +#define MR_L7_BIT BIT(28)
3469 +#define MR_PORT_BIT BIT(27)
3470 +#define MR_PRIORITY_BIT BIT(26)
3471 +#define MR_DA_BIT BIT(23)
3472 +#define MR_SA_BIT BIT(22)
3473 +#define MR_ETHER_TYPE_BIT BIT(21)
3474 +#define MR_VLAN_BIT BIT(20)
3475 +#define MR_PPPOE_BIT BIT(19)
3476 +#define MR_IP_VER_BIT BIT(15)
3477 +#define MR_IP_HDR_LEN_BIT BIT(14)
3478 +#define MR_FLOW_LABLE_BIT BIT(13)
3479 +#define MR_TOS_TRAFFIC_BIT BIT(12)
3480 +#define MR_SPR_BIT(x) BIT(x)
3481 +#define MR_SPR_BITS 0xff
3482 +
3483 +/*
3484 + * GMAC Matching Rule Control Register 1
3485 + * GMAC0 offset 0x807C
3486 + * GMAC1 offset 0xC07C
3487 + */
3488 +typedef union {
3489 + unsigned int bits32;
3490 + struct bit_807C {
3491 + unsigned int l4_byte0_15 : 16; /* bit 15: 0 */
3492 + unsigned int dip_netmask : 7; /* bit 22:16 Dest IP net mask, number of mask bits */
3493 + unsigned int dip : 1; /* bit 23 Dest IP */
3494 + unsigned int sip_netmask : 7; /* bit 30:24 Srce IP net mask, number of mask bits */
3495 + unsigned int sip : 1; /* bit 31 Srce IP */
3496 + } bits;
3497 +} GMAC_MRxCR1_T;
3498 +
3499 +/*
3500 + * GMAC Matching Rule Control Register 2
3501 + * GMAC0 offset 0x8080
3502 + * GMAC1 offset 0xC080
3503 + */
3504 +typedef union {
3505 + unsigned int bits32;
3506 + struct bit_8080 {
3507 + unsigned int l7_byte0_23 : 24; /* bit 23:0 */
3508 + unsigned int l4_byte16_24 : 8; /* bit 31: 24 */
3509 + } bits;
3510 +} GMAC_MRxCR2_T;
3511 +
3512 +/*
3513 + * GMAC Support registers
3514 + * GMAC0 offset 0x80A8
3515 + * GMAC1 offset 0xC0A8
3516 + */
3517 +typedef union {
3518 + unsigned int bits32;
3519 + struct bit_80A8 {
3520 + unsigned int protocol : 8; /* bit 7:0 Supported protocol */
3521 + unsigned int swap : 3; /* bit 10:8 Swap */
3522 + unsigned int reserved : 21; /* bit 31:11 */
3523 + } bits;
3524 +} GMAC_SPR_T;
3525 +
3526 +/*
3527 + * GMAC_AHB_WEIGHT registers
3528 + * GMAC0 offset 0x80C8
3529 + * GMAC1 offset 0xC0C8
3530 + */
3531 +typedef union {
3532 + unsigned int bits32;
3533 + struct bit_80C8 {
3534 + unsigned int hash_weight : 5; /* 4:0 */
3535 + unsigned int rx_weight : 5; /* 9:5 */
3536 + unsigned int tx_weight : 5; /* 14:10 */
3537 + unsigned int pre_req : 5; /* 19:15 Rx Data Pre Request FIFO Threshold */
3538 + unsigned int tqDV_threshold : 5; /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
3539 + unsigned int reserved : 7; /* 31:25 */
3540 + } bits;
3541 +} GMAC_AHB_WEIGHT_T;
3542 +
3543 +/*
3544 + * the register structure of GMAC
3545 + */
3546 +
3547 +/*
3548 + * GMAC RX FLTR
3549 + * GMAC0 Offset 0xA00C
3550 + * GMAC1 Offset 0xE00C
3551 + */
3552 +typedef union {
3553 + unsigned int bits32;
3554 + struct bit1_000c {
3555 + unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
3556 + unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
3557 + unsigned int broadcast : 1; /* enable receive of broadcast frames */
3558 + unsigned int promiscuous : 1; /* enable receive of all frames */
3559 + unsigned int error : 1; /* enable receive of all error frames */
3560 + unsigned int : 27;
3561 + } bits;
3562 +} GMAC_RX_FLTR_T;
3563 +
3564 +/*
3565 + * GMAC Configuration 0
3566 + * GMAC0 Offset 0xA018
3567 + * GMAC1 Offset 0xE018
3568 + */
3569 +typedef union {
3570 + unsigned int bits32;
3571 + struct bit1_0018 {
3572 + unsigned int dis_tx : 1; /* 0: disable transmit */
3573 + unsigned int dis_rx : 1; /* 1: disable receive */
3574 + unsigned int loop_back : 1; /* 2: transmit data loopback enable */
3575 + unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
3576 + unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
3577 + unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
3578 + unsigned int dis_bkoff : 1; /* 11: disable back-off function */
3579 + unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
3580 + unsigned int sim_test : 1; /* 13: speed up timers in simulation */
3581 + unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
3582 + unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
3583 + unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
3584 + unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
3585 + unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
3586 + unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
3587 + unsigned int rgmm_edge : 1; /* 20 */
3588 + unsigned int rxc_inv : 1; /* 21 */
3589 + unsigned int ipv6_exthdr_order : 1; /* 22 */
3590 + unsigned int rx_err_detect : 1; /* 23 */
3591 + unsigned int port0_chk_hwq : 1; /* 24 */
3592 + unsigned int port1_chk_hwq : 1; /* 25 */
3593 + unsigned int port0_chk_toeq : 1; /* 26 */
3594 + unsigned int port1_chk_toeq : 1; /* 27 */
3595 + unsigned int port0_chk_classq : 1; /* 28 */
3596 + unsigned int port1_chk_classq : 1; /* 29 */
3597 + unsigned int reserved : 2; /* 31 */
3598 + } bits;
3599 +} GMAC_CONFIG0_T;
3600 +
3601 +#define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0))
3602 +#define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17))
3603 +#define CONFIG0_FLOW_RX (BIT(14))
3604 +#define CONFIG0_FLOW_TX (BIT(15))
3605 +#define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15))
3606 +#define CONFIG0_FLOW_CTL (BIT(14)|BIT(15))
3607 +
3608 +#define CONFIG0_MAXLEN_SHIFT 8
3609 +#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
3610 +#define CONFIG0_MAXLEN_1536 0
3611 +#define CONFIG0_MAXLEN_1518 1
3612 +#define CONFIG0_MAXLEN_1522 2
3613 +#define CONFIG0_MAXLEN_1542 3
3614 +#define CONFIG0_MAXLEN_9k 4 /* 9212 */
3615 +#define CONFIG0_MAXLEN_10k 5 /* 10236 */
3616 +#define CONFIG0_MAXLEN_1518__6 6
3617 +#define CONFIG0_MAXLEN_1518__7 7
3618 +
3619 +/*
3620 + * GMAC Configuration 1
3621 + * GMAC0 Offset 0xA01C
3622 + * GMAC1 Offset 0xE01C
3623 + */
3624 +typedef union {
3625 + unsigned int bits32;
3626 + struct bit1_001c {
3627 + unsigned int set_threshold : 8; /* flow control set threshold */
3628 + unsigned int rel_threshold : 8; /* flow control release threshold */
3629 + unsigned int reserved : 16;
3630 + } bits;
3631 +} GMAC_CONFIG1_T;
3632 +
3633 +#define GMAC_FLOWCTRL_SET_MAX 32
3634 +#define GMAC_FLOWCTRL_SET_MIN 0
3635 +#define GMAC_FLOWCTRL_RELEASE_MAX 32
3636 +#define GMAC_FLOWCTRL_RELEASE_MIN 0
3637 +
3638 +/*
3639 + * GMAC Configuration 2
3640 + * GMAC0 Offset 0xA020
3641 + * GMAC1 Offset 0xE020
3642 + */
3643 +typedef union {
3644 + unsigned int bits32;
3645 + struct bit1_0020 {
3646 + unsigned int set_threshold : 16; /* flow control set threshold */
3647 + unsigned int rel_threshold : 16; /* flow control release threshold */
3648 + } bits;
3649 +} GMAC_CONFIG2_T;
3650 +
3651 +/*
3652 + * GMAC Configuration 3
3653 + * GMAC0 Offset 0xA024
3654 + * GMAC1 Offset 0xE024
3655 + */
3656 +typedef union {
3657 + unsigned int bits32;
3658 + struct bit1_0024 {
3659 + unsigned int set_threshold : 16; /* flow control set threshold */
3660 + unsigned int rel_threshold : 16; /* flow control release threshold */
3661 + } bits;
3662 +} GMAC_CONFIG3_T;
3663 +
3664 +
3665 +/*
3666 + * GMAC STATUS
3667 + * GMAC0 Offset 0xA02C
3668 + * GMAC1 Offset 0xE02C
3669 + */
3670 +typedef union {
3671 + unsigned int bits32;
3672 + struct bit1_002c {
3673 + unsigned int link : 1; /* link status */
3674 + unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
3675 + unsigned int duplex : 1; /* duplex mode */
3676 + unsigned int reserved : 1;
3677 + unsigned int mii_rmii : 2; /* PHY interface type */
3678 + unsigned int : 25;
3679 + } bits;
3680 +} GMAC_STATUS_T;
3681 +
3682 +#define GMAC_SPEED_10 0
3683 +#define GMAC_SPEED_100 1
3684 +#define GMAC_SPEED_1000 2
3685 +
3686 +#define GMAC_PHY_MII 0
3687 +#define GMAC_PHY_GMII 1
3688 +#define GMAC_PHY_RGMII_100_10 2
3689 +#define GMAC_PHY_RGMII_1000 3
3690 +
3691 +/*
3692 + * Queue Header
3693 + * (1) TOE Queue Header
3694 + * (2) Non-TOE Queue Header
3695 + * (3) Interrupt Queue Header
3696 + *
3697 + * memory Layout
3698 + * TOE Queue Header
3699 + * 0x60003000 +---------------------------+ 0x0000
3700 + * | TOE Queue 0 Header |
3701 + * | 8 * 4 Bytes |
3702 + * +---------------------------+ 0x0020
3703 + * | TOE Queue 1 Header |
3704 + * | 8 * 4 Bytes |
3705 + * +---------------------------+ 0x0040
3706 + * | ...... |
3707 + * | |
3708 + * +---------------------------+
3709 + *
3710 + * Non TOE Queue Header
3711 + * 0x60002000 +---------------------------+ 0x0000
3712 + * | Default Queue 0 Header |
3713 + * | 2 * 4 Bytes |
3714 + * +---------------------------+ 0x0008
3715 + * | Default Queue 1 Header |
3716 + * | 2 * 4 Bytes |
3717 + * +---------------------------+ 0x0010
3718 + * | Classification Queue 0 |
3719 + * | 2 * 4 Bytes |
3720 + * +---------------------------+
3721 + * | Classification Queue 1 |
3722 + * | 2 * 4 Bytes |
3723 + * +---------------------------+ (n * 8 + 0x10)
3724 + * | ... |
3725 + * | 2 * 4 Bytes |
3726 + * +---------------------------+ (13 * 8 + 0x10)
3727 + * | Classification Queue 13 |
3728 + * | 2 * 4 Bytes |
3729 + * +---------------------------+ 0x80
3730 + * | Interrupt Queue 0 |
3731 + * | 2 * 4 Bytes |
3732 + * +---------------------------+
3733 + * | Interrupt Queue 1 |
3734 + * | 2 * 4 Bytes |
3735 + * +---------------------------+
3736 + * | Interrupt Queue 2 |
3737 + * | 2 * 4 Bytes |
3738 + * +---------------------------+
3739 + * | Interrupt Queue 3 |
3740 + * | 2 * 4 Bytes |
3741 + * +---------------------------+
3742 + *
3743 + */
3744 +#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
3745 +#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
3746 +#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
3747 +#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
3748 +#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
3749 +#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
3750 +#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
3751 +/*
3752 + * TOE Queue Header Word 0
3753 + */
3754 +typedef union {
3755 + unsigned int bits32;
3756 + unsigned int base_size;
3757 +} TOE_QHDR0_T;
3758 +
3759 +#define TOE_QHDR0_BASE_MASK (~0x0f)
3760 +
3761 +/*
3762 + * TOE Queue Header Word 1
3763 + */
3764 +typedef union {
3765 + unsigned int bits32;
3766 + struct bit_qhdr1 {
3767 + unsigned int rptr : 16; /* bit 15:0 */
3768 + unsigned int wptr : 16; /* bit 31:16 */
3769 + } bits;
3770 +} TOE_QHDR1_T;
3771 +
3772 +/*
3773 + * TOE Queue Header Word 2
3774 + */
3775 +typedef union {
3776 + unsigned int bits32;
3777 + struct bit_qhdr2 {
3778 + unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
3779 + unsigned int reserved : 7; /* bit 23:17 */
3780 + unsigned int dack : 1; /* bit 24 1: Duplicated ACK */
3781 + unsigned int abn : 1; /* bit 25 1: Abnormal case Found */
3782 + unsigned int tcp_opt : 1; /* bit 26 1: Have TCP option */
3783 + unsigned int ip_opt : 1; /* bit 27 1: have IPV4 option or IPV6 Extension header */
3784 + unsigned int sat : 1; /* bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
3785 + unsigned int osq : 1; /* bit 29 1: out of sequence */
3786 + unsigned int ctl : 1; /* bit 30 1: have control flag bits (except ack) */
3787 + unsigned int usd : 1; /* bit 31 0: if no data assembled yet */
3788 + } bits;
3789 +} TOE_QHDR2_T;
3790 +
3791 +/*
3792 + * TOE Queue Header Word 3
3793 + */
3794 +typedef union {
3795 + unsigned int bits32;
3796 + unsigned int seq_num;
3797 +} TOE_QHDR3_T;
3798 +
3799 +/*
3800 + * TOE Queue Header Word 4
3801 + */
3802 +typedef union {
3803 + unsigned int bits32;
3804 + unsigned int ack_num;
3805 +} TOE_QHDR4_T;
3806 +
3807 +/*
3808 + * TOE Queue Header Word 5
3809 + */
3810 +typedef union {
3811 + unsigned int bits32;
3812 + struct bit_qhdr5 {
3813 + unsigned int AckCnt : 16; /* bit 15:0 */
3814 + unsigned int SeqCnt : 16; /* bit 31:16 */
3815 + } bits;
3816 +} TOE_QHDR5_T;
3817 +
3818 +/*
3819 + * TOE Queue Header Word 6
3820 + */
3821 +typedef union {
3822 + unsigned int bits32;
3823 + struct bit_qhdr6 {
3824 + unsigned int WinSize : 16; /* bit 15:0 */
3825 + unsigned int iq_num : 2; /* bit 17:16 */
3826 + unsigned int MaxPktSize : 14; /* bit 31:18 */
3827 + } bits;
3828 +} TOE_QHDR6_T;
3829 +
3830 +/*
3831 + * TOE Queue Header Word 7
3832 + */
3833 +typedef union {
3834 + unsigned int bits32;
3835 + struct bit_qhdr7 {
3836 + unsigned int AckThreshold : 16; /* bit 15:0 */
3837 + unsigned int SeqThreshold : 16; /* bit 31:16 */
3838 + } bits;
3839 +} TOE_QHDR7_T;
3840 +
3841 +/*
3842 + * TOE Queue Header
3843 + */
3844 +typedef struct {
3845 + TOE_QHDR0_T word0;
3846 + TOE_QHDR1_T word1;
3847 + TOE_QHDR2_T word2;
3848 + TOE_QHDR3_T word3;
3849 + TOE_QHDR4_T word4;
3850 + TOE_QHDR5_T word5;
3851 + TOE_QHDR6_T word6;
3852 + TOE_QHDR7_T word7;
3853 +} TOE_QHDR_T;
3854 +
3855 +/*
3856 + * NONTOE Queue Header Word 0
3857 + */
3858 +typedef union {
3859 + unsigned int bits32;
3860 + unsigned int base_size;
3861 +} NONTOE_QHDR0_T;
3862 +
3863 +#define NONTOE_QHDR0_BASE_MASK (~0x0f)
3864 +
3865 +/*
3866 + * NONTOE Queue Header Word 1
3867 + */
3868 +typedef union {
3869 + unsigned int bits32;
3870 + struct bit_nonqhdr1 {
3871 + unsigned int rptr : 16; /* bit 15:0 */
3872 + unsigned int wptr : 16; /* bit 31:16 */
3873 + } bits;
3874 +} NONTOE_QHDR1_T;
3875 +
3876 +/*
3877 + * Non-TOE Queue Header
3878 + */
3879 +typedef struct {
3880 + NONTOE_QHDR0_T word0;
3881 + NONTOE_QHDR1_T word1;
3882 +} NONTOE_QHDR_T;
3883 +
3884 +/*
3885 + * Interrupt Queue Header Word 0
3886 + */
3887 +typedef union {
3888 + unsigned int bits32;
3889 + struct bit_intrqhdr0 {
3890 + unsigned int win_size : 16; /* bit 15:0 Descriptor Ring Size */
3891 + unsigned int wptr : 16; /* bit 31:16 Write Pointer where hw stopped */
3892 + } bits;
3893 +} INTR_QHDR0_T;
3894 +
3895 +/*
3896 + * Interrupt Queue Header Word 1
3897 + */
3898 +typedef union {
3899 + unsigned int bits32;
3900 + struct bit_intrqhdr1 {
3901 + unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
3902 + unsigned int tcp_qid : 8; /* bit 24:17 TCP Queue ID */
3903 + unsigned int dack : 1; /* bit 25 1: Duplicated ACK */
3904 + unsigned int abn : 1; /* bit 26 1: Abnormal case Found */
3905 + unsigned int tcp_opt : 1; /* bit 27 1: Have TCP option */
3906 + unsigned int ip_opt : 1; /* bit 28 1: have IPV4 option or IPV6 Extension header */
3907 + unsigned int sat : 1; /* bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
3908 + unsigned int osq : 1; /* bit 30 1: out of sequence */
3909 + unsigned int ctl : 1; /* bit 31 1: have control flag bits (except ack) */
3910 + } bits;
3911 +} INTR_QHDR1_T;
3912 +
3913 +/*
3914 + * Interrupt Queue Header Word 2
3915 + */
3916 +typedef union {
3917 + unsigned int bits32;
3918 + unsigned int seq_num;
3919 +} INTR_QHDR2_T;
3920 +
3921 +/*
3922 + * Interrupt Queue Header Word 3
3923 + */
3924 +typedef union {
3925 + unsigned int bits32;
3926 + unsigned int ack_num;
3927 +} INTR_QHDR3_T;
3928 +
3929 +/*
3930 + * Interrupt Queue Header Word 4
3931 + */
3932 +typedef union {
3933 + unsigned int bits32;
3934 + struct bit_intrqhdr4 {
3935 + unsigned int AckCnt : 16; /* bit 15:0 Ack# change since last ack# intr. */
3936 + unsigned int SeqCnt : 16; /* bit 31:16 Seq# change since last seq# intr. */
3937 + } bits;
3938 +} INTR_QHDR4_T;
3939 +
3940 +/*
3941 + * Interrupt Queue Header
3942 + */
3943 +typedef struct {
3944 + INTR_QHDR0_T word0;
3945 + INTR_QHDR1_T word1;
3946 + INTR_QHDR2_T word2;
3947 + INTR_QHDR3_T word3;
3948 + INTR_QHDR4_T word4;
3949 + unsigned int word5;
3950 + unsigned int word6;
3951 + unsigned int word7;
3952 +} INTR_QHDR_T;
3953 +
3954 +#endif /* _GMAC_SL351x_H */
OpenWrt Source Repository