target/linux/gemini/patches-4.19/0008-ARM-dts-Enable-Gemini-flash-access.patch

   1 From 74631102645df8984acbdf67b731e4d437f27fed Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Thu, 11 Oct 2018 20:06:23 +0200
   4 Subject: [PATCH 08/18] ARM: dts: Enable Gemini flash access
   5
   6 Some Gemini platforms have a parallel NOR flash which conflicts
   7 with use cases reusing some of the flash lines (such as CE1)
   8 for GPIO.
   9
  10 Fix this on the D-Link DIR-685 and Itian SQ201 by creating
  11 "enabled" and "disabled" states for the flash pin control
  12 handle, and rely on the flash handling code to switch this
  13 in and out when accessed so these lines can be used
  14 for GPIO when flash is not accessed, and enable flash
  15 access.
  16
  17 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  18 ---
  19  arch/arm/boot/dts/gemini-dlink-dir-685.dts | 35 +++++++++++++++-------
  20  arch/arm/boot/dts/gemini-sq201.dts         | 31 ++++++++++---------
  21  2 files changed, 41 insertions(+), 25 deletions(-)
  22
  23 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
  24 +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
  25 @@ -64,7 +64,6 @@
  26                 gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  27                 gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  28                 gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  29 -               /* Collides with pflash CE1, not so cool */
  30                 cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
  31                 num-chipselects = <1>;
  32
  33 @@ -253,15 +252,18 @@
  34         soc {
  35                 flash@30000000 {
  36                         /*
  37 -                        * Flash access is by default disabled, because it
  38 -                        * collides with the Chip Enable signal for the display
  39 -                        * panel, that reuse the parallel flash Chip Select 1
  40 -                        * (CS1). Enabling flash makes graphics stop working.
  41 -                        *
  42 -                        * We might be able to hack around this by letting
  43 -                        * GPIO poke around in the flash controller registers.
  44 +                        * Flash access collides with the Chip Enable signal for
  45 +                        * the display panel, that reuse the parallel flash Chip
  46 +                        * Select 1 (CS1). We switch the pin control state so we
  47 +                        * enable these pins for flash access only when we need
  48 +                        * then, and when disabled they can be used for GPIO which
  49 +                        * is what the display panel needs.
  50                          */
  51 -                       /* status = "okay"; */
  52 +                       status = "okay";
  53 +                       pinctrl-names = "enabled", "disabled";
  54 +                       pinctrl-0 = <&pflash_default_pins>;
  55 +                       pinctrl-1 = <&pflash_disabled_pins>;
  56 +
  57                         /* 32MB of flash */
  58                         reg = <0x30000000 0x02000000>;
  59
  60 @@ -327,7 +329,6 @@
  61                                                 "gpio0cgrp",
  62                                                 "gpio0egrp",
  63                                                 "gpio0fgrp",
  64 -                                               "gpio0ggrp",
  65                                                 "gpio0hgrp";
  66                                         };
  67                                 };
  68 @@ -342,6 +343,18 @@
  69                                                 groups = "gpio1bgrp";
  70                                         };
  71                                 };
  72 +                               /*
  73 +                                * These GPIO groups will be mapped in over some
  74 +                                * of the flash pins when the flash is not in
  75 +                                * active use.
  76 +                                */
  77 +                               pflash_disabled_pins: pinctrl-pflash-disabled {
  78 +                                       mux {
  79 +                                               function = "gpio0";
  80 +                                               groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
  81 +                                                        "gpio0kgrp";
  82 +                                       };
  83 +                               };
  84                                 pinctrl-gmii {
  85                                         mux {
  86                                                 function = "gmii";
  87 @@ -430,7 +443,7 @@
  88                 };
  89
  90                 display-controller@6a000000 {
  91 -                       status = "okay";
  92 +                       status = "disabled";
  93
  94                         port@0 {
  95                                 reg = <0>;
  96 --- a/arch/arm/boot/dts/gemini-sq201.dts
  97 +++ b/arch/arm/boot/dts/gemini-sq201.dts
  98 @@ -41,14 +41,12 @@
  99                 compatible = "gpio-leds";
 100                 led-green-info {
 101                         label = "sq201:green:info";
 102 -                       /* Conflict with parallel flash */
 103                         gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
 104                         default-state = "on";
 105                         linux,default-trigger = "heartbeat";
 106                 };
 107                 led-green-usb {
 108                         label = "sq201:green:usb";
 109 -                       /* Conflict with parallel and NAND flash */
 110                         gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
 111                         default-state = "off";
 112                         linux,default-trigger = "usb-host";
 113 @@ -126,15 +124,10 @@
 114
 115         soc {
 116                 flash@30000000 {
 117 -                       /*
 118 -                        * Flash access can be enabled, with the side effect
 119 -                        * of disabling access to GPIO LED on GPIO0[20] which
 120 -                        * reuse one of the parallel flash chip select lines.
 121 -                        * Also the default firmware on the machine has the
 122 -                        * problem that since it uses the flash, the two LEDS
 123 -                        * on the right become numb.
 124 -                        */
 125 -                       /* status = "okay"; */
 126 +                       status = "okay";
 127 +                       pinctrl-names = "enabled", "disabled";
 128 +                       pinctrl-0 = <&pflash_default_pins>;
 129 +                       pinctrl-1 = <&pflash_disabled_pins>;
 130                         /* 16MB of flash */
 131                         reg = <0x30000000 0x01000000>;
 132
 133 @@ -184,9 +177,7 @@
 134                                         mux {
 135                                                 function = "gpio0";
 136                                                 groups = "gpio0fgrp",
 137 -                                               "gpio0ggrp",
 138 -                                               "gpio0hgrp",
 139 -                                               "gpio0kgrp";
 140 +                                               "gpio0hgrp";
 141                                         };
 142                                 };
 143                                 /*
 144 @@ -199,6 +190,18 @@
 145                                                 groups = "gpio1dgrp";
 146                                         };
 147                                 };
 148 +                               /*
 149 +                                * These GPIO groups will be mapped in over some
 150 +                                * of the flash pins when the flash is not in
 151 +                                * active use.
 152 +                                */
 153 +                               pflash_disabled_pins: pinctrl-pflash-disabled {
 154 +                                       mux {
 155 +                                               function = "gpio0";
 156 +                                               groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
 157 +                                                        "gpio0kgrp";
 158 +                                       };
 159 +                               };
 160                                 pinctrl-gmii {
 161                                         mux {
 162                                                 function = "gmii";