target/linux/generic-2.4/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c

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  50         specific prior written permission.
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  56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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  60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62
  63 *******************************************************************************/
  64
  65 /*******************************************************************************
  66 * mvEthDebug.c - Source file for user friendly debug functions
  67 *
  68 * DESCRIPTION:
  69 *
  70 * DEPENDENCIES:
  71 *       None.
  72 *
  73 *******************************************************************************/
  74
  75 #include "mvOs.h"
  76 #include "mvCommon.h"
  77 #include "mvTypes.h"
  78 #include "mv802_3.h"
  79 #include "mvDebug.h"
  80 #include "ctrlEnv/mvCtrlEnvLib.h"
  81 #include "eth-phy/mvEthPhy.h"
  82 #include "eth/mvEth.h"
  83 #include "eth/gbe/mvEthDebug.h"
  84
  85 /* #define mvOsPrintf printf */
  86
  87 void    mvEthPortShow(void* pHndl);
  88 void    mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode);
  89
  90 /******************************************************************************/
  91 /*                          Debug functions                                   */
  92 /******************************************************************************/
  93 void    ethRxCoal(int port, int usec)
  94 {
  95     void*   pHndl;
  96
  97     pHndl = mvEthPortHndlGet(port);
  98     if(pHndl != NULL)
  99     {
 100         mvEthRxCoalSet(pHndl, usec);
 101     }
 102 }
 103
 104 void    ethTxCoal(int port, int usec)
 105 {
 106     void*   pHndl;
 107
 108     pHndl = mvEthPortHndlGet(port);
 109     if(pHndl != NULL)
 110     {
 111         mvEthTxCoalSet(pHndl, usec);
 112     }
 113 }
 114
 115 #if (MV_ETH_VERSION >= 4)
 116 void     ethEjpModeSet(int port, int mode)
 117 {
 118     void*   pHndl;
 119
 120     pHndl = mvEthPortHndlGet(port);
 121     if(pHndl != NULL)
 122     {
 123         mvEthEjpModeSet(pHndl, mode);
 124     }
 125 }
 126 #endif /* (MV_ETH_VERSION >= 4) */
 127
 128 void    ethBpduRxQ(int port, int bpduQueue)
 129 {
 130     void*   pHndl;
 131
 132     pHndl = mvEthPortHndlGet(port);
 133     if(pHndl != NULL)
 134     {
 135         mvEthBpduRxQueue(pHndl, bpduQueue);
 136     }
 137 }
 138
 139 void    ethArpRxQ(int port, int arpQueue)
 140 {
 141     void*   pHndl;
 142
 143     pHndl = mvEthPortHndlGet(port);
 144     if(pHndl != NULL)
 145     {
 146         mvEthArpRxQueue(pHndl, arpQueue);
 147     }
 148 }
 149
 150 void    ethTcpRxQ(int port, int tcpQueue)
 151 {
 152     void*   pHndl;
 153
 154     pHndl = mvEthPortHndlGet(port);
 155     if(pHndl != NULL)
 156     {
 157         mvEthTcpRxQueue(pHndl, tcpQueue);
 158     }
 159 }
 160
 161 void    ethUdpRxQ(int port, int udpQueue)
 162 {
 163     void*   pHndl;
 164
 165     pHndl = mvEthPortHndlGet(port);
 166     if(pHndl != NULL)
 167     {
 168         mvEthUdpRxQueue(pHndl, udpQueue);
 169     }
 170 }
 171
 172 void    ethTxPolicyRegs(int port)
 173 {
 174     int             queue;
 175     ETH_PORT_CTRL*  pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port);
 176
 177     if(pPortCtrl == NULL)
 178     {
 179         return;
 180     }
 181     mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ",
 182                 port, pPortCtrl->portConfig.ejpMode);
 183     for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
 184     {
 185         if(pPortCtrl->txQueueConfig[queue].descrNum > 0)
 186             mvOsPrintf("%d, ", queue);
 187     }
 188     mvOsPrintf("\n");
 189
 190     mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port);
 191
 192     mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG            : 0x%X = 0x%08x\n",
 193                 ETH_TX_QUEUE_COMMAND_REG(port),
 194                 MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
 195
 196     mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG           : 0x%X = 0x%08x\n",
 197                 ETH_TX_FIXED_PRIO_CFG_REG(port),
 198                 MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) );
 199
 200     mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG           : 0x%X = 0x%08x\n",
 201                 ETH_TX_TOKEN_RATE_CFG_REG(port),
 202                 MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) );
 203
 204     mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG           : 0x%X = 0x%08x\n",
 205                 ETH_MAX_TRANSMIT_UNIT_REG(port),
 206                 MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) );
 207
 208     mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG        : 0x%X = 0x%08x\n",
 209                 ETH_TX_TOKEN_BUCKET_SIZE_REG(port),
 210                 MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) );
 211
 212     mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG       : 0x%X = 0x%08x\n",
 213                 ETH_TX_TOKEN_BUCKET_COUNT_REG(port),
 214                 MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) );
 215
 216     for(queue=0; queue<MV_ETH_MAX_TXQ; queue++)
 217     {
 218         mvOsPrintf("\n\t TX policy Port #%d, Queue #%d configuration registers\n", port, queue);
 219
 220         mvOsPrintf("ETH_TXQ_TOKEN_COUNT_REG             : 0x%X = 0x%08x\n",
 221                 ETH_TXQ_TOKEN_COUNT_REG(port, queue),
 222                 MV_REG_READ( ETH_TXQ_TOKEN_COUNT_REG(port, queue) ) );
 223
 224         mvOsPrintf("ETH_TXQ_TOKEN_CFG_REG               : 0x%X = 0x%08x\n",
 225                 ETH_TXQ_TOKEN_CFG_REG(port, queue),
 226                 MV_REG_READ( ETH_TXQ_TOKEN_CFG_REG(port, queue) ) );
 227
 228         mvOsPrintf("ETH_TXQ_ARBITER_CFG_REG             : 0x%X = 0x%08x\n",
 229                 ETH_TXQ_ARBITER_CFG_REG(port, queue),
 230                 MV_REG_READ( ETH_TXQ_ARBITER_CFG_REG(port, queue) ) );
 231     }
 232     mvOsPrintf("\n");
 233 }
 234
 235 /* Print important registers of Ethernet port */
 236 void    ethPortRegs(int port)
 237 {
 238     mvOsPrintf("\n\t ethGiga #%d port Registers:\n", port);
 239
 240     mvOsPrintf("ETH_PORT_STATUS_REG                 : 0x%X = 0x%08x\n",
 241                 ETH_PORT_STATUS_REG(port),
 242                 MV_REG_READ( ETH_PORT_STATUS_REG(port) ) );
 243
 244     mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG            : 0x%X = 0x%08x\n",
 245                 ETH_PORT_SERIAL_CTRL_REG(port),
 246                 MV_REG_READ( ETH_PORT_SERIAL_CTRL_REG(port) ) );
 247
 248     mvOsPrintf("ETH_PORT_CONFIG_REG                 : 0x%X = 0x%08x\n",
 249                 ETH_PORT_CONFIG_REG(port),
 250                 MV_REG_READ( ETH_PORT_CONFIG_REG(port) ) );
 251
 252     mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG          : 0x%X = 0x%08x\n",
 253                 ETH_PORT_CONFIG_EXTEND_REG(port),
 254                 MV_REG_READ( ETH_PORT_CONFIG_EXTEND_REG(port) ) );
 255
 256     mvOsPrintf("ETH_SDMA_CONFIG_REG                 : 0x%X = 0x%08x\n",
 257                 ETH_SDMA_CONFIG_REG(port),
 258                 MV_REG_READ( ETH_SDMA_CONFIG_REG(port) ) );
 259
 260     mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG       : 0x%X = 0x%08x\n",
 261                 ETH_TX_FIFO_URGENT_THRESH_REG(port),
 262                 MV_REG_READ( ETH_TX_FIFO_URGENT_THRESH_REG(port) ) );
 263
 264     mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG            : 0x%X = 0x%08x\n",
 265                 ETH_RX_QUEUE_COMMAND_REG(port),
 266                 MV_REG_READ( ETH_RX_QUEUE_COMMAND_REG(port) ) );
 267
 268     mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG            : 0x%X = 0x%08x\n",
 269                 ETH_TX_QUEUE_COMMAND_REG(port),
 270                 MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
 271
 272     mvOsPrintf("ETH_INTR_CAUSE_REG                  : 0x%X = 0x%08x\n",
 273                 ETH_INTR_CAUSE_REG(port),
 274                 MV_REG_READ( ETH_INTR_CAUSE_REG(port) ) );
 275
 276     mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG           : 0x%X = 0x%08x\n",
 277                 ETH_INTR_CAUSE_EXT_REG(port),
 278                 MV_REG_READ( ETH_INTR_CAUSE_EXT_REG(port) ) );
 279
 280     mvOsPrintf("ETH_INTR_MASK_REG                   : 0x%X = 0x%08x\n",
 281                 ETH_INTR_MASK_REG(port),
 282                 MV_REG_READ( ETH_INTR_MASK_REG(port) ) );
 283
 284     mvOsPrintf("ETH_INTR_EXTEND_MASK_REG            : 0x%X = 0x%08x\n",
 285                 ETH_INTR_MASK_EXT_REG(port),
 286                 MV_REG_READ( ETH_INTR_MASK_EXT_REG(port) ) );
 287
 288     mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG           : 0x%X = 0x%08x\n",
 289                 ETH_RX_DESCR_STAT_CMD_REG(port, 0),
 290                 MV_REG_READ( ETH_RX_DESCR_STAT_CMD_REG(port, 0) ) );
 291
 292     mvOsPrintf("ETH_RX_BYTE_COUNT_REG               : 0x%X = 0x%08x\n",
 293                 ETH_RX_BYTE_COUNT_REG(port, 0),
 294                 MV_REG_READ( ETH_RX_BYTE_COUNT_REG(port, 0) ) );
 295
 296     mvOsPrintf("ETH_RX_BUF_PTR_REG                  : 0x%X = 0x%08x\n",
 297                 ETH_RX_BUF_PTR_REG(port, 0),
 298                 MV_REG_READ( ETH_RX_BUF_PTR_REG(port, 0) ) );
 299
 300     mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG             : 0x%X = 0x%08x\n",
 301                 ETH_RX_CUR_DESC_PTR_REG(port, 0),
 302                 MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, 0) ) );
 303 }
 304
 305
 306 /* Print Giga Ethernet UNIT registers */
 307 void    ethRegs(int port)
 308 {
 309     mvOsPrintf("ETH_PHY_ADDR_REG               : 0x%X = 0x%08x\n",
 310                 ETH_PHY_ADDR_REG(port),
 311                 MV_REG_READ(ETH_PHY_ADDR_REG(port)) );
 312
 313     mvOsPrintf("ETH_UNIT_INTR_CAUSE_REG        : 0x%X = 0x%08x\n",
 314                 ETH_UNIT_INTR_CAUSE_REG(port),
 315                 MV_REG_READ( ETH_UNIT_INTR_CAUSE_REG(port)) );
 316
 317     mvOsPrintf("ETH_UNIT_INTR_MASK_REG         : 0x%X = 0x%08x\n",
 318                 ETH_UNIT_INTR_MASK_REG(port),
 319                 MV_REG_READ( ETH_UNIT_INTR_MASK_REG(port)) );
 320
 321     mvOsPrintf("ETH_UNIT_ERROR_ADDR_REG        : 0x%X = 0x%08x\n",
 322                 ETH_UNIT_ERROR_ADDR_REG(port),
 323                 MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(port)) );
 324
 325     mvOsPrintf("ETH_UNIT_INT_ADDR_ERROR_REG    : 0x%X = 0x%08x\n",
 326                 ETH_UNIT_INT_ADDR_ERROR_REG(port),
 327                 MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(port)) );
 328
 329 }
 330
 331 /******************************************************************************/
 332 /*                      MIB Counters functions                                */
 333 /******************************************************************************/
 334
 335 /*******************************************************************************
 336 * ethClearMibCounters - Clear all MIB counters
 337 *
 338 * DESCRIPTION:
 339 *       This function clears all MIB counters of a specific ethernet port.
 340 *       A read from the MIB counter will reset the counter.
 341 *
 342 * INPUT:
 343 *       int    port -  Ethernet Port number.
 344 *
 345 * RETURN: None
 346 *
 347 *******************************************************************************/
 348 void ethClearCounters(int port)
 349 {
 350     void*   pHndl;
 351
 352     pHndl = mvEthPortHndlGet(port);
 353     if(pHndl != NULL)
 354         mvEthMibCountersClear(pHndl);
 355
 356     return;
 357 }
 358
 359
 360 /* Print counters of the Ethernet port */
 361 void    ethPortCounters(int port)
 362 {
 363     MV_U32  regValue, regValHigh;
 364     void*   pHndl;
 365
 366     pHndl = mvEthPortHndlGet(port);
 367     if(pHndl == NULL)
 368         return;
 369
 370     mvOsPrintf("\n\t Port #%d MIB Counters\n\n", port);
 371
 372     mvOsPrintf("GoodFramesReceived          = %u\n",
 373               mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_RECEIVED, NULL));
 374     mvOsPrintf("BadFramesReceived           = %u\n",
 375               mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FRAMES_RECEIVED, NULL));
 376     mvOsPrintf("BroadcastFramesReceived     = %u\n",
 377               mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_RECEIVED, NULL));
 378     mvOsPrintf("MulticastFramesReceived     = %u\n",
 379               mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_RECEIVED, NULL));
 380
 381     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW,
 382                                  &regValHigh);
 383     mvOsPrintf("GoodOctetsReceived          = 0x%08x%08x\n",
 384                regValHigh, regValue);
 385
 386     mvOsPrintf("\n");
 387     mvOsPrintf("GoodFramesSent              = %u\n",
 388               mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_SENT, NULL));
 389     mvOsPrintf("BroadcastFramesSent         = %u\n",
 390               mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_SENT, NULL));
 391     mvOsPrintf("MulticastFramesSent         = %u\n",
 392               mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_SENT, NULL));
 393
 394     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_SENT_LOW,
 395                                  &regValHigh);
 396     mvOsPrintf("GoodOctetsSent              = 0x%08x%08x\n", regValHigh, regValue);
 397
 398
 399     mvOsPrintf("\n\t FC Control Counters\n");
 400
 401     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED, NULL);
 402     mvOsPrintf("UnrecogMacControlReceived   = %u\n", regValue);
 403
 404     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FC_RECEIVED, NULL);
 405     mvOsPrintf("GoodFCFramesReceived        = %u\n", regValue);
 406
 407     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FC_RECEIVED, NULL);
 408     mvOsPrintf("BadFCFramesReceived         = %u\n", regValue);
 409
 410     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FC_SENT, NULL);
 411     mvOsPrintf("FCFramesSent                = %u\n", regValue);
 412
 413
 414     mvOsPrintf("\n\t RX Errors\n");
 415
 416     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_OCTETS_RECEIVED, NULL);
 417     mvOsPrintf("BadOctetsReceived           = %u\n", regValue);
 418
 419     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNDERSIZE_RECEIVED, NULL);
 420     mvOsPrintf("UndersizeFramesReceived     = %u\n", regValue);
 421
 422     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FRAGMENTS_RECEIVED, NULL);
 423     mvOsPrintf("FragmentsReceived           = %u\n", regValue);
 424
 425     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_OVERSIZE_RECEIVED, NULL);
 426     mvOsPrintf("OversizeFramesReceived      = %u\n", regValue);
 427
 428     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_JABBER_RECEIVED, NULL);
 429     mvOsPrintf("JabbersReceived             = %u\n", regValue);
 430
 431     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_MAC_RECEIVE_ERROR, NULL);
 432     mvOsPrintf("MacReceiveErrors            = %u\n", regValue);
 433
 434     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_CRC_EVENT, NULL);
 435     mvOsPrintf("BadCrcReceived              = %u\n", regValue);
 436
 437     mvOsPrintf("\n\t TX Errors\n");
 438
 439     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR, NULL);
 440     mvOsPrintf("TxMacErrors                 = %u\n", regValue);
 441
 442     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_EXCESSIVE_COLLISION, NULL);
 443     mvOsPrintf("TxExcessiveCollisions       = %u\n", regValue);
 444
 445     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_COLLISION, NULL);
 446     mvOsPrintf("TxCollisions                = %u\n", regValue);
 447
 448     regValue = mvEthMibCounterRead(pHndl, ETH_MIB_LATE_COLLISION, NULL);
 449     mvOsPrintf("TxLateCollisions            = %u\n", regValue);
 450
 451
 452     mvOsPrintf("\n");
 453     regValue = MV_REG_READ( ETH_RX_DISCARD_PKTS_CNTR_REG(port));
 454     mvOsPrintf("Rx Discard packets counter  = %u\n", regValue);
 455
 456     regValue = MV_REG_READ(ETH_RX_OVERRUN_PKTS_CNTR_REG(port));
 457     mvOsPrintf("Rx Overrun packets counter  = %u\n", regValue);
 458 }
 459
 460 /* Print RMON counters of the Ethernet port */
 461 void    ethPortRmonCounters(int port)
 462 {
 463     void*   pHndl;
 464
 465     pHndl = mvEthPortHndlGet(port);
 466     if(pHndl == NULL)
 467         return;
 468
 469     mvOsPrintf("\n\t Port #%d RMON MIB Counters\n\n", port);
 470
 471     mvOsPrintf("64 ByteFramesReceived           = %u\n",
 472               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_64_OCTETS, NULL));
 473     mvOsPrintf("65...127 ByteFramesReceived     = %u\n",
 474               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_65_TO_127_OCTETS, NULL));
 475     mvOsPrintf("128...255 ByteFramesReceived    = %u\n",
 476               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_128_TO_255_OCTETS, NULL));
 477     mvOsPrintf("256...511 ByteFramesReceived    = %u\n",
 478               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_256_TO_511_OCTETS, NULL));
 479     mvOsPrintf("512...1023 ByteFramesReceived   = %u\n",
 480               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_512_TO_1023_OCTETS, NULL));
 481     mvOsPrintf("1024...Max ByteFramesReceived   = %u\n",
 482               mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_1024_TO_MAX_OCTETS, NULL));
 483 }
 484
 485 /* Print port information */
 486 void    ethPortStatus(int port)
 487 {
 488     void*   pHndl;
 489
 490     pHndl = mvEthPortHndlGet(port);
 491     if(pHndl != NULL)
 492     {
 493         mvEthPortShow(pHndl);
 494     }
 495 }
 496
 497 /* Print port queues information */
 498 void    ethPortQueues(int port, int rxQueue, int txQueue, int mode)
 499 {
 500     void*   pHndl;
 501
 502     pHndl = mvEthPortHndlGet(port);
 503     if(pHndl != NULL)
 504     {
 505         mvEthQueuesShow(pHndl, rxQueue, txQueue, mode);
 506     }
 507 }
 508
 509 void    ethUcastSet(int port, char* macStr, int queue)
 510 {
 511     void*   pHndl;
 512     MV_U8   macAddr[MV_MAC_ADDR_SIZE];
 513
 514     pHndl = mvEthPortHndlGet(port);
 515     if(pHndl != NULL)
 516     {
 517         mvMacStrToHex(macStr, macAddr);
 518         mvEthMacAddrSet(pHndl, macAddr, queue);
 519     }
 520 }
 521
 522
 523 void    ethPortUcastShow(int port)
 524 {
 525     MV_U32  unicastReg, macL, macH;
 526     int     i, j;
 527
 528     macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(port));
 529     macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(port));
 530
 531     mvOsPrintf("\n\t Port #%d Unicast MAC table: %02x:%02x:%02x:%02x:%02x:%02x\n\n",
 532                 port, ((macH >> 24) & 0xff), ((macH >> 16) & 0xff),
 533                       ((macH >> 8) & 0xff), (macH  & 0xff),
 534                       ((macL >> 8) & 0xff), (macL  & 0xff) );
 535
 536     for (i=0; i<4; i++)
 537     {
 538         unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4));
 539         for(j=0; j<4; j++)
 540         {
 541             MV_U8   macEntry = (unicastReg >> (8*j)) & 0xFF;
 542
 543             mvOsPrintf("%X: %8s, Q = %d\n", i*4+j,
 544                 (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7);
 545         }
 546     }
 547 }
 548
 549 void    ethMcastAdd(int port, char* macStr, int queue)
 550 {
 551     void*   pHndl;
 552     MV_U8   macAddr[MV_MAC_ADDR_SIZE];
 553
 554     pHndl = mvEthPortHndlGet(port);
 555     if(pHndl != NULL)
 556     {
 557         mvMacStrToHex(macStr, macAddr);
 558         mvEthMcastAddrSet(pHndl, macAddr, queue);
 559     }
 560 }
 561
 562 void    ethPortMcast(int port)
 563 {
 564     int     tblIdx, regIdx;
 565     MV_U32  regVal;
 566
 567     mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n",
 568                 port);
 569
 570     for(tblIdx=0; tblIdx<(256/4); tblIdx++)
 571     {
 572         regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4));
 573         for(regIdx=0; regIdx<4; regIdx++)
 574         {
 575             if((regVal & (0x01 << (regIdx*8))) != 0)
 576             {
 577                 mvOsPrintf("0x%02X: Accepted, rxQ = %d\n",
 578                     tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07));
 579             }
 580         }
 581     }
 582     mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port);
 583     for(tblIdx=0; tblIdx<(256/4); tblIdx++)
 584     {
 585         regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4));
 586         for(regIdx=0; regIdx<4; regIdx++)
 587         {
 588             if((regVal & (0x01 << (regIdx*8))) != 0)
 589             {
 590                 mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n",
 591                     tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07));
 592             }
 593         }
 594     }
 595 }
 596
 597
 598 /* Print status of Ethernet port */
 599 void    mvEthPortShow(void* pHndl)
 600 {
 601     MV_U32              regValue, rxCoal, txCoal;
 602     int                 speed, queue, port;
 603     ETH_PORT_CTRL*      pPortCtrl = (ETH_PORT_CTRL*)pHndl;
 604
 605     port = pPortCtrl->portNo;
 606
 607     regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) );
 608
 609     mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n",
 610                 port, ETH_PORT_STATUS_REG(port), regValue);
 611
 612     mvOsPrintf("descInSram=%d, descSwCoher=%d\n",
 613                 ethDescInSram, ethDescSwCoher);
 614
 615     if(regValue & ETH_GMII_SPEED_1000_MASK)
 616         speed = 1000;
 617     else if(regValue & ETH_MII_SPEED_100_MASK)
 618         speed = 100;
 619     else
 620         speed = 10;
 621
 622     mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal);
 623
 624     /* Link, Speed, Duplex, FlowControl */
 625     mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s",
 626                 (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN",
 627                 speed,
 628                 (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF",
 629                 (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE");
 630
 631     mvOsPrintf("\n");
 632
 633     mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n",
 634                 rxCoal, txCoal);
 635
 636     mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n",
 637                 pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ,
 638                 pPortCtrl->portConfig.rxBpduQ,
 639                 pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ);
 640
 641     /* Print all RX and TX queues */
 642     for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
 643     {
 644         mvOsPrintf("RX Queue #%d: base=0x%lx, free=%d\n",
 645                     queue, (MV_ULONG)pPortCtrl->rxQueue[queue].pFirstDescr,
 646                     mvEthRxResourceGet(pPortCtrl, queue) );
 647     }
 648     mvOsPrintf("\n");
 649     for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
 650     {
 651         mvOsPrintf("TX Queue #%d: base=0x%lx, free=%d\n",
 652                 queue, (MV_ULONG)pPortCtrl->txQueue[queue].pFirstDescr,
 653                 mvEthTxResourceGet(pPortCtrl, queue) );
 654     }
 655 }
 656
 657 /* Print RX and TX queue of the Ethernet port */
 658 void    mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode)
 659 {
 660     ETH_PORT_CTRL   *pPortCtrl = (ETH_PORT_CTRL*)pHndl;
 661     ETH_QUEUE_CTRL  *pQueueCtrl;
 662     MV_U32          regValue;
 663     ETH_RX_DESC     *pRxDescr;
 664     ETH_TX_DESC     *pTxDescr;
 665     int             i, port = pPortCtrl->portNo;
 666
 667     if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) )
 668     {
 669         pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]);
 670         mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue);
 671
 672         mvOsPrintf("CURR_RX_DESC_PTR        : 0x%X = 0x%08x\n",
 673             ETH_RX_CUR_DESC_PTR_REG(port, rxQueue),
 674             MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue)));
 675
 676
 677         if(pQueueCtrl->pFirstDescr != NULL)
 678         {
 679             mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
 680                 (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr,
 681                 pQueueCtrl->resource);
 682             mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
 683                 (MV_ULONG)pQueueCtrl->pCurrentDescr,
 684                 (MV_ULONG)pQueueCtrl->pUsedDescr);
 685
 686             if(mode == 1)
 687             {
 688                 pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr;
 689                 i = 0;
 690                 do
 691                 {
 692                     mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n",
 693                                 i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr),
 694                                 pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize,
 695                                 (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo,
 696                                 ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo);
 697
 698                     ETH_DESCR_INV(pPortCtrl, pRxDescr);
 699                     pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl);
 700                     i++;
 701                 } while (pRxDescr != pQueueCtrl->pFirstDescr);
 702             }
 703         }
 704         else
 705             mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue);
 706     }
 707
 708     if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) )
 709     {
 710         pQueueCtrl = &(pPortCtrl->txQueue[txQueue]);
 711         mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue);
 712
 713         regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue));
 714         mvOsPrintf("CURR_TX_DESC_PTR        : 0x%X = 0x%08x\n",
 715                     ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue);
 716
 717         if(pQueueCtrl->pFirstDescr != NULL)
 718         {
 719             mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
 720                        (MV_ULONG)pQueueCtrl->pFirstDescr,
 721                        (MV_ULONG)pQueueCtrl->pLastDescr,
 722                         pQueueCtrl->resource);
 723             mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
 724                        (MV_ULONG)pQueueCtrl->pCurrentDescr,
 725                        (MV_ULONG)pQueueCtrl->pUsedDescr);
 726
 727             if(mode == 1)
 728             {
 729                 pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr;
 730                 i = 0;
 731                 do
 732                 {
 733                     mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n",
 734                                 i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr),
 735                                 pTxDescr->cmdSts, pTxDescr->byteCnt,
 736                                 (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo,
 737                                 pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0);
 738
 739                     ETH_DESCR_INV(pPortCtrl, pTxDescr);
 740                     pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl);
 741                     i++;
 742                 } while (pTxDescr != pQueueCtrl->pFirstDescr);
 743             }
 744         }
 745         else
 746             mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue);
 747     }
 748 }