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[openwrt/openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
73 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
74 #define RTL8366S_MIB_CTRL_REG 0x11F0
75 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
76 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
77 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
78
79 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
80 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
81 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
82
83
84 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
85 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
86 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
87 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
88 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
89
90
91 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
92 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93
94 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95
96 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
97 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
98 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99
100 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
101
102
103 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
104 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
105 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
106 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
107 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
108 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
109 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
110
111
112 #define RTL8366_PORT_NUM_CPU 5
113 #define RTL8366_NUM_PORTS 6
114 #define RTL8366_NUM_VLANS 16
115 #define RTL8366_NUM_LEDGROUPS 4
116 #define RTL8366_NUM_VIDS 4096
117 #define RTL8366S_PRIORITYMAX 7
118 #define RTL8366S_FIDMAX 7
119
120
121 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
122 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
123 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
124 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125
126 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
127 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128
129 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
130 RTL8366_PORT_2 | \
131 RTL8366_PORT_3 | \
132 RTL8366_PORT_4 | \
133 RTL8366_PORT_UNKNOWN | \
134 RTL8366_PORT_CPU)
135
136 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
137 RTL8366_PORT_2 | \
138 RTL8366_PORT_3 | \
139 RTL8366_PORT_4 | \
140 RTL8366_PORT_UNKNOWN)
141
142 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
143 RTL8366_PORT_2 | \
144 RTL8366_PORT_3 | \
145 RTL8366_PORT_4)
146
147 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
148 RTL8366_PORT_CPU)
149
150 struct rtl8366s {
151 struct device *parent;
152 struct rtl8366_smi smi;
153 struct switch_dev dev;
154 char buf[4096];
155 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
156 struct dentry *debugfs_root;
157 #endif
158 };
159
160 struct rtl8366s_vlan_mc {
161 u16 reserved2:1;
162 u16 priority:3;
163 u16 vid:12;
164
165 u16 reserved1:1;
166 u16 fid:3;
167 u16 untag:6;
168 u16 member:6;
169 };
170
171 struct rtl8366s_vlan_4k {
172 u16 reserved1:4;
173 u16 vid:12;
174
175 u16 reserved2:1;
176 u16 fid:3;
177 u16 untag:6;
178 u16 member:6;
179 };
180
181 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
182 u16 g_dbg_reg;
183 #endif
184
185 struct mib_counter {
186 unsigned base;
187 unsigned offset;
188 unsigned length;
189 const char *name;
190 };
191
192 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 0, 4, "IfInOctets" },
194 { 0, 4, 4, "EtherStatsOctets" },
195 { 0, 8, 2, "EtherStatsUnderSizePkts" },
196 { 0, 10, 2, "EtherFragments" },
197 { 0, 12, 2, "EtherStatsPkts64Octets" },
198 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
199 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
200 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
201 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
202 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
203 { 0, 24, 2, "EtherOversizeStats" },
204 { 0, 26, 2, "EtherStatsJabbers" },
205 { 0, 28, 2, "IfInUcastPkts" },
206 { 0, 30, 2, "EtherStatsMulticastPkts" },
207 { 0, 32, 2, "EtherStatsBroadcastPkts" },
208 { 0, 34, 2, "EtherStatsDropEvents" },
209 { 0, 36, 2, "Dot3StatsFCSErrors" },
210 { 0, 38, 2, "Dot3StatsSymbolErrors" },
211 { 0, 40, 2, "Dot3InPauseFrames" },
212 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
213 { 0, 44, 4, "IfOutOctets" },
214 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
215 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
216 { 0, 52, 2, "Dot3sDeferredTransmissions" },
217 { 0, 54, 2, "Dot3StatsLateCollisions" },
218 { 0, 56, 2, "EtherStatsCollisions" },
219 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
220 { 0, 60, 2, "Dot3OutPauseFrames" },
221 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
222
223 /*
224 * The following counters are accessible at a different
225 * base address.
226 */
227 { 1, 0, 2, "Dot1dTpPortInDiscards" },
228 { 1, 2, 2, "IfOutUcastPkts" },
229 { 1, 4, 2, "IfOutMulticastPkts" },
230 { 1, 6, 2, "IfOutBroadcastPkts" },
231 };
232
233 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
234 {
235 return container_of(smi, struct rtl8366s, smi);
236 }
237
238 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
239 {
240 return container_of(sw, struct rtl8366s, dev);
241 }
242
243 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
244 {
245 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
246 return &rtl->smi;
247 }
248
249 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
250 {
251 int timeout = 10;
252 u32 data;
253
254 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
255 RTL8366_CHIP_CTRL_RESET_HW);
256 do {
257 msleep(1);
258 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
259 return -EIO;
260
261 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
262 break;
263 } while (--timeout);
264
265 if (!timeout) {
266 printk("Timeout waiting for the switch to reset\n");
267 return -EIO;
268 }
269
270 return 0;
271 }
272
273 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
274 u32 phy_no, u32 page, u32 addr, u32 *data)
275 {
276 u32 reg;
277 int ret;
278
279 if (phy_no > RTL8366S_PHY_NO_MAX)
280 return -EINVAL;
281
282 if (page > RTL8366S_PHY_PAGE_MAX)
283 return -EINVAL;
284
285 if (addr > RTL8366S_PHY_ADDR_MAX)
286 return -EINVAL;
287
288 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
289 RTL8366S_PHY_CTRL_READ);
290 if (ret)
291 return ret;
292
293 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
294 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
295 (addr & RTL8366S_PHY_REG_MASK);
296
297 ret = rtl8366_smi_write_reg(smi, reg, 0);
298 if (ret)
299 return ret;
300
301 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
302 if (ret)
303 return ret;
304
305 return 0;
306 }
307
308 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
309 u32 phy_no, u32 page, u32 addr, u32 data)
310 {
311 u32 reg;
312 int ret;
313
314 if (phy_no > RTL8366S_PHY_NO_MAX)
315 return -EINVAL;
316
317 if (page > RTL8366S_PHY_PAGE_MAX)
318 return -EINVAL;
319
320 if (addr > RTL8366S_PHY_ADDR_MAX)
321 return -EINVAL;
322
323 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
324 RTL8366S_PHY_CTRL_WRITE);
325 if (ret)
326 return ret;
327
328 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
329 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
330 (addr & RTL8366S_PHY_REG_MASK);
331
332 ret = rtl8366_smi_write_reg(smi, reg, data);
333 if (ret)
334 return ret;
335
336 return 0;
337 }
338
339 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
340 int port, unsigned long long *val)
341 {
342 int i;
343 int err;
344 u32 addr, data;
345 u64 mibvalue;
346
347 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
348 return -EINVAL;
349
350 switch (rtl8366s_mib_counters[counter].base) {
351 case 0:
352 addr = RTL8366S_MIB_COUNTER_BASE +
353 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
354 break;
355
356 case 1:
357 addr = RTL8366S_MIB_COUNTER_BASE2 +
358 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
359 break;
360
361 default:
362 return -EINVAL;
363 }
364
365 addr += rtl8366s_mib_counters[counter].offset;
366
367 /*
368 * Writing access counter address first
369 * then ASIC will prepare 64bits counter wait for being retrived
370 */
371 data = 0; /* writing data will be discard by ASIC */
372 err = rtl8366_smi_write_reg(smi, addr, data);
373 if (err)
374 return err;
375
376 /* read MIB control register */
377 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
378 if (err)
379 return err;
380
381 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
382 return -EBUSY;
383
384 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
385 return -EIO;
386
387 mibvalue = 0;
388 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
389 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
390 if (err)
391 return err;
392
393 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
394 }
395
396 *val = mibvalue;
397 return 0;
398 }
399
400 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
401 struct rtl8366_vlan_4k *vlan4k)
402 {
403 struct rtl8366s_vlan_4k vlan4k_priv;
404 int err;
405 u32 data;
406 u16 *tableaddr;
407
408 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
409 vlan4k_priv.vid = vid;
410
411 if (vid >= RTL8366_NUM_VIDS)
412 return -EINVAL;
413
414 tableaddr = (u16 *)&vlan4k_priv;
415
416 /* write VID */
417 data = *tableaddr;
418 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
419 if (err)
420 return err;
421
422 /* write table access control word */
423 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
424 RTL8366S_TABLE_VLAN_READ_CTRL);
425 if (err)
426 return err;
427
428 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
429 if (err)
430 return err;
431
432 *tableaddr = data;
433 tableaddr++;
434
435 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
436 &data);
437 if (err)
438 return err;
439
440 *tableaddr = data;
441
442 vlan4k->vid = vid;
443 vlan4k->untag = vlan4k_priv.untag;
444 vlan4k->member = vlan4k_priv.member;
445 vlan4k->fid = vlan4k_priv.fid;
446
447 return 0;
448 }
449
450 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
451 const struct rtl8366_vlan_4k *vlan4k)
452 {
453 struct rtl8366s_vlan_4k vlan4k_priv;
454 int err;
455 u32 data;
456 u16 *tableaddr;
457
458 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
459 vlan4k->member > RTL8366_PORT_ALL ||
460 vlan4k->untag > RTL8366_PORT_ALL ||
461 vlan4k->fid > RTL8366S_FIDMAX)
462 return -EINVAL;
463
464 vlan4k_priv.vid = vlan4k->vid;
465 vlan4k_priv.untag = vlan4k->untag;
466 vlan4k_priv.member = vlan4k->member;
467 vlan4k_priv.fid = vlan4k->fid;
468
469 tableaddr = (u16 *)&vlan4k_priv;
470
471 data = *tableaddr;
472
473 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
474 if (err)
475 return err;
476
477 tableaddr++;
478
479 data = *tableaddr;
480
481 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
482 data);
483 if (err)
484 return err;
485
486 /* write table access control word */
487 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
488 RTL8366S_TABLE_VLAN_WRITE_CTRL);
489
490 return err;
491 }
492
493 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
494 struct rtl8366_vlan_mc *vlanmc)
495 {
496 struct rtl8366s_vlan_mc vlanmc_priv;
497 int err;
498 u32 addr;
499 u32 data;
500 u16 *tableaddr;
501
502 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
503
504 if (index >= RTL8366_NUM_VLANS)
505 return -EINVAL;
506
507 tableaddr = (u16 *)&vlanmc_priv;
508
509 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
510 err = rtl8366_smi_read_reg(smi, addr, &data);
511 if (err)
512 return err;
513
514 *tableaddr = data;
515 tableaddr++;
516
517 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
518 err = rtl8366_smi_read_reg(smi, addr, &data);
519 if (err)
520 return err;
521
522 *tableaddr = data;
523
524 vlanmc->vid = vlanmc_priv.vid;
525 vlanmc->priority = vlanmc_priv.priority;
526 vlanmc->untag = vlanmc_priv.untag;
527 vlanmc->member = vlanmc_priv.member;
528 vlanmc->fid = vlanmc_priv.fid;
529
530 return 0;
531 }
532
533 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
534 const struct rtl8366_vlan_mc *vlanmc)
535 {
536 struct rtl8366s_vlan_mc vlanmc_priv;
537 int err;
538 u32 addr;
539 u32 data;
540 u16 *tableaddr;
541
542 if (index >= RTL8366_NUM_VLANS ||
543 vlanmc->vid >= RTL8366_NUM_VIDS ||
544 vlanmc->priority > RTL8366S_PRIORITYMAX ||
545 vlanmc->member > RTL8366_PORT_ALL ||
546 vlanmc->untag > RTL8366_PORT_ALL ||
547 vlanmc->fid > RTL8366S_FIDMAX)
548 return -EINVAL;
549
550 vlanmc_priv.vid = vlanmc->vid;
551 vlanmc_priv.priority = vlanmc->priority;
552 vlanmc_priv.untag = vlanmc->untag;
553 vlanmc_priv.member = vlanmc->member;
554 vlanmc_priv.fid = vlanmc->fid;
555
556 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
557
558 tableaddr = (u16 *)&vlanmc_priv;
559 data = *tableaddr;
560
561 err = rtl8366_smi_write_reg(smi, addr, data);
562 if (err)
563 return err;
564
565 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
566
567 tableaddr++;
568 data = *tableaddr;
569
570 err = rtl8366_smi_write_reg(smi, addr, data);
571 if (err)
572 return err;
573
574 return 0;
575 }
576
577 static int rtl8366s_get_port_vlan_index(struct rtl8366_smi *smi, int port,
578 int *val)
579 {
580 u32 data;
581 int err;
582
583 if (port >= RTL8366_NUM_PORTS)
584 return -EINVAL;
585
586 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
587 &data);
588 if (err)
589 return err;
590
591 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
592 RTL8366S_PORT_VLAN_CTRL_MASK;
593
594 return 0;
595
596 }
597
598 static int rtl8366s_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
599 int *val)
600 {
601 struct rtl8366_vlan_mc vlanmc;
602 int err;
603 int index;
604
605 err = rtl8366s_get_port_vlan_index(smi, port, &index);
606 if (err)
607 return err;
608
609 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
610 if (err)
611 return err;
612
613 *val = vlanmc.vid;
614 return 0;
615 }
616
617 static int rtl8366s_set_port_vlan_index(struct rtl8366_smi *smi, int port,
618 int index)
619 {
620 u32 data;
621 int err;
622
623 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
624 return -EINVAL;
625
626 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
627 &data);
628 if (err)
629 return err;
630
631 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
632 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
633 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
634 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
635
636 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
637 data);
638 return err;
639 }
640
641 static int rtl8366s_set_vlan_port_pvid(struct rtl8366_smi *smi, int port, int val)
642 {
643 int i;
644 struct rtl8366_vlan_mc vlanmc;
645 struct rtl8366_vlan_4k vlan4k;
646
647 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
648 return -EINVAL;
649
650 /* Updating the 4K entry; lookup it and change the port member set */
651 rtl8366s_get_vlan_4k(smi, val, &vlan4k);
652 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
653 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
654 rtl8366s_set_vlan_4k(smi, &vlan4k);
655
656 /*
657 * For the 16 entries more work needs to be done. First see if such
658 * VID is already there and change it
659 */
660 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
661 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
662
663 /* Try to find an existing vid and update port member set */
664 if (val == vlanmc.vid) {
665 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
666 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
667
668 /* Now update PVID register settings */
669 rtl8366s_set_port_vlan_index(smi, port, i);
670
671 return 0;
672 }
673 }
674
675 /*
676 * PVID could not be found from vlan table. Replace unused (one that
677 * has no member ports) with new one
678 */
679 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
680 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
681
682 /*
683 * See if this vlan member configuration is unused. It is
684 * unused if member set contains no ports or CPU port only
685 */
686 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
687 vlanmc.vid = val;
688 vlanmc.priority = 0;
689 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
690 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
691 vlanmc.fid = 0;
692
693 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
694
695 /* Now update PVID register settings */
696 rtl8366s_set_port_vlan_index(smi, port, i);
697
698 return 0;
699 }
700 }
701
702 dev_err(smi->parent,
703 "All 16 vlan member configurations are in use\n");
704
705 return -EINVAL;
706 }
707
708
709 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
710 {
711 u32 data = 0;
712
713 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
714
715 if (enable)
716 data |= RTL8366_CHIP_CTRL_VLAN;
717 else
718 data &= ~RTL8366_CHIP_CTRL_VLAN;
719
720 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
721 }
722
723 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
724 {
725 u32 data = 0;
726
727 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
728
729 if (enable)
730 data |= 1;
731 else
732 data &= ~1;
733
734 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
735 }
736
737 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
738 {
739 struct rtl8366_vlan_4k vlan4k;
740 struct rtl8366_vlan_mc vlanmc;
741 int err;
742 int i;
743
744 /* clear 16 VLAN member configuration */
745 vlanmc.vid = 0;
746 vlanmc.priority = 0;
747 vlanmc.member = 0;
748 vlanmc.untag = 0;
749 vlanmc.fid = 0;
750 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
751 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
752 if (err)
753 return err;
754 }
755
756 /* Set a default VLAN with vid 1 to 4K table for all ports */
757 vlan4k.vid = 1;
758 vlan4k.member = RTL8366_PORT_ALL;
759 vlan4k.untag = RTL8366_PORT_ALL;
760 vlan4k.fid = 0;
761 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
762 if (err)
763 return err;
764
765 /* Set all ports PVID to default VLAN */
766 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
767 err = rtl8366s_set_vlan_port_pvid(smi, i, 0);
768 if (err)
769 return err;
770 }
771
772 return 0;
773 }
774
775 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
776 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
777 {
778 file->private_data = inode->i_private;
779 return 0;
780 }
781
782 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
783 char __user *user_buf,
784 size_t count, loff_t *ppos)
785 {
786 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
787 struct rtl8366_smi *smi = &rtl->smi;
788 int i, j, len = 0;
789 char *buf = rtl->buf;
790
791 len += snprintf(buf + len, sizeof(rtl->buf) - len,
792 "%-36s %12s %12s %12s %12s %12s %12s\n",
793 "Counter",
794 "Port 0", "Port 1", "Port 2",
795 "Port 3", "Port 4", "Port 5");
796
797 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
798 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
799 rtl8366s_mib_counters[i].name);
800 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
801 unsigned long long counter = 0;
802
803 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
804 len += snprintf(buf + len,
805 sizeof(rtl->buf) - len,
806 "%12llu ", counter);
807 else
808 len += snprintf(buf + len,
809 sizeof(rtl->buf) - len,
810 "%12s ", "error");
811 }
812 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
813 }
814
815 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
816 }
817
818 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
819 char __user *user_buf,
820 size_t count, loff_t *ppos)
821 {
822 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
823 struct rtl8366_smi *smi = &rtl->smi;
824 int i, j, len = 0;
825 char *buf = rtl->buf;
826
827 len += snprintf(buf + len, sizeof(rtl->buf) - len,
828 "VLAN Member Config:\n");
829 len += snprintf(buf + len, sizeof(rtl->buf) - len,
830 "\t id \t vid \t prio \t member \t untag \t fid "
831 "\tports\n");
832
833 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
834 struct rtl8366_vlan_mc vlanmc;
835
836 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
837
838 len += snprintf(buf + len, sizeof(rtl->buf) - len,
839 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
840 "\t", i, vlanmc.vid, vlanmc.priority,
841 vlanmc.member, vlanmc.untag, vlanmc.fid);
842
843 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
844 int index = 0;
845 if (!rtl8366s_get_port_vlan_index(smi, j, &index)) {
846 if (index == i)
847 len += snprintf(buf + len,
848 sizeof(rtl->buf) - len,
849 "%d", j);
850 }
851 }
852 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
853 }
854
855 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
856 }
857
858 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
859 char __user *user_buf,
860 size_t count, loff_t *ppos)
861 {
862 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
863 struct rtl8366_smi *smi = &rtl->smi;
864 u32 t, reg = g_dbg_reg;
865 int err, len = 0;
866 char *buf = rtl->buf;
867
868 memset(buf, '\0', sizeof(rtl->buf));
869
870 err = rtl8366_smi_read_reg(smi, reg, &t);
871 if (err) {
872 len += snprintf(buf, sizeof(rtl->buf),
873 "Read failed (reg: 0x%04x)\n", reg);
874 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
875 }
876
877 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
878 reg, t);
879
880 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
881 }
882
883 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
884 const char __user *user_buf,
885 size_t count, loff_t *ppos)
886 {
887 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
888 struct rtl8366_smi *smi = &rtl->smi;
889 unsigned long data;
890 u32 reg = g_dbg_reg;
891 int err;
892 size_t len;
893 char *buf = rtl->buf;
894
895 len = min(count, sizeof(rtl->buf) - 1);
896 if (copy_from_user(buf, user_buf, len)) {
897 dev_err(rtl->parent, "copy from user failed\n");
898 return -EFAULT;
899 }
900
901 buf[len] = '\0';
902 if (len > 0 && buf[len - 1] == '\n')
903 buf[len - 1] = '\0';
904
905
906 if (strict_strtoul(buf, 16, &data)) {
907 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
908 } else {
909 err = rtl8366_smi_write_reg(smi, reg, data);
910 if (err) {
911 dev_err(rtl->parent,
912 "writing reg 0x%04x val 0x%04lx failed\n",
913 reg, data);
914 }
915 }
916
917 return count;
918 }
919
920 static const struct file_operations fops_rtl8366s_regs = {
921 .read = rtl8366s_read_debugfs_reg,
922 .write = rtl8366s_write_debugfs_reg,
923 .open = rtl8366s_debugfs_open,
924 .owner = THIS_MODULE
925 };
926
927 static const struct file_operations fops_rtl8366s_vlan = {
928 .read = rtl8366s_read_debugfs_vlan,
929 .open = rtl8366s_debugfs_open,
930 .owner = THIS_MODULE
931 };
932
933 static const struct file_operations fops_rtl8366s_mibs = {
934 .read = rtl8366s_read_debugfs_mibs,
935 .open = rtl8366s_debugfs_open,
936 .owner = THIS_MODULE
937 };
938
939 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
940 {
941 struct dentry *node;
942 struct dentry *root;
943
944 if (!rtl->debugfs_root)
945 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
946
947 if (!rtl->debugfs_root) {
948 dev_err(rtl->parent, "Unable to create debugfs dir\n");
949 return;
950 }
951 root = rtl->debugfs_root;
952
953 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
954 if (!node) {
955 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
956 "reg");
957 return;
958 }
959
960 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
961 &fops_rtl8366s_regs);
962 if (!node) {
963 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
964 "val");
965 return;
966 }
967
968 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
969 &fops_rtl8366s_vlan);
970 if (!node) {
971 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
972 "vlan");
973 return;
974 }
975
976 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
977 &fops_rtl8366s_mibs);
978 if (!node) {
979 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
980 "mibs");
981 return;
982 }
983 }
984
985 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
986 {
987 if (rtl->debugfs_root) {
988 debugfs_remove_recursive(rtl->debugfs_root);
989 rtl->debugfs_root = NULL;
990 }
991 }
992
993 #else
994 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
995 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
996 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
997
998 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
999 const struct switch_attr *attr,
1000 struct switch_val *val)
1001 {
1002 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1003 u32 data = 0;
1004
1005 if (val->value.i == 1) {
1006 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1007 data |= (1 << 2);
1008 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1009 }
1010
1011 return 0;
1012 }
1013
1014 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1015 const struct switch_attr *attr,
1016 struct switch_val *val)
1017 {
1018 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1019 u32 data;
1020
1021 if (attr->ofs == 1) {
1022 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1023
1024 if (data & RTL8366_CHIP_CTRL_VLAN)
1025 val->value.i = 1;
1026 else
1027 val->value.i = 0;
1028 } else if (attr->ofs == 2) {
1029 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1030
1031 if (data & 0x0001)
1032 val->value.i = 1;
1033 else
1034 val->value.i = 0;
1035 }
1036
1037 return 0;
1038 }
1039
1040 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1041 const struct switch_attr *attr,
1042 struct switch_val *val)
1043 {
1044 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1045 u32 data;
1046
1047 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1048
1049 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1050
1051 return 0;
1052 }
1053
1054 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1055 const struct switch_attr *attr,
1056 struct switch_val *val)
1057 {
1058 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1059 u32 data;
1060
1061 if (val->value.i >= 6)
1062 return -EINVAL;
1063
1064 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1065
1066 data &= ~RTL8366_LED_BLINKRATE_MASK;
1067 data |= val->value.i;
1068
1069 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1070
1071 return 0;
1072 }
1073
1074 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1075 const struct switch_attr *attr,
1076 struct switch_val *val)
1077 {
1078 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1079
1080 if (attr->ofs == 1)
1081 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1082 else
1083 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1084 }
1085
1086 static const char *rtl8366s_speed_str(unsigned speed)
1087 {
1088 switch (speed) {
1089 case 0:
1090 return "10baseT";
1091 case 1:
1092 return "100baseT";
1093 case 2:
1094 return "1000baseT";
1095 }
1096
1097 return "unknown";
1098 }
1099
1100 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1101 const struct switch_attr *attr,
1102 struct switch_val *val)
1103 {
1104 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1105 struct rtl8366_smi *smi = &rtl->smi;
1106 u32 len = 0, data = 0;
1107
1108 if (val->port_vlan >= RTL8366_NUM_PORTS)
1109 return -EINVAL;
1110
1111 memset(rtl->buf, '\0', sizeof(rtl->buf));
1112 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1113 (val->port_vlan / 2), &data);
1114
1115 if (val->port_vlan % 2)
1116 data = data >> 8;
1117
1118 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1119 len = snprintf(rtl->buf, sizeof(rtl->buf),
1120 "port:%d link:up speed:%s %s-duplex %s%s%s",
1121 val->port_vlan,
1122 rtl8366s_speed_str(data &
1123 RTL8366S_PORT_STATUS_SPEED_MASK),
1124 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1125 "full" : "half",
1126 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1127 "tx-pause ": "",
1128 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1129 "rx-pause " : "",
1130 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1131 "nway ": "");
1132 } else {
1133 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1134 val->port_vlan);
1135 }
1136
1137 val->value.s = rtl->buf;
1138 val->len = len;
1139
1140 return 0;
1141 }
1142
1143 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1144 const struct switch_attr *attr,
1145 struct switch_val *val)
1146 {
1147 int i;
1148 u32 len = 0;
1149 struct rtl8366_vlan_mc vlanmc;
1150 struct rtl8366_vlan_4k vlan4k;
1151 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1152 struct rtl8366_smi *smi = &rtl->smi;
1153 char *buf = rtl->buf;
1154
1155 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1156 return -EINVAL;
1157
1158 memset(buf, '\0', sizeof(rtl->buf));
1159
1160 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1161 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1162
1163 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1164 val->port_vlan);
1165
1166 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1167 int index = 0;
1168 if (!rtl8366s_get_port_vlan_index(smi, i, &index) &&
1169 index == val->port_vlan)
1170 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1171 "%d", i);
1172 }
1173 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1174
1175 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1176 "\t\t vid \t prio \t member \t untag \t fid\n");
1177 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1178 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1179 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1180 vlanmc.vid, vlanmc.priority, vlanmc.member,
1181 vlanmc.untag, vlanmc.fid);
1182 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1183 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1184 "%d \t \t 0x%04x \t 0x%04x \t %d",
1185 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1186
1187 val->value.s = buf;
1188 val->len = len;
1189
1190 return 0;
1191 }
1192
1193 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1194 const struct switch_attr *attr,
1195 struct switch_val *val)
1196 {
1197 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1198 u32 data = 0;
1199
1200 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1201 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1202 return -EINVAL;
1203
1204 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1205 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1206 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1207 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1208 } else {
1209 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1210 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1211 (val->value.i << (val->port_vlan * 4));
1212 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1213 }
1214
1215 return 0;
1216 }
1217
1218 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1219 const struct switch_attr *attr,
1220 struct switch_val *val)
1221 {
1222 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1223 u32 data = 0;
1224
1225 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1226 return -EINVAL;
1227
1228 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1229 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1230
1231 return 0;
1232 }
1233
1234 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1235 const struct switch_attr *attr,
1236 struct switch_val *val)
1237 {
1238 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1239 u32 data = 0;
1240
1241 if (val->port_vlan >= RTL8366_NUM_PORTS)
1242 return -EINVAL;
1243
1244 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1245 data |= (1 << (val->port_vlan + 3));
1246 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1247
1248 return 0;
1249 }
1250
1251 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1252 const struct switch_attr *attr,
1253 struct switch_val *val)
1254 {
1255 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1256 struct rtl8366_smi *smi = &rtl->smi;
1257 int i, len = 0;
1258 unsigned long long counter = 0;
1259 char *buf = rtl->buf;
1260
1261 if (val->port_vlan >= RTL8366_NUM_PORTS)
1262 return -EINVAL;
1263
1264 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1265 "Port %d MIB counters\n",
1266 val->port_vlan);
1267
1268 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1269 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1270 "%-36s: ", rtl8366s_mib_counters[i].name);
1271 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1272 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1273 "%llu\n", counter);
1274 else
1275 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1276 "%s\n", "error");
1277 }
1278
1279 val->value.s = buf;
1280 val->len = len;
1281 return 0;
1282 }
1283
1284 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1285 struct switch_val *val)
1286 {
1287 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1288 struct rtl8366_vlan_mc vlanmc;
1289 struct switch_port *port;
1290 int i;
1291
1292 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1293 return -EINVAL;
1294
1295 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1296
1297 port = &val->value.ports[0];
1298 val->len = 0;
1299 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1300 if (!(vlanmc.member & BIT(i)))
1301 continue;
1302
1303 port->id = i;
1304 port->flags = (vlanmc.untag & BIT(i)) ?
1305 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1306 val->len++;
1307 port++;
1308 }
1309 return 0;
1310 }
1311
1312 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1313 struct switch_val *val)
1314 {
1315 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1316 struct rtl8366_vlan_mc vlanmc;
1317 struct rtl8366_vlan_4k vlan4k;
1318 struct switch_port *port;
1319 int i;
1320
1321 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1322 return -EINVAL;
1323
1324 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1325 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1326
1327 vlanmc.untag = 0;
1328 vlanmc.member = 0;
1329
1330 port = &val->value.ports[0];
1331 for (i = 0; i < val->len; i++, port++) {
1332 vlanmc.member |= BIT(port->id);
1333
1334 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1335 vlanmc.untag |= BIT(port->id);
1336 }
1337
1338 vlan4k.member = vlanmc.member;
1339 vlan4k.untag = vlanmc.untag;
1340
1341 rtl8366s_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1342 rtl8366s_set_vlan_4k(smi, &vlan4k);
1343 return 0;
1344 }
1345
1346 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1347 {
1348 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1349 return rtl8366s_get_vlan_port_pvid(smi, port, val);
1350 }
1351
1352 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1353 {
1354 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1355 return rtl8366s_set_vlan_port_pvid(smi, port, val);
1356 }
1357
1358 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1359 {
1360 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1361 int err;
1362
1363 err = rtl8366s_reset_chip(smi);
1364 if (err)
1365 return err;
1366
1367 return rtl8366s_reset_vlan(smi);
1368 }
1369
1370 static struct switch_attr rtl8366s_globals[] = {
1371 {
1372 .type = SWITCH_TYPE_INT,
1373 .name = "enable_vlan",
1374 .description = "Enable VLAN mode",
1375 .set = rtl8366s_sw_set_vlan_enable,
1376 .get = rtl8366s_sw_get_vlan_enable,
1377 .max = 1,
1378 .ofs = 1
1379 }, {
1380 .type = SWITCH_TYPE_INT,
1381 .name = "enable_vlan4k",
1382 .description = "Enable VLAN 4K mode",
1383 .set = rtl8366s_sw_set_vlan_enable,
1384 .get = rtl8366s_sw_get_vlan_enable,
1385 .max = 1,
1386 .ofs = 2
1387 }, {
1388 .type = SWITCH_TYPE_INT,
1389 .name = "reset_mibs",
1390 .description = "Reset all MIB counters",
1391 .set = rtl8366s_sw_reset_mibs,
1392 .get = NULL,
1393 .max = 1
1394 }, {
1395 .type = SWITCH_TYPE_INT,
1396 .name = "blinkrate",
1397 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1398 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1399 .set = rtl8366s_sw_set_blinkrate,
1400 .get = rtl8366s_sw_get_blinkrate,
1401 .max = 5
1402 },
1403 };
1404
1405 static struct switch_attr rtl8366s_port[] = {
1406 {
1407 .type = SWITCH_TYPE_STRING,
1408 .name = "link",
1409 .description = "Get port link information",
1410 .max = 1,
1411 .set = NULL,
1412 .get = rtl8366s_sw_get_port_link,
1413 }, {
1414 .type = SWITCH_TYPE_INT,
1415 .name = "reset_mib",
1416 .description = "Reset single port MIB counters",
1417 .max = 1,
1418 .set = rtl8366s_sw_reset_port_mibs,
1419 .get = NULL,
1420 }, {
1421 .type = SWITCH_TYPE_STRING,
1422 .name = "mib",
1423 .description = "Get MIB counters for port",
1424 .max = 33,
1425 .set = NULL,
1426 .get = rtl8366s_sw_get_port_mib,
1427 }, {
1428 .type = SWITCH_TYPE_INT,
1429 .name = "led",
1430 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1431 .max = 15,
1432 .set = rtl8366s_sw_set_port_led,
1433 .get = rtl8366s_sw_get_port_led,
1434 },
1435 };
1436
1437 static struct switch_attr rtl8366s_vlan[] = {
1438 {
1439 .type = SWITCH_TYPE_STRING,
1440 .name = "info",
1441 .description = "Get vlan information",
1442 .max = 1,
1443 .set = NULL,
1444 .get = rtl8366s_sw_get_vlan_info,
1445 },
1446 };
1447
1448 /* template */
1449 static struct switch_dev rtl8366_switch_dev = {
1450 .name = "RTL8366S",
1451 .cpu_port = RTL8366_PORT_NUM_CPU,
1452 .ports = RTL8366_NUM_PORTS,
1453 .vlans = RTL8366_NUM_VLANS,
1454 .attr_global = {
1455 .attr = rtl8366s_globals,
1456 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1457 },
1458 .attr_port = {
1459 .attr = rtl8366s_port,
1460 .n_attr = ARRAY_SIZE(rtl8366s_port),
1461 },
1462 .attr_vlan = {
1463 .attr = rtl8366s_vlan,
1464 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1465 },
1466
1467 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1468 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1469 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1470 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1471 .reset_switch = rtl8366s_sw_reset_switch,
1472 };
1473
1474 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1475 {
1476 struct switch_dev *dev = &rtl->dev;
1477 int err;
1478
1479 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1480 dev->priv = rtl;
1481 dev->devname = dev_name(rtl->parent);
1482
1483 err = register_switch(dev, NULL);
1484 if (err)
1485 dev_err(rtl->parent, "switch registration failed\n");
1486
1487 return err;
1488 }
1489
1490 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1491 {
1492 unregister_switch(&rtl->dev);
1493 }
1494
1495 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1496 {
1497 struct rtl8366_smi *smi = bus->priv;
1498 u32 val = 0;
1499 int err;
1500
1501 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1502 if (err)
1503 return 0xffff;
1504
1505 return val;
1506 }
1507
1508 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1509 {
1510 struct rtl8366_smi *smi = bus->priv;
1511 u32 t;
1512 int err;
1513
1514 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1515 /* flush write */
1516 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1517
1518 return err;
1519 }
1520
1521 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1522 {
1523 return (bus->read == rtl8366s_mii_read &&
1524 bus->write == rtl8366s_mii_write);
1525 }
1526
1527 static int rtl8366s_setup(struct rtl8366s *rtl)
1528 {
1529 struct rtl8366_smi *smi = &rtl->smi;
1530 int ret;
1531
1532 ret = rtl8366s_reset_chip(smi);
1533 if (ret)
1534 return ret;
1535
1536 rtl8366s_debugfs_init(rtl);
1537 return 0;
1538 }
1539
1540 static int rtl8366s_detect(struct rtl8366_smi *smi)
1541 {
1542 u32 chip_id = 0;
1543 u32 chip_ver = 0;
1544 int ret;
1545
1546 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1547 if (ret) {
1548 dev_err(smi->parent, "unable to read chip id\n");
1549 return ret;
1550 }
1551
1552 switch (chip_id) {
1553 case RTL8366S_CHIP_ID_8366:
1554 break;
1555 default:
1556 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1557 return -ENODEV;
1558 }
1559
1560 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1561 &chip_ver);
1562 if (ret) {
1563 dev_err(smi->parent, "unable to read chip version\n");
1564 return ret;
1565 }
1566
1567 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1568 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1569
1570 return 0;
1571 }
1572
1573 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1574 .detect = rtl8366s_detect,
1575 .mii_read = rtl8366s_mii_read,
1576 .mii_write = rtl8366s_mii_write,
1577 };
1578
1579 static int __init rtl8366s_probe(struct platform_device *pdev)
1580 {
1581 static int rtl8366_smi_version_printed;
1582 struct rtl8366s_platform_data *pdata;
1583 struct rtl8366s *rtl;
1584 struct rtl8366_smi *smi;
1585 int err;
1586
1587 if (!rtl8366_smi_version_printed++)
1588 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1589 " version " RTL8366S_DRIVER_VER"\n");
1590
1591 pdata = pdev->dev.platform_data;
1592 if (!pdata) {
1593 dev_err(&pdev->dev, "no platform data specified\n");
1594 err = -EINVAL;
1595 goto err_out;
1596 }
1597
1598 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1599 if (!rtl) {
1600 dev_err(&pdev->dev, "no memory for private data\n");
1601 err = -ENOMEM;
1602 goto err_out;
1603 }
1604
1605 rtl->parent = &pdev->dev;
1606
1607 smi = &rtl->smi;
1608 smi->parent = &pdev->dev;
1609 smi->gpio_sda = pdata->gpio_sda;
1610 smi->gpio_sck = pdata->gpio_sck;
1611 smi->ops = &rtl8366s_smi_ops;
1612
1613 err = rtl8366_smi_init(smi);
1614 if (err)
1615 goto err_free_rtl;
1616
1617 platform_set_drvdata(pdev, rtl);
1618
1619 err = rtl8366s_setup(rtl);
1620 if (err)
1621 goto err_clear_drvdata;
1622
1623 err = rtl8366s_switch_init(rtl);
1624 if (err)
1625 goto err_clear_drvdata;
1626
1627 return 0;
1628
1629 err_clear_drvdata:
1630 platform_set_drvdata(pdev, NULL);
1631 rtl8366_smi_cleanup(smi);
1632 err_free_rtl:
1633 kfree(rtl);
1634 err_out:
1635 return err;
1636 }
1637
1638 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1639 {
1640 if (!rtl8366s_mii_bus_match(phydev->bus))
1641 return -EINVAL;
1642
1643 return 0;
1644 }
1645
1646 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1647 {
1648 return 0;
1649 }
1650
1651 static struct phy_driver rtl8366s_phy_driver = {
1652 .phy_id = 0x001cc960,
1653 .name = "Realtek RTL8366S",
1654 .phy_id_mask = 0x1ffffff0,
1655 .features = PHY_GBIT_FEATURES,
1656 .config_aneg = rtl8366s_phy_config_aneg,
1657 .config_init = rtl8366s_phy_config_init,
1658 .read_status = genphy_read_status,
1659 .driver = {
1660 .owner = THIS_MODULE,
1661 },
1662 };
1663
1664 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1665 {
1666 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1667
1668 if (rtl) {
1669 rtl8366s_switch_cleanup(rtl);
1670 rtl8366s_debugfs_remove(rtl);
1671 platform_set_drvdata(pdev, NULL);
1672 rtl8366_smi_cleanup(&rtl->smi);
1673 kfree(rtl);
1674 }
1675
1676 return 0;
1677 }
1678
1679 static struct platform_driver rtl8366s_driver = {
1680 .driver = {
1681 .name = RTL8366S_DRIVER_NAME,
1682 .owner = THIS_MODULE,
1683 },
1684 .probe = rtl8366s_probe,
1685 .remove = __devexit_p(rtl8366s_remove),
1686 };
1687
1688 static int __init rtl8366s_module_init(void)
1689 {
1690 int ret;
1691 ret = platform_driver_register(&rtl8366s_driver);
1692 if (ret)
1693 return ret;
1694
1695 ret = phy_driver_register(&rtl8366s_phy_driver);
1696 if (ret)
1697 goto err_platform_unregister;
1698
1699 return 0;
1700
1701 err_platform_unregister:
1702 platform_driver_unregister(&rtl8366s_driver);
1703 return ret;
1704 }
1705 module_init(rtl8366s_module_init);
1706
1707 static void __exit rtl8366s_module_exit(void)
1708 {
1709 phy_driver_unregister(&rtl8366s_phy_driver);
1710 platform_driver_unregister(&rtl8366s_driver);
1711 }
1712 module_exit(rtl8366s_module_exit);
1713
1714 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1715 MODULE_VERSION(RTL8366S_DRIVER_VER);
1716 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1717 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1718 MODULE_LICENSE("GPL v2");
1719 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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