target/linux/generic/backport-5.10/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch

   1 From: Johan Almbladh <johan.almbladh@anyfinetworks.com>
   2 Date: Tue, 5 Oct 2021 18:54:02 +0200
   3 Subject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6
   4
   5 Enable the 'muhu' instruction, complementing the existing 'mulu', needed
   6 to implement a MIPS32 BPF JIT.
   7
   8 Also fix a typo in the existing definition of 'dmulu'.
   9
  10 Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
  11
  12 This patch is a dependency for my 32-bit MIPS eBPF JIT.
  13
  14 Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
  15 ---
  16
  17 --- a/arch/mips/include/asm/uasm.h
  18 +++ b/arch/mips/include/asm/uasm.h
  19 @@ -145,6 +145,7 @@ Ip_u1(_mtlo);
  20  Ip_u3u1u2(_mul);
  21  Ip_u1u2(_multu);
  22  Ip_u3u1u2(_mulu);
  23 +Ip_u3u1u2(_muhu);
  24  Ip_u3u1u2(_nor);
  25  Ip_u3u1u2(_or);
  26  Ip_u2u1u3(_ori);
  27 --- a/arch/mips/mm/uasm-mips.c
  28 +++ b/arch/mips/mm/uasm-mips.c
  29 @@ -90,7 +90,7 @@ static const struct insn insn_table[insn
  30                                 RS | RT | RD},
  31         [insn_dmtc0]    = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
  32         [insn_dmultu]   = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
  33 -       [insn_dmulu]    = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
  34 +       [insn_dmulu]    = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
  35                                 RS | RT | RD},
  36         [insn_drotr]    = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
  37         [insn_drotr32]  = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
  38 @@ -150,6 +150,8 @@ static const struct insn insn_table[insn
  39         [insn_mtlo]     = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
  40         [insn_mulu]     = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
  41                                 RS | RT | RD},
  42 +       [insn_muhu]     = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
  43 +                               RS | RT | RD},
  44  #ifndef CONFIG_CPU_MIPSR6
  45         [insn_mul]      = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
  46  #else
  47 --- a/arch/mips/mm/uasm.c
  48 +++ b/arch/mips/mm/uasm.c
  49 @@ -59,7 +59,7 @@ enum opcode {
  50         insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
  51         insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
  52         insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
  53 -       insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
  54 +       insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
  55         insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
  56         insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
  57         insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
  58 @@ -344,6 +344,7 @@ I_u1(_mtlo)
  59  I_u3u1u2(_mul)
  60  I_u1u2(_multu)
  61  I_u3u1u2(_mulu)
  62 +I_u3u1u2(_muhu)
  63  I_u3u1u2(_nor)
  64  I_u3u1u2(_or)
  65  I_u2u1u3(_ori)