target/linux/generic/backport-5.10/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch

   1 From 620a988813403318023296b61228ee8f3fcdb8e0 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Sun, 20 Mar 2022 17:59:59 +0800
   4 Subject: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG
   5
   6 This chip is the 1.8v version of GD5F1GQ5UExxG.
   7
   8 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
   9 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  10 Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.com
  11 ---
  12  drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++
  13  1 file changed, 10 insertions(+)
  14
  15 --- a/drivers/mtd/nand/spi/gigadevice.c
  16 +++ b/drivers/mtd/nand/spi/gigadevice.c
  17 @@ -383,6 +383,16 @@ static const struct spinand_info gigadev
  18                      SPINAND_HAS_QE_BIT,
  19                      SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  20                                      gd5fxgq5xexxg_ecc_get_status)),
  21 +       SPINAND_INFO("GD5F1GQ5RExxG",
  22 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
  23 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
  24 +                    NAND_ECCREQ(4, 512),
  25 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  26 +                                             &write_cache_variants,
  27 +                                             &update_cache_variants),
  28 +                    SPINAND_HAS_QE_BIT,
  29 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  30 +                                    gd5fxgq5xexxg_ecc_get_status)),
  31  };
  32
  33  static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {