target/linux/generic/backport-5.10/737-v5.14-01-net-dsa-qca8k-check-return-value-of-read-functions-c.patch

   1 From 7c9896e37807862e276064dd9331860f5d27affc Mon Sep 17 00:00:00 2001
   2 From: Yang Yingliang <yangyingliang@huawei.com>
   3 Date: Sat, 29 May 2021 11:04:38 +0800
   4 Subject: [PATCH] net: dsa: qca8k: check return value of read functions
   5  correctly
   6
   7 Current return type of qca8k_mii_read32() and qca8k_read() are
   8 unsigned, it can't be negative, so the return value check is
   9 unuseful. For check the return value correctly, change return
  10 type of the read functions and add a output parameter to store
  11 the read value.
  12
  13 Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/dsa/qca8k.c | 130 +++++++++++++++++++---------------------
  17  1 file changed, 60 insertions(+), 70 deletions(-)
  18
  19 --- a/drivers/net/dsa/qca8k.c
  20 +++ b/drivers/net/dsa/qca8k.c
  21 @@ -89,26 +89,26 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
  22         *page = regaddr & 0x3ff;
  23  }
  24
  25 -static u32
  26 -qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
  27 +static int
  28 +qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  29  {
  30 -       u32 val;
  31         int ret;
  32
  33         ret = bus->read(bus, phy_id, regnum);
  34         if (ret >= 0) {
  35 -               val = ret;
  36 +               *val = ret;
  37                 ret = bus->read(bus, phy_id, regnum + 1);
  38 -               val |= ret << 16;
  39 +               *val |= ret << 16;
  40         }
  41
  42         if (ret < 0) {
  43                 dev_err_ratelimited(&bus->dev,
  44                                     "failed to read qca8k 32bit register\n");
  45 +               *val = 0;
  46                 return ret;
  47         }
  48
  49 -       return val;
  50 +       return 0;
  51  }
  52
  53  static void
  54 @@ -148,26 +148,26 @@ qca8k_set_page(struct mii_bus *bus, u16
  55         return 0;
  56  }
  57
  58 -static u32
  59 -qca8k_read(struct qca8k_priv *priv, u32 reg)
  60 +static int
  61 +qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
  62  {
  63         struct mii_bus *bus = priv->bus;
  64         u16 r1, r2, page;
  65 -       u32 val;
  66 +       int ret;
  67
  68         qca8k_split_addr(reg, &r1, &r2, &page);
  69
  70         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
  71
  72 -       val = qca8k_set_page(bus, page);
  73 -       if (val < 0)
  74 +       ret = qca8k_set_page(bus, page);
  75 +       if (ret < 0)
  76                 goto exit;
  77
  78 -       val = qca8k_mii_read32(bus, 0x10 | r2, r1);
  79 +       ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
  80
  81  exit:
  82         mutex_unlock(&bus->mdio_lock);
  83 -       return val;
  84 +       return ret;
  85  }
  86
  87  static int
  88 @@ -208,11 +208,9 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r
  89         if (ret < 0)
  90                 goto exit;
  91
  92 -       val = qca8k_mii_read32(bus, 0x10 | r2, r1);
  93 -       if (val < 0) {
  94 -               ret = val;
  95 +       ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
  96 +       if (ret < 0)
  97                 goto exit;
  98 -       }
  99
 100         val &= ~mask;
 101         val |= write_val;
 102 @@ -240,15 +238,8 @@ static int
 103  qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 104  {
 105         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 106 -       int ret;
 107 -
 108 -       ret = qca8k_read(priv, reg);
 109 -       if (ret < 0)
 110 -               return ret;
 111 -
 112 -       *val = ret;
 113
 114 -       return 0;
 115 +       return qca8k_read(priv, reg, val);
 116  }
 117
 118  static int
 119 @@ -296,18 +287,18 @@ static struct regmap_config qca8k_regmap
 120  static int
 121  qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 122  {
 123 +       int ret, ret1;
 124         u32 val;
 125 -       int ret;
 126
 127 -       ret = read_poll_timeout(qca8k_read, val, !(val & mask),
 128 +       ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
 129                                 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 130 -                               priv, reg);
 131 +                               priv, reg, &val);
 132
 133         /* Check if qca8k_read has failed for a different reason
 134          * before returning -ETIMEDOUT
 135          */
 136 -       if (ret < 0 && val < 0)
 137 -               return val;
 138 +       if (ret < 0 && ret1 < 0)
 139 +               return ret1;
 140
 141         return ret;
 142  }
 143 @@ -316,13 +307,13 @@ static int
 144  qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 145  {
 146         u32 reg[4], val;
 147 -       int i;
 148 +       int i, ret;
 149
 150         /* load the ARL table into an array */
 151         for (i = 0; i < 4; i++) {
 152 -               val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
 153 -               if (val < 0)
 154 -                       return val;
 155 +               ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
 156 +               if (ret < 0)
 157 +                       return ret;
 158
 159                 reg[i] = val;
 160         }
 161 @@ -396,9 +387,9 @@ qca8k_fdb_access(struct qca8k_priv *priv
 162
 163         /* Check for table full violation when adding an entry */
 164         if (cmd == QCA8K_FDB_LOAD) {
 165 -               reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
 166 -               if (reg < 0)
 167 -                       return reg;
 168 +               ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
 169 +               if (ret < 0)
 170 +                       return ret;
 171                 if (reg & QCA8K_ATU_FUNC_FULL)
 172                         return -1;
 173         }
 174 @@ -477,9 +468,9 @@ qca8k_vlan_access(struct qca8k_priv *pri
 175
 176         /* Check for table full violation when adding an entry */
 177         if (cmd == QCA8K_VLAN_LOAD) {
 178 -               reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);
 179 -               if (reg < 0)
 180 -                       return reg;
 181 +               ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
 182 +               if (ret < 0)
 183 +                       return ret;
 184                 if (reg & QCA8K_VTU_FUNC1_FULL)
 185                         return -ENOMEM;
 186         }
 187 @@ -505,11 +496,9 @@ qca8k_vlan_add(struct qca8k_priv *priv,
 188         if (ret < 0)
 189                 goto out;
 190
 191 -       reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
 192 -       if (reg < 0) {
 193 -               ret = reg;
 194 +       ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 195 +       if (ret < 0)
 196                 goto out;
 197 -       }
 198         reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
 199         reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 200         if (untagged)
 201 @@ -542,11 +531,9 @@ qca8k_vlan_del(struct qca8k_priv *priv,
 202         if (ret < 0)
 203                 goto out;
 204
 205 -       reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
 206 -       if (reg < 0) {
 207 -               ret = reg;
 208 +       ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 209 +       if (ret < 0)
 210                 goto out;
 211 -       }
 212         reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 213         reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
 214                         QCA8K_VTU_FUNC0_EG_MODE_S(port);
 215 @@ -638,19 +625,19 @@ qca8k_mdio_busy_wait(struct mii_bus *bus
 216  {
 217         u16 r1, r2, page;
 218         u32 val;
 219 -       int ret;
 220 +       int ret, ret1;
 221
 222         qca8k_split_addr(reg, &r1, &r2, &page);
 223
 224 -       ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,
 225 +       ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
 226                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 227 -                               bus, 0x10 | r2, r1);
 228 +                               bus, 0x10 | r2, r1, &val);
 229
 230         /* Check if qca8k_read has failed for a different reason
 231          * before returnting -ETIMEDOUT
 232          */
 233 -       if (ret < 0 && val < 0)
 234 -               return val;
 235 +       if (ret < 0 && ret1 < 0)
 236 +               return ret1;
 237
 238         return ret;
 239  }
 240 @@ -725,7 +712,7 @@ qca8k_mdio_read(struct mii_bus *salve_bu
 241         if (ret)
 242                 goto exit;
 243
 244 -       val = qca8k_mii_read32(bus, 0x10 | r2, r1);
 245 +       ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 246
 247  exit:
 248         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 249 @@ -733,10 +720,10 @@ exit:
 250
 251         mutex_unlock(&bus->mdio_lock);
 252
 253 -       if (val >= 0)
 254 -               val &= QCA8K_MDIO_MASTER_DATA_MASK;
 255 +       if (ret >= 0)
 256 +               ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 257
 258 -       return val;
 259 +       return ret;
 260  }
 261
 262  static int
 263 @@ -1211,7 +1198,7 @@ qca8k_phylink_mac_config(struct dsa_swit
 264                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 265
 266                 /* Enable/disable SerDes auto-negotiation as necessary */
 267 -               val = qca8k_read(priv, QCA8K_REG_PWS);
 268 +               qca8k_read(priv, QCA8K_REG_PWS, &val);
 269                 if (phylink_autoneg_inband(mode))
 270                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
 271                 else
 272 @@ -1219,7 +1206,7 @@ qca8k_phylink_mac_config(struct dsa_swit
 273                 qca8k_write(priv, QCA8K_REG_PWS, val);
 274
 275                 /* Configure the SGMII parameters */
 276 -               val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);
 277 +               qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
 278
 279                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
 280                         QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
 281 @@ -1314,10 +1301,11 @@ qca8k_phylink_mac_link_state(struct dsa_
 282  {
 283         struct qca8k_priv *priv = ds->priv;
 284         u32 reg;
 285 +       int ret;
 286
 287 -       reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));
 288 -       if (reg < 0)
 289 -               return reg;
 290 +       ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
 291 +       if (ret < 0)
 292 +               return ret;
 293
 294         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
 295         state->an_complete = state->link;
 296 @@ -1419,19 +1407,20 @@ qca8k_get_ethtool_stats(struct dsa_switc
 297         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 298         const struct qca8k_mib_desc *mib;
 299         u32 reg, i, val;
 300 -       u64 hi;
 301 +       u64 hi = 0;
 302 +       int ret;
 303
 304         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
 305                 mib = &ar8327_mib[i];
 306                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
 307
 308 -               val = qca8k_read(priv, reg);
 309 -               if (val < 0)
 310 +               ret = qca8k_read(priv, reg, &val);
 311 +               if (ret < 0)
 312                         continue;
 313
 314                 if (mib->size == 2) {
 315 -                       hi = qca8k_read(priv, reg + 4);
 316 -                       if (hi < 0)
 317 +                       ret = qca8k_read(priv, reg + 4, (u32 *)&hi);
 318 +                       if (ret < 0)
 319                                 continue;
 320                 }
 321
 322 @@ -1459,7 +1448,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds,
 323         int ret;
 324
 325         mutex_lock(&priv->reg_mutex);
 326 -       reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
 327 +       ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
 328         if (reg < 0) {
 329                 ret = reg;
 330                 goto exit;
 331 @@ -1802,14 +1791,15 @@ static int qca8k_read_switch_id(struct q
 332         const struct qca8k_match_data *data;
 333         u32 val;
 334         u8 id;
 335 +       int ret;
 336
 337         /* get the switches ID from the compatible */
 338         data = of_device_get_match_data(priv->dev);
 339         if (!data)
 340                 return -ENODEV;
 341
 342 -       val = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
 343 -       if (val < 0)
 344 +       ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
 345 +       if (ret < 0)
 346                 return -ENODEV;
 347
 348         id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);