target/linux/generic/backport-5.10/737-v5.14-02-net-dsa-qca8k-add-missing-check-return-value-in-qca8.patch

   1 From 9fe99de01440d9ede74d447ac76e9c445d8daae9 Mon Sep 17 00:00:00 2001
   2 From: Yang Yingliang <yangyingliang@huawei.com>
   3 Date: Sat, 29 May 2021 11:04:39 +0800
   4 Subject: [PATCH] net: dsa: qca8k: add missing check return value in
   5  qca8k_phylink_mac_config()
   6
   7 Now we can check qca8k_read() return value correctly, so if
   8 it fails, we need return directly.
   9
  10 Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
  11 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  12 ---
  13  drivers/net/dsa/qca8k.c | 9 +++++++--
  14  1 file changed, 7 insertions(+), 2 deletions(-)
  15
  16 --- a/drivers/net/dsa/qca8k.c
  17 +++ b/drivers/net/dsa/qca8k.c
  18 @@ -1128,6 +1128,7 @@ qca8k_phylink_mac_config(struct dsa_swit
  19  {
  20         struct qca8k_priv *priv = ds->priv;
  21         u32 reg, val;
  22 +       int ret;
  23
  24         switch (port) {
  25         case 0: /* 1st CPU port */
  26 @@ -1198,7 +1199,9 @@ qca8k_phylink_mac_config(struct dsa_swit
  27                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
  28
  29                 /* Enable/disable SerDes auto-negotiation as necessary */
  30 -               qca8k_read(priv, QCA8K_REG_PWS, &val);
  31 +               ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
  32 +               if (ret)
  33 +                       return;
  34                 if (phylink_autoneg_inband(mode))
  35                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
  36                 else
  37 @@ -1206,7 +1209,9 @@ qca8k_phylink_mac_config(struct dsa_swit
  38                 qca8k_write(priv, QCA8K_REG_PWS, val);
  39
  40                 /* Configure the SGMII parameters */
  41 -               qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
  42 +               ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
  43 +               if (ret)
  44 +                       return;
  45
  46                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  47                         QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;