target/linux/generic/backport-5.10/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch

   1 From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:13 +0200
   4 Subject: net: dsa: qca8k: add explicit SGMII PLL enable
   5
   6 Support enabling PLL on the SGMII CPU port. Some device require this
   7 special configuration or no traffic is transmitted and the switch
   8 doesn't work at all. A dedicated binding is added to the CPU node
   9 port to apply the correct reg on mac config.
  10 Fail to correctly configure sgmii with qca8327 switch and warn if pll is
  11 used on qca8337 with a revision greater than 1.
  12
  13 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  14 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17  drivers/net/dsa/qca8k.c | 19 +++++++++++++++++--
  18  drivers/net/dsa/qca8k.h |  1 +
  19  2 files changed, 18 insertions(+), 2 deletions(-)
  20
  21 --- a/drivers/net/dsa/qca8k.c
  22 +++ b/drivers/net/dsa/qca8k.c
  23 @@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri
  24                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
  25                                 priv->sgmii_rx_clk_falling_edge = true;
  26
  27 +                       if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
  28 +                               priv->sgmii_enable_pll = true;
  29 +
  30 +                               if (priv->switch_id == QCA8K_ID_QCA8327) {
  31 +                                       dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
  32 +                                       priv->sgmii_enable_pll = false;
  33 +                               }
  34 +
  35 +                               if (priv->switch_revision < 2)
  36 +                                       dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
  37 +                       }
  38 +
  39                         break;
  40                 default:
  41                         continue;
  42 @@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit
  43                 if (ret)
  44                         return;
  45
  46 -               val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  47 -                       QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
  48 +               val |= QCA8K_SGMII_EN_SD;
  49 +
  50 +               if (priv->sgmii_enable_pll)
  51 +                       val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  52 +                              QCA8K_SGMII_EN_TX;
  53
  54                 if (dsa_is_cpu_port(ds, port)) {
  55                         /* CPU port, we're talking to the CPU MAC, be a PHY */
  56 --- a/drivers/net/dsa/qca8k.h
  57 +++ b/drivers/net/dsa/qca8k.h
  58 @@ -266,6 +266,7 @@ struct qca8k_priv {
  59         u8 switch_revision;
  60         bool sgmii_rx_clk_falling_edge;
  61         bool sgmii_tx_clk_falling_edge;
  62 +       bool sgmii_enable_pll;
  63         u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
  64         u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
  65         bool legacy_phy_port_mapping;