target/linux/generic/backport-5.10/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch

   1 From 362bb238d8bf1470424214a8a5968d9c6cce68fa Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:15 +0200
   4 Subject: net: dsa: qca8k: add support for pws config reg
   5
   6 Some qca8327 switch require to force the ignore of power on sel
   7 strapping. Some switch require to set the led open drain mode in regs
   8 instead of using strapping. While most of the device implements this
   9 using the correct way using pin strapping, there are still some broken
  10 device that require to be set using sw regs.
  11 Introduce a new binding and support these special configuration.
  12 As led open drain require to ignore pin strapping to work, the probe
  13 fails with EINVAL error with incorrect configuration.
  14
  15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  16 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++
  20  drivers/net/dsa/qca8k.h |  6 ++++++
  21  2 files changed, 45 insertions(+)
  22
  23 --- a/drivers/net/dsa/qca8k.c
  24 +++ b/drivers/net/dsa/qca8k.c
  25 @@ -932,6 +932,41 @@ static int qca8k_find_cpu_port(struct ds
  26  }
  27
  28  static int
  29 +qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
  30 +{
  31 +       struct device_node *node = priv->dev->of_node;
  32 +       u32 val = 0;
  33 +       int ret;
  34 +
  35 +       /* QCA8327 require to set to the correct mode.
  36 +        * His bigger brother QCA8328 have the 172 pin layout.
  37 +        * Should be applied by default but we set this just to make sure.
  38 +        */
  39 +       if (priv->switch_id == QCA8K_ID_QCA8327) {
  40 +               ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
  41 +                               QCA8327_PWS_PACKAGE148_EN);
  42 +               if (ret)
  43 +                       return ret;
  44 +       }
  45 +
  46 +       if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
  47 +               val |= QCA8K_PWS_POWER_ON_SEL;
  48 +
  49 +       if (of_property_read_bool(node, "qca,led-open-drain")) {
  50 +               if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
  51 +                       dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
  52 +                       return -EINVAL;
  53 +               }
  54 +
  55 +               val |= QCA8K_PWS_LED_OPEN_EN_CSR;
  56 +       }
  57 +
  58 +       return qca8k_rmw(priv, QCA8K_REG_PWS,
  59 +                       QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
  60 +                       val);
  61 +}
  62 +
  63 +static int
  64  qca8k_parse_port_config(struct qca8k_priv *priv)
  65  {
  66         int port, cpu_port_index = 0, ret;
  67 @@ -1053,6 +1088,10 @@ qca8k_setup(struct dsa_switch *ds)
  68         if (ret)
  69                 return ret;
  70
  71 +       ret = qca8k_setup_of_pws_reg(priv);
  72 +       if (ret)
  73 +               return ret;
  74 +
  75         ret = qca8k_setup_mac_pwr_sel(priv);
  76         if (ret)
  77                 return ret;
  78 --- a/drivers/net/dsa/qca8k.h
  79 +++ b/drivers/net/dsa/qca8k.h
  80 @@ -46,6 +46,12 @@
  81  #define   QCA8K_MAX_DELAY                              3
  82  #define   QCA8K_PORT_PAD_SGMII_EN                      BIT(7)
  83  #define QCA8K_REG_PWS                                  0x010
  84 +#define   QCA8K_PWS_POWER_ON_SEL                       BIT(31)
  85 +/* This reg is only valid for QCA832x and toggle the package
  86 + * type from 176 pin (by default) to 148 pin used on QCA8327
  87 + */
  88 +#define   QCA8327_PWS_PACKAGE148_EN                    BIT(30)
  89 +#define   QCA8K_PWS_LED_OPEN_EN_CSR                    BIT(24)
  90  #define   QCA8K_PWS_SERDES_AEN_DIS                     BIT(7)
  91  #define QCA8K_REG_MODULE_EN                            0x030
  92  #define   QCA8K_MODULE_EN_MIB                          BIT(0)