target/linux/generic/backport-5.10/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch

   1 From d291fbb8245d5ba04979fed85575860a5cea7196 Mon Sep 17 00:00:00 2001
   2 From: Matthew Hagan <mnhagan88@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:21 +0200
   4 Subject: dt-bindings: net: dsa: qca8k: convert to YAML schema
   5
   6 Convert the qca8k bindings to YAML format.
   7
   8 Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
   9 Co-developed-by: Ansuel Smith <ansuelsmth@gmail.com>
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Signed-off-by: David S. Miller <davem@davemloft.net>
  12 ---
  13  .../devicetree/bindings/net/dsa/qca8k.txt          | 245 --------------
  14  .../devicetree/bindings/net/dsa/qca8k.yaml         | 362 +++++++++++++++++++++
  15  2 files changed, 362 insertions(+), 245 deletions(-)
  16  delete mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt
  17  create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.yaml
  18
  19 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  20 +++ /dev/null
  21 @@ -1,245 +0,0 @@
  22 -* Qualcomm Atheros QCA8xxx switch family
  23 -
  24 -Required properties:
  25 -
  26 -- compatible: should be one of:
  27 -    "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
  28 -    "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package
  29 -    "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package
  30 -    "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
  31 -
  32 -- #size-cells: must be 0
  33 -- #address-cells: must be 1
  34 -
  35 -Optional properties:
  36 -
  37 -- reset-gpios: GPIO to be used to reset the whole device
  38 -- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open
  39 -                           drain or eeprom presence. This is needed for broken
  40 -                           devices that have wrong configuration or when the oem
  41 -                           decided to not use pin strapping and fallback to sw
  42 -                           regs.
  43 -- qca,led-open-drain: Set leds to open-drain mode. This requires the
  44 -                      qca,ignore-power-on-sel to be set or the driver will fail
  45 -                      to probe. This is needed if the oem doesn't use pin
  46 -                      strapping to set this mode and prefers to set it using sw
  47 -                      regs. The pin strapping related to led open drain mode is
  48 -                      the pin B68 for QCA832x and B49 for QCA833x
  49 -
  50 -Subnodes:
  51 -
  52 -The integrated switch subnode should be specified according to the binding
  53 -described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
  54 -mdio-bus each subnode describing a port needs to have a valid phandle
  55 -referencing the internal PHY it is connected to. This is because there's no
  56 -N:N mapping of port and PHY id.
  57 -To declare the internal mdio-bus configuration, declare a mdio node in the
  58 -switch node and declare the phandle for the port referencing the internal
  59 -PHY is connected to. In this config a internal mdio-bus is registered and
  60 -the mdio MASTER is used as communication.
  61 -
  62 -Don't use mixed external and internal mdio-bus configurations, as this is
  63 -not supported by the hardware.
  64 -
  65 -This switch support 2 CPU port. Normally and advised configuration is with
  66 -CPU port set to port 0. It is also possible to set the CPU port to port 6
  67 -if the device requires it. The driver will configure the switch to the defined
  68 -port. With both CPU port declared the first CPU port is selected as primary
  69 -and the secondary CPU ignored.
  70 -
  71 -A CPU port node has the following optional node:
  72 -
  73 -- fixed-link            : Fixed-link subnode describing a link to a non-MDIO
  74 -                          managed entity. See
  75 -                          Documentation/devicetree/bindings/net/fixed-link.txt
  76 -                          for details.
  77 -- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.
  78 -                                Mostly used in qca8327 with CPU port 0 set to
  79 -                                sgmii.
  80 -- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
  81 -- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX
  82 -                          chain along with Signal Detection.
  83 -                          This should NOT be enabled for qca8327. If enabled with
  84 -                          qca8327 the sgmii port won't correctly init and an err
  85 -                          is printed.
  86 -                          This can be required for qca8337 switch with revision 2.
  87 -                          A warning is displayed when used with revision greater
  88 -                          2.
  89 -                          With CPU port set to sgmii and qca8337 it is advised
  90 -                          to set this unless a communication problem is observed.
  91 -
  92 -For QCA8K the 'fixed-link' sub-node supports only the following properties:
  93 -
  94 -- 'speed' (integer, mandatory), to indicate the link speed. Accepted
  95 -  values are 10, 100 and 1000
  96 -- 'full-duplex' (boolean, optional), to indicate that full duplex is
  97 -  used. When absent, half duplex is assumed.
  98 -
  99 -Examples:
 100 -
 101 -for the external mdio-bus configuration:
 102 -
 103 -       &mdio0 {
 104 -               phy_port1: phy@0 {
 105 -                       reg = <0>;
 106 -               };
 107 -
 108 -               phy_port2: phy@1 {
 109 -                       reg = <1>;
 110 -               };
 111 -
 112 -               phy_port3: phy@2 {
 113 -                       reg = <2>;
 114 -               };
 115 -
 116 -               phy_port4: phy@3 {
 117 -                       reg = <3>;
 118 -               };
 119 -
 120 -               phy_port5: phy@4 {
 121 -                       reg = <4>;
 122 -               };
 123 -
 124 -               switch@10 {
 125 -                       compatible = "qca,qca8337";
 126 -                       #address-cells = <1>;
 127 -                       #size-cells = <0>;
 128 -
 129 -                       reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 130 -                       reg = <0x10>;
 131 -
 132 -                       ports {
 133 -                               #address-cells = <1>;
 134 -                               #size-cells = <0>;
 135 -                               port@0 {
 136 -                                       reg = <0>;
 137 -                                       label = "cpu";
 138 -                                       ethernet = <&gmac1>;
 139 -                                       phy-mode = "rgmii";
 140 -                                       fixed-link {
 141 -                                               speed = 1000;
 142 -                                               full-duplex;
 143 -                                       };
 144 -                               };
 145 -
 146 -                               port@1 {
 147 -                                       reg = <1>;
 148 -                                       label = "lan1";
 149 -                                       phy-handle = <&phy_port1>;
 150 -                               };
 151 -
 152 -                               port@2 {
 153 -                                       reg = <2>;
 154 -                                       label = "lan2";
 155 -                                       phy-handle = <&phy_port2>;
 156 -                               };
 157 -
 158 -                               port@3 {
 159 -                                       reg = <3>;
 160 -                                       label = "lan3";
 161 -                                       phy-handle = <&phy_port3>;
 162 -                               };
 163 -
 164 -                               port@4 {
 165 -                                       reg = <4>;
 166 -                                       label = "lan4";
 167 -                                       phy-handle = <&phy_port4>;
 168 -                               };
 169 -
 170 -                               port@5 {
 171 -                                       reg = <5>;
 172 -                                       label = "wan";
 173 -                                       phy-handle = <&phy_port5>;
 174 -                               };
 175 -                       };
 176 -               };
 177 -       };
 178 -
 179 -for the internal master mdio-bus configuration:
 180 -
 181 -       &mdio0 {
 182 -               switch@10 {
 183 -                       compatible = "qca,qca8337";
 184 -                       #address-cells = <1>;
 185 -                       #size-cells = <0>;
 186 -
 187 -                       reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 188 -                       reg = <0x10>;
 189 -
 190 -                       ports {
 191 -                               #address-cells = <1>;
 192 -                               #size-cells = <0>;
 193 -
 194 -                               port@0 {
 195 -                                       reg = <0>;
 196 -                                       label = "cpu";
 197 -                                       ethernet = <&gmac1>;
 198 -                                       phy-mode = "rgmii";
 199 -                                       fixed-link {
 200 -                                               speed = 1000;
 201 -                                               full-duplex;
 202 -                                       };
 203 -                               };
 204 -
 205 -                               port@1 {
 206 -                                       reg = <1>;
 207 -                                       label = "lan1";
 208 -                                       phy-mode = "internal";
 209 -                                       phy-handle = <&phy_port1>;
 210 -                               };
 211 -
 212 -                               port@2 {
 213 -                                       reg = <2>;
 214 -                                       label = "lan2";
 215 -                                       phy-mode = "internal";
 216 -                                       phy-handle = <&phy_port2>;
 217 -                               };
 218 -
 219 -                               port@3 {
 220 -                                       reg = <3>;
 221 -                                       label = "lan3";
 222 -                                       phy-mode = "internal";
 223 -                                       phy-handle = <&phy_port3>;
 224 -                               };
 225 -
 226 -                               port@4 {
 227 -                                       reg = <4>;
 228 -                                       label = "lan4";
 229 -                                       phy-mode = "internal";
 230 -                                       phy-handle = <&phy_port4>;
 231 -                               };
 232 -
 233 -                               port@5 {
 234 -                                       reg = <5>;
 235 -                                       label = "wan";
 236 -                                       phy-mode = "internal";
 237 -                                       phy-handle = <&phy_port5>;
 238 -                               };
 239 -                       };
 240 -
 241 -                       mdio {
 242 -                               #address-cells = <1>;
 243 -                               #size-cells = <0>;
 244 -
 245 -                               phy_port1: phy@0 {
 246 -                                       reg = <0>;
 247 -                               };
 248 -
 249 -                               phy_port2: phy@1 {
 250 -                                       reg = <1>;
 251 -                               };
 252 -
 253 -                               phy_port3: phy@2 {
 254 -                                       reg = <2>;
 255 -                               };
 256 -
 257 -                               phy_port4: phy@3 {
 258 -                                       reg = <3>;
 259 -                               };
 260 -
 261 -                               phy_port5: phy@4 {
 262 -                                       reg = <4>;
 263 -                               };
 264 -                       };
 265 -               };
 266 -       };
 267 --- /dev/null
 268 +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml
 269 @@ -0,0 +1,362 @@
 270 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 271 +%YAML 1.2
 272 +---
 273 +$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
 274 +$schema: http://devicetree.org/meta-schemas/core.yaml#
 275 +
 276 +title: Qualcomm Atheros QCA83xx switch family
 277 +
 278 +maintainers:
 279 +  - John Crispin <john@phrozen.org>
 280 +
 281 +description:
 282 +  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
 283 +  describing a port needs to have a valid phandle referencing the internal PHY
 284 +  it is connected to. This is because there is no N:N mapping of port and PHY
 285 +  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
 286 +  the switch node and declare the phandle for the port, referencing the internal
 287 +  PHY it is connected to. In this config, an internal mdio-bus is registered and
 288 +  the MDIO master is used for communication. Mixed external and internal
 289 +  mdio-bus configurations are not supported by the hardware.
 290 +
 291 +properties:
 292 +  compatible:
 293 +    oneOf:
 294 +      - enum:
 295 +          - qca,qca8327
 296 +          - qca,qca8328
 297 +          - qca,qca8334
 298 +          - qca,qca8337
 299 +    description: |
 300 +      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
 301 +      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
 302 +      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
 303 +      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
 304 +
 305 +  reg:
 306 +    maxItems: 1
 307 +
 308 +  reset-gpios:
 309 +    description:
 310 +      GPIO to be used to reset the whole device
 311 +    maxItems: 1
 312 +
 313 +  qca,ignore-power-on-sel:
 314 +    $ref: /schemas/types.yaml#/definitions/flag
 315 +    description:
 316 +      Ignore power-on pin strapping to configure LED open-drain or EEPROM
 317 +      presence. This is needed for devices with incorrect configuration or when
 318 +      the OEM has decided not to use pin strapping and falls back to SW regs.
 319 +
 320 +  qca,led-open-drain:
 321 +    $ref: /schemas/types.yaml#/definitions/flag
 322 +    description:
 323 +      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
 324 +      be set, otherwise the driver will fail at probe. This is required if the
 325 +      OEM does not use pin strapping to set this mode and prefers to set it
 326 +      using SW regs. The pin strappings related to LED open-drain mode are
 327 +      B68 on the QCA832x and B49 on the QCA833x.
 328 +
 329 +  mdio:
 330 +    type: object
 331 +    description: Qca8k switch have an internal mdio to access switch port.
 332 +                 If this is not present, the legacy mapping is used and the
 333 +                 internal mdio access is used.
 334 +                 With the legacy mapping the reg corresponding to the internal
 335 +                 mdio is the switch reg with an offset of -1.
 336 +
 337 +    properties:
 338 +      '#address-cells':
 339 +        const: 1
 340 +      '#size-cells':
 341 +        const: 0
 342 +
 343 +    patternProperties:
 344 +      "^(ethernet-)?phy@[0-4]$":
 345 +        type: object
 346 +
 347 +        allOf:
 348 +          - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
 349 +
 350 +        properties:
 351 +          reg:
 352 +            maxItems: 1
 353 +
 354 +        required:
 355 +          - reg
 356 +
 357 +patternProperties:
 358 +  "^(ethernet-)?ports$":
 359 +    type: object
 360 +    properties:
 361 +      '#address-cells':
 362 +        const: 1
 363 +      '#size-cells':
 364 +        const: 0
 365 +
 366 +    patternProperties:
 367 +      "^(ethernet-)?port@[0-6]$":
 368 +        type: object
 369 +        description: Ethernet switch ports
 370 +
 371 +        properties:
 372 +          reg:
 373 +            description: Port number
 374 +
 375 +          label:
 376 +            description:
 377 +              Describes the label associated with this port, which will become
 378 +              the netdev name
 379 +            $ref: /schemas/types.yaml#/definitions/string
 380 +
 381 +          link:
 382 +            description:
 383 +              Should be a list of phandles to other switch's DSA port. This
 384 +              port is used as the outgoing port towards the phandle ports. The
 385 +              full routing information must be given, not just the one hop
 386 +              routes to neighbouring switches
 387 +            $ref: /schemas/types.yaml#/definitions/phandle-array
 388 +
 389 +          ethernet:
 390 +            description:
 391 +              Should be a phandle to a valid Ethernet device node.  This host
 392 +              device is what the switch port is connected to
 393 +            $ref: /schemas/types.yaml#/definitions/phandle
 394 +
 395 +          phy-handle: true
 396 +
 397 +          phy-mode: true
 398 +
 399 +          fixed-link: true
 400 +
 401 +          mac-address: true
 402 +
 403 +          sfp: true
 404 +
 405 +          qca,sgmii-rxclk-falling-edge:
 406 +            $ref: /schemas/types.yaml#/definitions/flag
 407 +            description:
 408 +              Set the receive clock phase to falling edge. Mostly commonly used on
 409 +              the QCA8327 with CPU port 0 set to SGMII.
 410 +
 411 +          qca,sgmii-txclk-falling-edge:
 412 +            $ref: /schemas/types.yaml#/definitions/flag
 413 +            description:
 414 +              Set the transmit clock phase to falling edge.
 415 +
 416 +          qca,sgmii-enable-pll:
 417 +            $ref: /schemas/types.yaml#/definitions/flag
 418 +            description:
 419 +              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
 420 +              Signal Detection. On the QCA8327 this should not be enabled, otherwise
 421 +              the SGMII port will not initialize. When used on the QCA8337, revision 3
 422 +              or greater, a warning will be displayed. When the CPU port is set to
 423 +              SGMII on the QCA8337, it is advised to set this unless a communication
 424 +              issue is observed.
 425 +
 426 +        required:
 427 +          - reg
 428 +
 429 +        additionalProperties: false
 430 +
 431 +oneOf:
 432 +  - required:
 433 +      - ports
 434 +  - required:
 435 +      - ethernet-ports
 436 +
 437 +required:
 438 +  - compatible
 439 +  - reg
 440 +
 441 +additionalProperties: true
 442 +
 443 +examples:
 444 +  - |
 445 +    #include <dt-bindings/gpio/gpio.h>
 446 +
 447 +    mdio {
 448 +        #address-cells = <1>;
 449 +        #size-cells = <0>;
 450 +
 451 +        external_phy_port1: ethernet-phy@0 {
 452 +            reg = <0>;
 453 +        };
 454 +
 455 +        external_phy_port2: ethernet-phy@1 {
 456 +            reg = <1>;
 457 +        };
 458 +
 459 +        external_phy_port3: ethernet-phy@2 {
 460 +            reg = <2>;
 461 +        };
 462 +
 463 +        external_phy_port4: ethernet-phy@3 {
 464 +            reg = <3>;
 465 +        };
 466 +
 467 +        external_phy_port5: ethernet-phy@4 {
 468 +            reg = <4>;
 469 +        };
 470 +
 471 +        switch@10 {
 472 +            compatible = "qca,qca8337";
 473 +            #address-cells = <1>;
 474 +            #size-cells = <0>;
 475 +            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 476 +            reg = <0x10>;
 477 +
 478 +            ports {
 479 +                #address-cells = <1>;
 480 +                #size-cells = <0>;
 481 +
 482 +                port@0 {
 483 +                    reg = <0>;
 484 +                    label = "cpu";
 485 +                    ethernet = <&gmac1>;
 486 +                    phy-mode = "rgmii";
 487 +
 488 +                    fixed-link {
 489 +                        speed = <1000>;
 490 +                        full-duplex;
 491 +                    };
 492 +                };
 493 +
 494 +                port@1 {
 495 +                    reg = <1>;
 496 +                    label = "lan1";
 497 +                    phy-handle = <&external_phy_port1>;
 498 +                };
 499 +
 500 +                port@2 {
 501 +                    reg = <2>;
 502 +                    label = "lan2";
 503 +                    phy-handle = <&external_phy_port2>;
 504 +                };
 505 +
 506 +                port@3 {
 507 +                    reg = <3>;
 508 +                    label = "lan3";
 509 +                    phy-handle = <&external_phy_port3>;
 510 +                };
 511 +
 512 +                port@4 {
 513 +                    reg = <4>;
 514 +                    label = "lan4";
 515 +                    phy-handle = <&external_phy_port4>;
 516 +                };
 517 +
 518 +                port@5 {
 519 +                    reg = <5>;
 520 +                    label = "wan";
 521 +                    phy-handle = <&external_phy_port5>;
 522 +                };
 523 +            };
 524 +        };
 525 +    };
 526 +  - |
 527 +    #include <dt-bindings/gpio/gpio.h>
 528 +
 529 +    mdio {
 530 +        #address-cells = <1>;
 531 +        #size-cells = <0>;
 532 +
 533 +        switch@10 {
 534 +            compatible = "qca,qca8337";
 535 +            #address-cells = <1>;
 536 +            #size-cells = <0>;
 537 +            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 538 +            reg = <0x10>;
 539 +
 540 +            ports {
 541 +                #address-cells = <1>;
 542 +                #size-cells = <0>;
 543 +
 544 +                port@0 {
 545 +                    reg = <0>;
 546 +                    label = "cpu";
 547 +                    ethernet = <&gmac1>;
 548 +                    phy-mode = "rgmii";
 549 +
 550 +                    fixed-link {
 551 +                        speed = <1000>;
 552 +                        full-duplex;
 553 +                    };
 554 +                };
 555 +
 556 +                port@1 {
 557 +                    reg = <1>;
 558 +                    label = "lan1";
 559 +                    phy-mode = "internal";
 560 +                    phy-handle = <&internal_phy_port1>;
 561 +                };
 562 +
 563 +                port@2 {
 564 +                    reg = <2>;
 565 +                    label = "lan2";
 566 +                    phy-mode = "internal";
 567 +                    phy-handle = <&internal_phy_port2>;
 568 +                };
 569 +
 570 +                port@3 {
 571 +                    reg = <3>;
 572 +                    label = "lan3";
 573 +                    phy-mode = "internal";
 574 +                    phy-handle = <&internal_phy_port3>;
 575 +                };
 576 +
 577 +                port@4 {
 578 +                    reg = <4>;
 579 +                    label = "lan4";
 580 +                    phy-mode = "internal";
 581 +                    phy-handle = <&internal_phy_port4>;
 582 +                };
 583 +
 584 +                port@5 {
 585 +                    reg = <5>;
 586 +                    label = "wan";
 587 +                    phy-mode = "internal";
 588 +                    phy-handle = <&internal_phy_port5>;
 589 +                };
 590 +
 591 +                port@6 {
 592 +                    reg = <0>;
 593 +                    label = "cpu";
 594 +                    ethernet = <&gmac1>;
 595 +                    phy-mode = "sgmii";
 596 +
 597 +                    qca,sgmii-rxclk-falling-edge;
 598 +
 599 +                    fixed-link {
 600 +                        speed = <1000>;
 601 +                        full-duplex;
 602 +                    };
 603 +                };
 604 +            };
 605 +
 606 +            mdio {
 607 +                #address-cells = <1>;
 608 +                #size-cells = <0>;
 609 +
 610 +                internal_phy_port1: ethernet-phy@0 {
 611 +                    reg = <0>;
 612 +                };
 613 +
 614 +                internal_phy_port2: ethernet-phy@1 {
 615 +                    reg = <1>;
 616 +                };
 617 +
 618 +                internal_phy_port3: ethernet-phy@2 {
 619 +                    reg = <2>;
 620 +                };
 621 +
 622 +                internal_phy_port4: ethernet-phy@3 {
 623 +                    reg = <3>;
 624 +                };
 625 +
 626 +                internal_phy_port5: ethernet-phy@4 {
 627 +                    reg = <4>;
 628 +                };
 629 +            };
 630 +        };
 631 +    };