target/linux/generic/backport-6.1/801-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch

   1 From 3e8b4d6277fd19d98c817576954dd6a4ff3caa2b Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Mon, 17 Apr 2023 17:17:23 +0200
   4 Subject: [PATCH 1/9] net: dsa: qca8k: move qca8k_port_to_phy() to header
   5
   6 Move qca8k_port_to_phy() to qca8k header as it's useful for future
   7 reference in Switch LEDs module since the same logic is applied to get
   8 the right index of the switch port.
   9 Make it inline as it's simple function that just decrease the port.
  10
  11 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
  14 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17  drivers/net/dsa/qca/qca8k-8xxx.c | 15 ---------------
  18  drivers/net/dsa/qca/qca8k.h      | 14 ++++++++++++++
  19  2 files changed, 14 insertions(+), 15 deletions(-)
  20
  21 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
  22 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
  23 @@ -716,21 +716,6 @@ err_clear_skb:
  24         return ret;
  25  }
  26
  27 -static u32
  28 -qca8k_port_to_phy(int port)
  29 -{
  30 -       /* From Andrew Lunn:
  31 -        * Port 0 has no internal phy.
  32 -        * Port 1 has an internal PHY at MDIO address 0.
  33 -        * Port 2 has an internal PHY at MDIO address 1.
  34 -        * ...
  35 -        * Port 5 has an internal PHY at MDIO address 4.
  36 -        * Port 6 has no internal PHY.
  37 -        */
  38 -
  39 -       return port - 1;
  40 -}
  41 -
  42  static int
  43  qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
  44  {
  45 --- a/drivers/net/dsa/qca/qca8k.h
  46 +++ b/drivers/net/dsa/qca/qca8k.h
  47 @@ -422,6 +422,20 @@ struct qca8k_fdb {
  48         u8 mac[6];
  49  };
  50
  51 +static inline u32 qca8k_port_to_phy(int port)
  52 +{
  53 +       /* From Andrew Lunn:
  54 +        * Port 0 has no internal phy.
  55 +        * Port 1 has an internal PHY at MDIO address 0.
  56 +        * Port 2 has an internal PHY at MDIO address 1.
  57 +        * ...
  58 +        * Port 5 has an internal PHY at MDIO address 4.
  59 +        * Port 6 has no internal PHY.
  60 +        */
  61 +
  62 +       return port - 1;
  63 +}
  64 +
  65  /* Common setup function */
  66  extern const struct qca8k_mib_desc ar8327_mib[];
  67  extern const struct regmap_access_table qca8k_readable_table;