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generic: copy backport, hack, pending patch and config from 6.1 to 6.6
[openwrt/openwrt.git] / target / linux / generic / backport-6.6 / 715-03-v6.2-net-dpaa-Convert-to-phylink.patch
1 From 38e50fc3d43882a43115b4f1ca3eb88255163c5b Mon Sep 17 00:00:00 2001
2 From: Sean Anderson <sean.anderson@seco.com>
3 Date: Mon, 17 Oct 2022 16:22:38 -0400
4 Subject: [PATCH 03/21] net: dpaa: Convert to phylink
5
6 This converts DPAA to phylink. All macs are converted. This should work
7 with no device tree modifications (including those made in this series),
8 except for QSGMII (as noted previously).
9
10 The mEMAC configuration is one of the tricker areas. I have tried to
11 capture all the restrictions across the various models. Most of the time,
12 we assume that if the serdes supports a mode or the phy-interface-mode
13 specifies it, then we support it. The only place we can't do this is
14 (RG)MII, since there's no serdes. In that case, we rely on a (new)
15 devicetree property. There are also several cases where half-duplex is
16 broken. Unfortunately, only a single compatible is used for the MAC, so we
17 have to use the board compatible instead.
18
19 The 10GEC conversion is very straightforward, since it only supports XAUI.
20 There is generally nothing to configure.
21
22 The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
23 don't support configuring the SerDes (though this can be easily added) and
24 we don't have multiple PCSs. From what I can tell, there's nothing
25 different in the driver or documentation between SGMII and 1000BASE-X
26 except for the advertising. Similarly, I couldn't find anything about
27 2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
28 by any in-tree boards. Similarly, despite being mentioned in the driver, I
29 couldn't find any documented SoCs which supported QSGMII. I have left it
30 unimplemented for now.
31
32 Signed-off-by: Sean Anderson <sean.anderson@seco.com>
33 Signed-off-by: David S. Miller <davem@davemloft.net>
34 ---
35 drivers/net/ethernet/freescale/dpaa/Kconfig | 4 +-
36 .../net/ethernet/freescale/dpaa/dpaa_eth.c | 89 +--
37 .../ethernet/freescale/dpaa/dpaa_ethtool.c | 90 +--
38 drivers/net/ethernet/freescale/fman/Kconfig | 1 -
39 .../net/ethernet/freescale/fman/fman_dtsec.c | 458 +++++++--------
40 .../net/ethernet/freescale/fman/fman_mac.h | 10 -
41 .../net/ethernet/freescale/fman/fman_memac.c | 547 +++++++++---------
42 .../net/ethernet/freescale/fman/fman_tgec.c | 131 ++---
43 drivers/net/ethernet/freescale/fman/mac.c | 168 +-----
44 drivers/net/ethernet/freescale/fman/mac.h | 23 +-
45 10 files changed, 612 insertions(+), 909 deletions(-)
46
47 --- a/drivers/net/ethernet/freescale/dpaa/Kconfig
48 +++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
49 @@ -2,8 +2,8 @@
50 menuconfig FSL_DPAA_ETH
51 tristate "DPAA Ethernet"
52 depends on FSL_DPAA && FSL_FMAN
53 - select PHYLIB
54 - select FIXED_PHY
55 + select PHYLINK
56 + select PCS_LYNX
57 help
58 Data Path Acceleration Architecture Ethernet driver,
59 supporting the Freescale QorIQ chips.
60 --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
61 +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
62 @@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_d
63 net_dev->needed_headroom = priv->tx_headroom;
64 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
65
66 - mac_dev->net_dev = net_dev;
67 + /* The rest of the config is filled in by the mac device already */
68 + mac_dev->phylink_config.dev = &net_dev->dev;
69 + mac_dev->phylink_config.type = PHYLINK_NETDEV;
70 mac_dev->update_speed = dpaa_eth_cgr_set_speed;
71 + mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
72 + dev_fwnode(mac_dev->dev),
73 + mac_dev->phy_if,
74 + mac_dev->phylink_ops);
75 + if (IS_ERR(mac_dev->phylink)) {
76 + err = PTR_ERR(mac_dev->phylink);
77 + dev_err_probe(dev, err, "Could not create phylink\n");
78 + return err;
79 + }
80
81 /* start without the RUNNING flag, phylib controls it later */
82 netif_carrier_off(net_dev);
83 @@ -273,6 +284,7 @@ static int dpaa_netdev_init(struct net_d
84 err = register_netdev(net_dev);
85 if (err < 0) {
86 dev_err(dev, "register_netdev() = %d\n", err);
87 + phylink_destroy(mac_dev->phylink);
88 return err;
89 }
90
91 @@ -295,8 +307,7 @@ static int dpaa_stop(struct net_device *
92 */
93 msleep(200);
94
95 - if (mac_dev->phy_dev)
96 - phy_stop(mac_dev->phy_dev);
97 + phylink_stop(mac_dev->phylink);
98 mac_dev->disable(mac_dev->fman_mac);
99
100 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
101 @@ -305,8 +316,7 @@ static int dpaa_stop(struct net_device *
102 err = error;
103 }
104
105 - if (net_dev->phydev)
106 - phy_disconnect(net_dev->phydev);
107 + phylink_disconnect_phy(mac_dev->phylink);
108 net_dev->phydev = NULL;
109
110 msleep(200);
111 @@ -834,10 +844,10 @@ static int dpaa_eth_cgr_init(struct dpaa
112
113 /* Set different thresholds based on the configured MAC speed.
114 * This may turn suboptimal if the MAC is reconfigured at another
115 - * speed, so MACs must call dpaa_eth_cgr_set_speed in their adjust_link
116 + * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
117 * callback.
118 */
119 - if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
120 + if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
121 cs_th = DPAA_CS_THRESHOLD_10G;
122 else
123 cs_th = DPAA_CS_THRESHOLD_1G;
124 @@ -866,7 +876,7 @@ out_error:
125
126 static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
127 {
128 - struct net_device *net_dev = mac_dev->net_dev;
129 + struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
130 struct dpaa_priv *priv = netdev_priv(net_dev);
131 struct qm_mcc_initcgr opts = { };
132 u32 cs_th;
133 @@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct
134 }
135 }
136
137 -static void dpaa_adjust_link(struct net_device *net_dev)
138 -{
139 - struct mac_device *mac_dev;
140 - struct dpaa_priv *priv;
141 -
142 - priv = netdev_priv(net_dev);
143 - mac_dev = priv->mac_dev;
144 - mac_dev->adjust_link(mac_dev);
145 -}
146 -
147 -/* The Aquantia PHYs are capable of performing rate adaptation */
148 -#define PHY_VEND_AQUANTIA 0x03a1b400
149 -#define PHY_VEND_AQUANTIA2 0x31c31c00
150 -
151 -static int dpaa_phy_init(struct net_device *net_dev)
152 -{
153 - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
154 - struct mac_device *mac_dev;
155 - struct phy_device *phy_dev;
156 - struct dpaa_priv *priv;
157 - u32 phy_vendor;
158 -
159 - priv = netdev_priv(net_dev);
160 - mac_dev = priv->mac_dev;
161 -
162 - phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
163 - &dpaa_adjust_link, 0,
164 - mac_dev->phy_if);
165 - if (!phy_dev) {
166 - netif_err(priv, ifup, net_dev, "init_phy() failed\n");
167 - return -ENODEV;
168 - }
169 -
170 - phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10);
171 - /* Unless the PHY is capable of rate adaptation */
172 - if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
173 - (phy_vendor != PHY_VEND_AQUANTIA &&
174 - phy_vendor != PHY_VEND_AQUANTIA2)) {
175 - /* remove any features not supported by the controller */
176 - ethtool_convert_legacy_u32_to_link_mode(mask,
177 - mac_dev->if_support);
178 - linkmode_and(phy_dev->supported, phy_dev->supported, mask);
179 - }
180 -
181 - phy_support_asym_pause(phy_dev);
182 -
183 - mac_dev->phy_dev = phy_dev;
184 - net_dev->phydev = phy_dev;
185 -
186 - return 0;
187 -}
188 -
189 static int dpaa_open(struct net_device *net_dev)
190 {
191 struct mac_device *mac_dev;
192 @@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device *
193 mac_dev = priv->mac_dev;
194 dpaa_eth_napi_enable(priv);
195
196 - err = dpaa_phy_init(net_dev);
197 + err = phylink_of_phy_connect(mac_dev->phylink,
198 + mac_dev->dev->of_node, 0);
199 if (err)
200 goto phy_init_failed;
201
202 @@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device *
203 netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
204 goto mac_start_failed;
205 }
206 - phy_start(priv->mac_dev->phy_dev);
207 + phylink_start(mac_dev->phylink);
208
209 netif_tx_start_all_queues(net_dev);
210
211 @@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device *
212 mac_start_failed:
213 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
214 fman_port_disable(mac_dev->port[i]);
215 + phylink_disconnect_phy(mac_dev->phylink);
216
217 phy_init_failed:
218 dpaa_eth_napi_disable(priv);
219 @@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi
220 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
221 {
222 int ret = -EINVAL;
223 + struct dpaa_priv *priv = netdev_priv(net_dev);
224
225 if (cmd == SIOCGMIIREG) {
226 if (net_dev->phydev)
227 - return phy_mii_ioctl(net_dev->phydev, rq, cmd);
228 + return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
229 + cmd);
230 }
231
232 if (cmd == SIOCSHWTSTAMP)
233 @@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d
234
235 dev_set_drvdata(dev, NULL);
236 unregister_netdev(net_dev);
237 + phylink_destroy(priv->mac_dev->phylink);
238
239 err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
240
241 --- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
242 +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
243 @@ -54,27 +54,19 @@ static char dpaa_stats_global[][ETH_GSTR
244 static int dpaa_get_link_ksettings(struct net_device *net_dev,
245 struct ethtool_link_ksettings *cmd)
246 {
247 - if (!net_dev->phydev)
248 - return 0;
249 + struct dpaa_priv *priv = netdev_priv(net_dev);
250 + struct mac_device *mac_dev = priv->mac_dev;
251
252 - phy_ethtool_ksettings_get(net_dev->phydev, cmd);
253 -
254 - return 0;
255 + return phylink_ethtool_ksettings_get(mac_dev->phylink, cmd);
256 }
257
258 static int dpaa_set_link_ksettings(struct net_device *net_dev,
259 const struct ethtool_link_ksettings *cmd)
260 {
261 - int err;
262 -
263 - if (!net_dev->phydev)
264 - return -ENODEV;
265 + struct dpaa_priv *priv = netdev_priv(net_dev);
266 + struct mac_device *mac_dev = priv->mac_dev;
267
268 - err = phy_ethtool_ksettings_set(net_dev->phydev, cmd);
269 - if (err < 0)
270 - netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", err);
271 -
272 - return err;
273 + return phylink_ethtool_ksettings_set(mac_dev->phylink, cmd);
274 }
275
276 static void dpaa_get_drvinfo(struct net_device *net_dev,
277 @@ -99,80 +91,28 @@ static void dpaa_set_msglevel(struct net
278
279 static int dpaa_nway_reset(struct net_device *net_dev)
280 {
281 - int err;
282 -
283 - if (!net_dev->phydev)
284 - return -ENODEV;
285 + struct dpaa_priv *priv = netdev_priv(net_dev);
286 + struct mac_device *mac_dev = priv->mac_dev;
287
288 - err = 0;
289 - if (net_dev->phydev->autoneg) {
290 - err = phy_start_aneg(net_dev->phydev);
291 - if (err < 0)
292 - netdev_err(net_dev, "phy_start_aneg() = %d\n",
293 - err);
294 - }
295 -
296 - return err;
297 + return phylink_ethtool_nway_reset(mac_dev->phylink);
298 }
299
300 static void dpaa_get_pauseparam(struct net_device *net_dev,
301 struct ethtool_pauseparam *epause)
302 {
303 - struct mac_device *mac_dev;
304 - struct dpaa_priv *priv;
305 -
306 - priv = netdev_priv(net_dev);
307 - mac_dev = priv->mac_dev;
308 -
309 - if (!net_dev->phydev)
310 - return;
311 + struct dpaa_priv *priv = netdev_priv(net_dev);
312 + struct mac_device *mac_dev = priv->mac_dev;
313
314 - epause->autoneg = mac_dev->autoneg_pause;
315 - epause->rx_pause = mac_dev->rx_pause_active;
316 - epause->tx_pause = mac_dev->tx_pause_active;
317 + phylink_ethtool_get_pauseparam(mac_dev->phylink, epause);
318 }
319
320 static int dpaa_set_pauseparam(struct net_device *net_dev,
321 struct ethtool_pauseparam *epause)
322 {
323 - struct mac_device *mac_dev;
324 - struct phy_device *phydev;
325 - bool rx_pause, tx_pause;
326 - struct dpaa_priv *priv;
327 - int err;
328 -
329 - priv = netdev_priv(net_dev);
330 - mac_dev = priv->mac_dev;
331 -
332 - phydev = net_dev->phydev;
333 - if (!phydev) {
334 - netdev_err(net_dev, "phy device not initialized\n");
335 - return -ENODEV;
336 - }
337 -
338 - if (!phy_validate_pause(phydev, epause))
339 - return -EINVAL;
340 -
341 - /* The MAC should know how to handle PAUSE frame autonegotiation before
342 - * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE
343 - * settings.
344 - */
345 - mac_dev->autoneg_pause = !!epause->autoneg;
346 - mac_dev->rx_pause_req = !!epause->rx_pause;
347 - mac_dev->tx_pause_req = !!epause->tx_pause;
348 -
349 - /* Determine the sym/asym advertised PAUSE capabilities from the desired
350 - * rx/tx pause settings.
351 - */
352 -
353 - phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
354 -
355 - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
356 - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
357 - if (err < 0)
358 - netdev_err(net_dev, "set_mac_active_pause() = %d\n", err);
359 + struct dpaa_priv *priv = netdev_priv(net_dev);
360 + struct mac_device *mac_dev = priv->mac_dev;
361
362 - return err;
363 + return phylink_ethtool_set_pauseparam(mac_dev->phylink, epause);
364 }
365
366 static int dpaa_get_sset_count(struct net_device *net_dev, int type)
367 --- a/drivers/net/ethernet/freescale/fman/Kconfig
368 +++ b/drivers/net/ethernet/freescale/fman/Kconfig
369 @@ -3,7 +3,6 @@ config FSL_FMAN
370 tristate "FMan support"
371 depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
372 select GENERIC_ALLOCATOR
373 - select PHYLIB
374 select PHYLINK
375 select PCS
376 select PCS_LYNX
377 --- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
378 +++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
379 @@ -17,6 +17,7 @@
380 #include <linux/crc32.h>
381 #include <linux/of_mdio.h>
382 #include <linux/mii.h>
383 +#include <linux/netdevice.h>
384
385 /* TBI register addresses */
386 #define MII_TBICON 0x11
387 @@ -29,9 +30,6 @@
388 #define TBICON_CLK_SELECT 0x0020 /* Clock select */
389 #define TBICON_MI_MODE 0x0010 /* GMII mode (TBI if not set) */
390
391 -#define TBIANA_SGMII 0x4001
392 -#define TBIANA_1000X 0x01a0
393 -
394 /* Interrupt Mask Register (IMASK) */
395 #define DTSEC_IMASK_BREN 0x80000000
396 #define DTSEC_IMASK_RXCEN 0x40000000
397 @@ -92,9 +90,10 @@
398
399 #define DTSEC_ECNTRL_GMIIM 0x00000040
400 #define DTSEC_ECNTRL_TBIM 0x00000020
401 -#define DTSEC_ECNTRL_SGMIIM 0x00000002
402 #define DTSEC_ECNTRL_RPM 0x00000010
403 #define DTSEC_ECNTRL_R100M 0x00000008
404 +#define DTSEC_ECNTRL_RMM 0x00000004
405 +#define DTSEC_ECNTRL_SGMIIM 0x00000002
406 #define DTSEC_ECNTRL_QSGMIIM 0x00000001
407
408 #define TCTRL_TTSE 0x00000040
409 @@ -318,7 +317,8 @@ struct fman_mac {
410 void *fm;
411 struct fman_rev_info fm_rev_info;
412 bool basex_if;
413 - struct phy_device *tbiphy;
414 + struct mdio_device *tbidev;
415 + struct phylink_pcs pcs;
416 };
417
418 static void set_dflts(struct dtsec_cfg *cfg)
419 @@ -356,56 +356,14 @@ static int init(struct dtsec_regs __iome
420 phy_interface_t iface, u16 iface_speed, u64 addr,
421 u32 exception_mask, u8 tbi_addr)
422 {
423 - bool is_rgmii, is_sgmii, is_qsgmii;
424 enet_addr_t eth_addr;
425 - u32 tmp;
426 + u32 tmp = 0;
427 int i;
428
429 /* Soft reset */
430 iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
431 iowrite32be(0, &regs->maccfg1);
432
433 - /* dtsec_id2 */
434 - tmp = ioread32be(&regs->tsec_id2);
435 -
436 - /* check RGMII support */
437 - if (iface == PHY_INTERFACE_MODE_RGMII ||
438 - iface == PHY_INTERFACE_MODE_RGMII_ID ||
439 - iface == PHY_INTERFACE_MODE_RGMII_RXID ||
440 - iface == PHY_INTERFACE_MODE_RGMII_TXID ||
441 - iface == PHY_INTERFACE_MODE_RMII)
442 - if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
443 - return -EINVAL;
444 -
445 - if (iface == PHY_INTERFACE_MODE_SGMII ||
446 - iface == PHY_INTERFACE_MODE_MII)
447 - if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
448 - return -EINVAL;
449 -
450 - is_rgmii = iface == PHY_INTERFACE_MODE_RGMII ||
451 - iface == PHY_INTERFACE_MODE_RGMII_ID ||
452 - iface == PHY_INTERFACE_MODE_RGMII_RXID ||
453 - iface == PHY_INTERFACE_MODE_RGMII_TXID;
454 - is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
455 - is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
456 -
457 - tmp = 0;
458 - if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
459 - tmp |= DTSEC_ECNTRL_GMIIM;
460 - if (is_sgmii)
461 - tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
462 - if (is_qsgmii)
463 - tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
464 - DTSEC_ECNTRL_QSGMIIM);
465 - if (is_rgmii)
466 - tmp |= DTSEC_ECNTRL_RPM;
467 - if (iface_speed == SPEED_100)
468 - tmp |= DTSEC_ECNTRL_R100M;
469 -
470 - iowrite32be(tmp, &regs->ecntrl);
471 -
472 - tmp = 0;
473 -
474 if (cfg->tx_pause_time)
475 tmp |= cfg->tx_pause_time;
476 if (cfg->tx_pause_time_extd)
477 @@ -446,17 +404,10 @@ static int init(struct dtsec_regs __iome
478
479 tmp = 0;
480
481 - if (iface_speed < SPEED_1000)
482 - tmp |= MACCFG2_NIBBLE_MODE;
483 - else if (iface_speed == SPEED_1000)
484 - tmp |= MACCFG2_BYTE_MODE;
485 -
486 tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
487 MACCFG2_PREAMBLE_LENGTH_MASK;
488 if (cfg->tx_pad_crc)
489 tmp |= MACCFG2_PAD_CRC_EN;
490 - /* Full Duplex */
491 - tmp |= MACCFG2_FULL_DUPLEX;
492 iowrite32be(tmp, &regs->maccfg2);
493
494 tmp = (((cfg->non_back_to_back_ipg1 <<
495 @@ -525,10 +476,6 @@ static void set_bucket(struct dtsec_regs
496
497 static int check_init_parameters(struct fman_mac *dtsec)
498 {
499 - if (dtsec->max_speed >= SPEED_10000) {
500 - pr_err("1G MAC driver supports 1G or lower speeds\n");
501 - return -EINVAL;
502 - }
503 if ((dtsec->dtsec_drv_param)->rx_prepend >
504 MAX_PACKET_ALIGNMENT) {
505 pr_err("packetAlignmentPadding can't be > than %d\n",
506 @@ -630,22 +577,10 @@ static int get_exception_flag(enum fman_
507 return bit_mask;
508 }
509
510 -static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
511 -{
512 - /* Checks if dTSEC driver parameters were initialized */
513 - if (!dtsec_drv_params)
514 - return true;
515 -
516 - return false;
517 -}
518 -
519 static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
520 {
521 struct dtsec_regs __iomem *regs = dtsec->regs;
522
523 - if (is_init_done(dtsec->dtsec_drv_param))
524 - return 0;
525 -
526 return (u16)ioread32be(&regs->maxfrm);
527 }
528
529 @@ -682,6 +617,7 @@ static void dtsec_isr(void *handle)
530 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
531 if (event & DTSEC_IMASK_XFUNEN) {
532 /* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
533 + /* FIXME: This races with the rest of the driver! */
534 if (dtsec->fm_rev_info.major == 2) {
535 u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
536 /* a. Write 0x00E0_0C00 to DTSEC_ID
537 @@ -814,6 +750,43 @@ static void free_init_resources(struct f
538 dtsec->unicast_addr_hash = NULL;
539 }
540
541 +static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs)
542 +{
543 + return container_of(pcs, struct fman_mac, pcs);
544 +}
545 +
546 +static void dtsec_pcs_get_state(struct phylink_pcs *pcs,
547 + struct phylink_link_state *state)
548 +{
549 + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
550 +
551 + phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
552 +}
553 +
554 +static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
555 + phy_interface_t interface,
556 + const unsigned long *advertising,
557 + bool permit_pause_to_mac)
558 +{
559 + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
560 +
561 + return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
562 + advertising);
563 +}
564 +
565 +static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
566 +{
567 + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
568 +
569 + phylink_mii_c22_pcs_an_restart(dtsec->tbidev);
570 +}
571 +
572 +static const struct phylink_pcs_ops dtsec_pcs_ops = {
573 + .pcs_get_state = dtsec_pcs_get_state,
574 + .pcs_config = dtsec_pcs_config,
575 + .pcs_an_restart = dtsec_pcs_an_restart,
576 +};
577 +
578 static void graceful_start(struct fman_mac *dtsec)
579 {
580 struct dtsec_regs __iomem *regs = dtsec->regs;
581 @@ -854,36 +827,11 @@ static void graceful_stop(struct fman_ma
582
583 static int dtsec_enable(struct fman_mac *dtsec)
584 {
585 - struct dtsec_regs __iomem *regs = dtsec->regs;
586 - u32 tmp;
587 -
588 - if (!is_init_done(dtsec->dtsec_drv_param))
589 - return -EINVAL;
590 -
591 - /* Enable */
592 - tmp = ioread32be(&regs->maccfg1);
593 - tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
594 - iowrite32be(tmp, &regs->maccfg1);
595 -
596 - /* Graceful start - clear the graceful Rx/Tx stop bit */
597 - graceful_start(dtsec);
598 -
599 return 0;
600 }
601
602 static void dtsec_disable(struct fman_mac *dtsec)
603 {
604 - struct dtsec_regs __iomem *regs = dtsec->regs;
605 - u32 tmp;
606 -
607 - WARN_ON_ONCE(!is_init_done(dtsec->dtsec_drv_param));
608 -
609 - /* Graceful stop - Assert the graceful Rx/Tx stop bit */
610 - graceful_stop(dtsec);
611 -
612 - tmp = ioread32be(&regs->maccfg1);
613 - tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
614 - iowrite32be(tmp, &regs->maccfg1);
615 }
616
617 static int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
618 @@ -894,11 +842,6 @@ static int dtsec_set_tx_pause_frames(str
619 struct dtsec_regs __iomem *regs = dtsec->regs;
620 u32 ptv = 0;
621
622 - if (!is_init_done(dtsec->dtsec_drv_param))
623 - return -EINVAL;
624 -
625 - graceful_stop(dtsec);
626 -
627 if (pause_time) {
628 /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
629 if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
630 @@ -919,8 +862,6 @@ static int dtsec_set_tx_pause_frames(str
631 iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
632 &regs->maccfg1);
633
634 - graceful_start(dtsec);
635 -
636 return 0;
637 }
638
639 @@ -929,11 +870,6 @@ static int dtsec_accept_rx_pause_frames(
640 struct dtsec_regs __iomem *regs = dtsec->regs;
641 u32 tmp;
642
643 - if (!is_init_done(dtsec->dtsec_drv_param))
644 - return -EINVAL;
645 -
646 - graceful_stop(dtsec);
647 -
648 tmp = ioread32be(&regs->maccfg1);
649 if (en)
650 tmp |= MACCFG1_RX_FLOW;
651 @@ -941,17 +877,125 @@ static int dtsec_accept_rx_pause_frames(
652 tmp &= ~MACCFG1_RX_FLOW;
653 iowrite32be(tmp, &regs->maccfg1);
654
655 + return 0;
656 +}
657 +
658 +static struct phylink_pcs *dtsec_select_pcs(struct phylink_config *config,
659 + phy_interface_t iface)
660 +{
661 + struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
662 +
663 + switch (iface) {
664 + case PHY_INTERFACE_MODE_SGMII:
665 + case PHY_INTERFACE_MODE_1000BASEX:
666 + case PHY_INTERFACE_MODE_2500BASEX:
667 + return &dtsec->pcs;
668 + default:
669 + return NULL;
670 + }
671 +}
672 +
673 +static void dtsec_mac_config(struct phylink_config *config, unsigned int mode,
674 + const struct phylink_link_state *state)
675 +{
676 + struct mac_device *mac_dev = fman_config_to_mac(config);
677 + struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
678 + u32 tmp;
679 +
680 + switch (state->interface) {
681 + case PHY_INTERFACE_MODE_RMII:
682 + tmp = DTSEC_ECNTRL_RMM;
683 + break;
684 + case PHY_INTERFACE_MODE_RGMII:
685 + case PHY_INTERFACE_MODE_RGMII_ID:
686 + case PHY_INTERFACE_MODE_RGMII_RXID:
687 + case PHY_INTERFACE_MODE_RGMII_TXID:
688 + tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
689 + break;
690 + case PHY_INTERFACE_MODE_SGMII:
691 + case PHY_INTERFACE_MODE_1000BASEX:
692 + case PHY_INTERFACE_MODE_2500BASEX:
693 + tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
694 + break;
695 + default:
696 + dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
697 + phy_modes(state->interface));
698 + return;
699 + }
700 +
701 + iowrite32be(tmp, &regs->ecntrl);
702 +}
703 +
704 +static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy,
705 + unsigned int mode, phy_interface_t interface,
706 + int speed, int duplex, bool tx_pause, bool rx_pause)
707 +{
708 + struct mac_device *mac_dev = fman_config_to_mac(config);
709 + struct fman_mac *dtsec = mac_dev->fman_mac;
710 + struct dtsec_regs __iomem *regs = dtsec->regs;
711 + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
712 + FSL_FM_PAUSE_TIME_DISABLE;
713 + u32 tmp;
714 +
715 + dtsec_set_tx_pause_frames(dtsec, 0, pause_time, 0);
716 + dtsec_accept_rx_pause_frames(dtsec, rx_pause);
717 +
718 + tmp = ioread32be(&regs->ecntrl);
719 + if (speed == SPEED_100)
720 + tmp |= DTSEC_ECNTRL_R100M;
721 + else
722 + tmp &= ~DTSEC_ECNTRL_R100M;
723 + iowrite32be(tmp, &regs->ecntrl);
724 +
725 + tmp = ioread32be(&regs->maccfg2);
726 + tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE | MACCFG2_FULL_DUPLEX);
727 + if (speed >= SPEED_1000)
728 + tmp |= MACCFG2_BYTE_MODE;
729 + else
730 + tmp |= MACCFG2_NIBBLE_MODE;
731 +
732 + if (duplex == DUPLEX_FULL)
733 + tmp |= MACCFG2_FULL_DUPLEX;
734 +
735 + iowrite32be(tmp, &regs->maccfg2);
736 +
737 + mac_dev->update_speed(mac_dev, speed);
738 +
739 + /* Enable */
740 + tmp = ioread32be(&regs->maccfg1);
741 + tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
742 + iowrite32be(tmp, &regs->maccfg1);
743 +
744 + /* Graceful start - clear the graceful Rx/Tx stop bit */
745 graceful_start(dtsec);
746 +}
747
748 - return 0;
749 +static void dtsec_link_down(struct phylink_config *config, unsigned int mode,
750 + phy_interface_t interface)
751 +{
752 + struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
753 + struct dtsec_regs __iomem *regs = dtsec->regs;
754 + u32 tmp;
755 +
756 + /* Graceful stop - Assert the graceful Rx/Tx stop bit */
757 + graceful_stop(dtsec);
758 +
759 + tmp = ioread32be(&regs->maccfg1);
760 + tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
761 + iowrite32be(tmp, &regs->maccfg1);
762 }
763
764 +static const struct phylink_mac_ops dtsec_mac_ops = {
765 + .validate = phylink_generic_validate,
766 + .mac_select_pcs = dtsec_select_pcs,
767 + .mac_config = dtsec_mac_config,
768 + .mac_link_up = dtsec_link_up,
769 + .mac_link_down = dtsec_link_down,
770 +};
771 +
772 static int dtsec_modify_mac_address(struct fman_mac *dtsec,
773 const enet_addr_t *enet_addr)
774 {
775 - if (!is_init_done(dtsec->dtsec_drv_param))
776 - return -EINVAL;
777 -
778 graceful_stop(dtsec);
779
780 /* Initialize MAC Station Address registers (1 & 2)
781 @@ -975,9 +1019,6 @@ static int dtsec_add_hash_mac_address(st
782 u32 crc = 0xFFFFFFFF;
783 bool mcast, ghtx;
784
785 - if (!is_init_done(dtsec->dtsec_drv_param))
786 - return -EINVAL;
787 -
788 addr = ENET_ADDR_TO_UINT64(*eth_addr);
789
790 ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
791 @@ -1037,9 +1078,6 @@ static int dtsec_set_allmulti(struct fma
792 u32 tmp;
793 struct dtsec_regs __iomem *regs = dtsec->regs;
794
795 - if (!is_init_done(dtsec->dtsec_drv_param))
796 - return -EINVAL;
797 -
798 tmp = ioread32be(&regs->rctrl);
799 if (enable)
800 tmp |= RCTRL_MPROM;
801 @@ -1056,9 +1094,6 @@ static int dtsec_set_tstamp(struct fman_
802 struct dtsec_regs __iomem *regs = dtsec->regs;
803 u32 rctrl, tctrl;
804
805 - if (!is_init_done(dtsec->dtsec_drv_param))
806 - return -EINVAL;
807 -
808 rctrl = ioread32be(&regs->rctrl);
809 tctrl = ioread32be(&regs->tctrl);
810
811 @@ -1087,9 +1122,6 @@ static int dtsec_del_hash_mac_address(st
812 u32 crc = 0xFFFFFFFF;
813 bool mcast, ghtx;
814
815 - if (!is_init_done(dtsec->dtsec_drv_param))
816 - return -EINVAL;
817 -
818 addr = ENET_ADDR_TO_UINT64(*eth_addr);
819
820 ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
821 @@ -1153,9 +1185,6 @@ static int dtsec_set_promiscuous(struct
822 struct dtsec_regs __iomem *regs = dtsec->regs;
823 u32 tmp;
824
825 - if (!is_init_done(dtsec->dtsec_drv_param))
826 - return -EINVAL;
827 -
828 /* Set unicast promiscuous */
829 tmp = ioread32be(&regs->rctrl);
830 if (new_val)
831 @@ -1177,90 +1206,12 @@ static int dtsec_set_promiscuous(struct
832 return 0;
833 }
834
835 -static int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
836 -{
837 - struct dtsec_regs __iomem *regs = dtsec->regs;
838 - u32 tmp;
839 -
840 - if (!is_init_done(dtsec->dtsec_drv_param))
841 - return -EINVAL;
842 -
843 - graceful_stop(dtsec);
844 -
845 - tmp = ioread32be(&regs->maccfg2);
846 -
847 - /* Full Duplex */
848 - tmp |= MACCFG2_FULL_DUPLEX;
849 -
850 - tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
851 - if (speed < SPEED_1000)
852 - tmp |= MACCFG2_NIBBLE_MODE;
853 - else if (speed == SPEED_1000)
854 - tmp |= MACCFG2_BYTE_MODE;
855 - iowrite32be(tmp, &regs->maccfg2);
856 -
857 - tmp = ioread32be(&regs->ecntrl);
858 - if (speed == SPEED_100)
859 - tmp |= DTSEC_ECNTRL_R100M;
860 - else
861 - tmp &= ~DTSEC_ECNTRL_R100M;
862 - iowrite32be(tmp, &regs->ecntrl);
863 -
864 - graceful_start(dtsec);
865 -
866 - return 0;
867 -}
868 -
869 -static int dtsec_restart_autoneg(struct fman_mac *dtsec)
870 -{
871 - u16 tmp_reg16;
872 -
873 - if (!is_init_done(dtsec->dtsec_drv_param))
874 - return -EINVAL;
875 -
876 - tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
877 -
878 - tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
879 - tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
880 - BMCR_FULLDPLX | BMCR_SPEED1000);
881 -
882 - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
883 -
884 - return 0;
885 -}
886 -
887 -static void adjust_link_dtsec(struct mac_device *mac_dev)
888 -{
889 - struct phy_device *phy_dev = mac_dev->phy_dev;
890 - struct fman_mac *fman_mac;
891 - bool rx_pause, tx_pause;
892 - int err;
893 -
894 - fman_mac = mac_dev->fman_mac;
895 - if (!phy_dev->link) {
896 - dtsec_restart_autoneg(fman_mac);
897 -
898 - return;
899 - }
900 -
901 - dtsec_adjust_link(fman_mac, phy_dev->speed);
902 - mac_dev->update_speed(mac_dev, phy_dev->speed);
903 - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
904 - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
905 - if (err < 0)
906 - dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
907 - err);
908 -}
909 -
910 static int dtsec_set_exception(struct fman_mac *dtsec,
911 enum fman_mac_exceptions exception, bool enable)
912 {
913 struct dtsec_regs __iomem *regs = dtsec->regs;
914 u32 bit_mask = 0;
915
916 - if (!is_init_done(dtsec->dtsec_drv_param))
917 - return -EINVAL;
918 -
919 if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
920 bit_mask = get_exception_flag(exception);
921 if (bit_mask) {
922 @@ -1310,12 +1261,9 @@ static int dtsec_init(struct fman_mac *d
923 {
924 struct dtsec_regs __iomem *regs = dtsec->regs;
925 struct dtsec_cfg *dtsec_drv_param;
926 - u16 max_frm_ln;
927 + u16 max_frm_ln, tbicon;
928 int err;
929
930 - if (is_init_done(dtsec->dtsec_drv_param))
931 - return -EINVAL;
932 -
933 if (DEFAULT_RESET_ON_INIT &&
934 (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
935 pr_err("Can't reset MAC!\n");
936 @@ -1330,38 +1278,19 @@ static int dtsec_init(struct fman_mac *d
937
938 err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
939 dtsec->max_speed, dtsec->addr, dtsec->exceptions,
940 - dtsec->tbiphy->mdio.addr);
941 + dtsec->tbidev->addr);
942 if (err) {
943 free_init_resources(dtsec);
944 pr_err("DTSEC version doesn't support this i/f mode\n");
945 return err;
946 }
947
948 - if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
949 - u16 tmp_reg16;
950 -
951 - /* Configure the TBI PHY Control Register */
952 - tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
953 - phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
954 -
955 - tmp_reg16 = TBICON_CLK_SELECT;
956 - phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
957 -
958 - tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
959 - BMCR_FULLDPLX | BMCR_SPEED1000);
960 - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
961 -
962 - if (dtsec->basex_if)
963 - tmp_reg16 = TBIANA_1000X;
964 - else
965 - tmp_reg16 = TBIANA_SGMII;
966 - phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
967 + /* Configure the TBI PHY Control Register */
968 + tbicon = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
969 + mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
970
971 - tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
972 - BMCR_FULLDPLX | BMCR_SPEED1000);
973 -
974 - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
975 - }
976 + tbicon = TBICON_CLK_SELECT;
977 + mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
978
979 /* Max Frame Length */
980 max_frm_ln = (u16)ioread32be(&regs->maxfrm);
981 @@ -1406,6 +1335,8 @@ static int dtsec_free(struct fman_mac *d
982
983 kfree(dtsec->dtsec_drv_param);
984 dtsec->dtsec_drv_param = NULL;
985 + if (!IS_ERR_OR_NULL(dtsec->tbidev))
986 + put_device(&dtsec->tbidev->dev);
987 kfree(dtsec);
988
989 return 0;
990 @@ -1434,7 +1365,6 @@ static struct fman_mac *dtsec_config(str
991
992 dtsec->regs = mac_dev->vaddr;
993 dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
994 - dtsec->max_speed = params->max_speed;
995 dtsec->phy_if = mac_dev->phy_if;
996 dtsec->mac_id = params->mac_id;
997 dtsec->exceptions = (DTSEC_IMASK_BREN |
998 @@ -1457,7 +1387,6 @@ static struct fman_mac *dtsec_config(str
999 dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;
1000
1001 dtsec->fm = params->fm;
1002 - dtsec->basex_if = params->basex_if;
1003
1004 /* Save FMan revision */
1005 fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
1006 @@ -1476,18 +1405,18 @@ int dtsec_initialization(struct mac_devi
1007 int err;
1008 struct fman_mac *dtsec;
1009 struct device_node *phy_node;
1010 + unsigned long capabilities;
1011 + unsigned long *supported;
1012
1013 + mac_dev->phylink_ops = &dtsec_mac_ops;
1014 mac_dev->set_promisc = dtsec_set_promiscuous;
1015 mac_dev->change_addr = dtsec_modify_mac_address;
1016 mac_dev->add_hash_mac_addr = dtsec_add_hash_mac_address;
1017 mac_dev->remove_hash_mac_addr = dtsec_del_hash_mac_address;
1018 - mac_dev->set_tx_pause = dtsec_set_tx_pause_frames;
1019 - mac_dev->set_rx_pause = dtsec_accept_rx_pause_frames;
1020 mac_dev->set_exception = dtsec_set_exception;
1021 mac_dev->set_allmulti = dtsec_set_allmulti;
1022 mac_dev->set_tstamp = dtsec_set_tstamp;
1023 mac_dev->set_multi = fman_set_multi;
1024 - mac_dev->adjust_link = adjust_link_dtsec;
1025 mac_dev->enable = dtsec_enable;
1026 mac_dev->disable = dtsec_disable;
1027
1028 @@ -1502,19 +1431,56 @@ int dtsec_initialization(struct mac_devi
1029 dtsec->dtsec_drv_param->tx_pad_crc = true;
1030
1031 phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
1032 - if (!phy_node) {
1033 - pr_err("TBI PHY node is not available\n");
1034 + if (!phy_node || of_device_is_available(phy_node)) {
1035 + of_node_put(phy_node);
1036 err = -EINVAL;
1037 + dev_err_probe(mac_dev->dev, err,
1038 + "TBI PCS node is not available\n");
1039 goto _return_fm_mac_free;
1040 }
1041
1042 - dtsec->tbiphy = of_phy_find_device(phy_node);
1043 - if (!dtsec->tbiphy) {
1044 - pr_err("of_phy_find_device (TBI PHY) failed\n");
1045 - err = -EINVAL;
1046 + dtsec->tbidev = of_mdio_find_device(phy_node);
1047 + of_node_put(phy_node);
1048 + if (!dtsec->tbidev) {
1049 + err = -EPROBE_DEFER;
1050 + dev_err_probe(mac_dev->dev, err,
1051 + "could not find mdiodev for PCS\n");
1052 goto _return_fm_mac_free;
1053 }
1054 - put_device(&dtsec->tbiphy->mdio.dev);
1055 + dtsec->pcs.ops = &dtsec_pcs_ops;
1056 + dtsec->pcs.poll = true;
1057 +
1058 + supported = mac_dev->phylink_config.supported_interfaces;
1059 +
1060 + /* FIXME: Can we use DTSEC_ID2_INT_FULL_OFF to determine if these are
1061 + * supported? If not, we can determine support via the phy if SerDes
1062 + * support is added.
1063 + */
1064 + if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII ||
1065 + mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) {
1066 + __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
1067 + __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
1068 + } else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) {
1069 + __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
1070 + }
1071 +
1072 + if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) {
1073 + phy_interface_set_rgmii(supported);
1074 +
1075 + /* DTSEC_ID2_INT_REDUCED_OFF indicates that the dTSEC supports
1076 + * RMII and RGMII. However, the only SoCs which support RMII
1077 + * are the P1017 and P1023. Avoid advertising this mode on
1078 + * other SoCs. This is a bit of a moot point, since there's no
1079 + * in-tree support for ethernet on these platforms...
1080 + */
1081 + if (of_machine_is_compatible("fsl,P1023") ||
1082 + of_machine_is_compatible("fsl,P1023RDB"))
1083 + __set_bit(PHY_INTERFACE_MODE_RMII, supported);
1084 + }
1085 +
1086 + capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1087 + capabilities |= MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
1088 + mac_dev->phylink_config.mac_capabilities = capabilities;
1089
1090 err = dtsec_init(dtsec);
1091 if (err < 0)
1092 --- a/drivers/net/ethernet/freescale/fman/fman_mac.h
1093 +++ b/drivers/net/ethernet/freescale/fman/fman_mac.h
1094 @@ -170,20 +170,10 @@ struct fman_mac_params {
1095 * 0 - FM_MAX_NUM_OF_10G_MACS
1096 */
1097 u8 mac_id;
1098 - /* Note that the speed should indicate the maximum rate that
1099 - * this MAC should support rather than the actual speed;
1100 - */
1101 - u16 max_speed;
1102 /* A handle to the FM object this port related to */
1103 void *fm;
1104 fman_mac_exception_cb *event_cb; /* MDIO Events Callback Routine */
1105 fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
1106 - /* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
1107 - * and phy or backplane; Note: 1000BaseX auto-negotiation relates only
1108 - * to interface between MAC and phy/backplane, SGMII phy can still
1109 - * synchronize with far-end phy at 10Mbps, 100Mbps or 1000Mbps
1110 - */
1111 - bool basex_if;
1112 };
1113
1114 struct eth_hash_t {
1115 --- a/drivers/net/ethernet/freescale/fman/fman_memac.c
1116 +++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
1117 @@ -278,9 +278,6 @@ struct fman_mac {
1118 struct memac_regs __iomem *regs;
1119 /* MAC address of device */
1120 u64 addr;
1121 - /* Ethernet physical interface */
1122 - phy_interface_t phy_if;
1123 - u16 max_speed;
1124 struct mac_device *dev_id; /* device cookie used by the exception cbs */
1125 fman_mac_exception_cb *exception_cb;
1126 fman_mac_exception_cb *event_cb;
1127 @@ -293,12 +290,12 @@ struct fman_mac {
1128 struct memac_cfg *memac_drv_param;
1129 void *fm;
1130 struct fman_rev_info fm_rev_info;
1131 - bool basex_if;
1132 struct phy *serdes;
1133 struct phylink_pcs *sgmii_pcs;
1134 struct phylink_pcs *qsgmii_pcs;
1135 struct phylink_pcs *xfi_pcs;
1136 bool allmulti_enabled;
1137 + bool rgmii_no_half_duplex;
1138 };
1139
1140 static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
1141 @@ -356,7 +353,6 @@ static void set_exception(struct memac_r
1142 }
1143
1144 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
1145 - phy_interface_t phy_if, u16 speed, bool slow_10g_if,
1146 u32 exceptions)
1147 {
1148 u32 tmp;
1149 @@ -384,41 +380,6 @@ static int init(struct memac_regs __iome
1150 iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
1151 iowrite32be((u32)0, &regs->pause_thresh[0]);
1152
1153 - /* IF_MODE */
1154 - tmp = 0;
1155 - switch (phy_if) {
1156 - case PHY_INTERFACE_MODE_XGMII:
1157 - tmp |= IF_MODE_10G;
1158 - break;
1159 - case PHY_INTERFACE_MODE_MII:
1160 - tmp |= IF_MODE_MII;
1161 - break;
1162 - default:
1163 - tmp |= IF_MODE_GMII;
1164 - if (phy_if == PHY_INTERFACE_MODE_RGMII ||
1165 - phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
1166 - phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
1167 - phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
1168 - tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
1169 - }
1170 - iowrite32be(tmp, &regs->if_mode);
1171 -
1172 - /* TX_FIFO_SECTIONS */
1173 - tmp = 0;
1174 - if (phy_if == PHY_INTERFACE_MODE_XGMII) {
1175 - if (slow_10g_if) {
1176 - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
1177 - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
1178 - } else {
1179 - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
1180 - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
1181 - }
1182 - } else {
1183 - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
1184 - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
1185 - }
1186 - iowrite32be(tmp, &regs->tx_fifo_sections);
1187 -
1188 /* clear all pending events and set-up interrupts */
1189 iowrite32be(0xffffffff, &regs->ievent);
1190 set_exception(regs, exceptions, true);
1191 @@ -458,24 +419,6 @@ static u32 get_mac_addr_hash_code(u64 et
1192 return xor_val;
1193 }
1194
1195 -static void setup_sgmii_internal(struct fman_mac *memac,
1196 - struct phylink_pcs *pcs,
1197 - struct fixed_phy_status *fixed_link)
1198 -{
1199 - __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
1200 - phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
1201 - PHY_INTERFACE_MODE_SGMII;
1202 - unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
1203 -
1204 - linkmode_set_pause(advertising, true, true);
1205 - pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
1206 - if (fixed_link)
1207 - pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
1208 - fixed_link->duplex);
1209 - else
1210 - pcs->ops->pcs_an_restart(pcs);
1211 -}
1212 -
1213 static int check_init_parameters(struct fman_mac *memac)
1214 {
1215 if (!memac->exception_cb) {
1216 @@ -581,41 +524,31 @@ static void free_init_resources(struct f
1217 memac->unicast_addr_hash = NULL;
1218 }
1219
1220 -static bool is_init_done(struct memac_cfg *memac_drv_params)
1221 -{
1222 - /* Checks if mEMAC driver parameters were initialized */
1223 - if (!memac_drv_params)
1224 - return true;
1225 -
1226 - return false;
1227 -}
1228 -
1229 static int memac_enable(struct fman_mac *memac)
1230 {
1231 - struct memac_regs __iomem *regs = memac->regs;
1232 - u32 tmp;
1233 + int ret;
1234
1235 - if (!is_init_done(memac->memac_drv_param))
1236 - return -EINVAL;
1237 + ret = phy_init(memac->serdes);
1238 + if (ret) {
1239 + dev_err(memac->dev_id->dev,
1240 + "could not initialize serdes: %pe\n", ERR_PTR(ret));
1241 + return ret;
1242 + }
1243
1244 - tmp = ioread32be(&regs->command_config);
1245 - tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
1246 - iowrite32be(tmp, &regs->command_config);
1247 + ret = phy_power_on(memac->serdes);
1248 + if (ret) {
1249 + dev_err(memac->dev_id->dev,
1250 + "could not power on serdes: %pe\n", ERR_PTR(ret));
1251 + phy_exit(memac->serdes);
1252 + }
1253
1254 - return 0;
1255 + return ret;
1256 }
1257
1258 static void memac_disable(struct fman_mac *memac)
1259 -
1260 {
1261 - struct memac_regs __iomem *regs = memac->regs;
1262 - u32 tmp;
1263 -
1264 - WARN_ON_ONCE(!is_init_done(memac->memac_drv_param));
1265 -
1266 - tmp = ioread32be(&regs->command_config);
1267 - tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
1268 - iowrite32be(tmp, &regs->command_config);
1269 + phy_power_off(memac->serdes);
1270 + phy_exit(memac->serdes);
1271 }
1272
1273 static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
1274 @@ -623,9 +556,6 @@ static int memac_set_promiscuous(struct
1275 struct memac_regs __iomem *regs = memac->regs;
1276 u32 tmp;
1277
1278 - if (!is_init_done(memac->memac_drv_param))
1279 - return -EINVAL;
1280 -
1281 tmp = ioread32be(&regs->command_config);
1282 if (new_val)
1283 tmp |= CMD_CFG_PROMIS_EN;
1284 @@ -637,73 +567,12 @@ static int memac_set_promiscuous(struct
1285 return 0;
1286 }
1287
1288 -static int memac_adjust_link(struct fman_mac *memac, u16 speed)
1289 -{
1290 - struct memac_regs __iomem *regs = memac->regs;
1291 - u32 tmp;
1292 -
1293 - if (!is_init_done(memac->memac_drv_param))
1294 - return -EINVAL;
1295 -
1296 - tmp = ioread32be(&regs->if_mode);
1297 -
1298 - /* Set full duplex */
1299 - tmp &= ~IF_MODE_HD;
1300 -
1301 - if (phy_interface_mode_is_rgmii(memac->phy_if)) {
1302 - /* Configure RGMII in manual mode */
1303 - tmp &= ~IF_MODE_RGMII_AUTO;
1304 - tmp &= ~IF_MODE_RGMII_SP_MASK;
1305 - /* Full duplex */
1306 - tmp |= IF_MODE_RGMII_FD;
1307 -
1308 - switch (speed) {
1309 - case SPEED_1000:
1310 - tmp |= IF_MODE_RGMII_1000;
1311 - break;
1312 - case SPEED_100:
1313 - tmp |= IF_MODE_RGMII_100;
1314 - break;
1315 - case SPEED_10:
1316 - tmp |= IF_MODE_RGMII_10;
1317 - break;
1318 - default:
1319 - break;
1320 - }
1321 - }
1322 -
1323 - iowrite32be(tmp, &regs->if_mode);
1324 -
1325 - return 0;
1326 -}
1327 -
1328 -static void adjust_link_memac(struct mac_device *mac_dev)
1329 -{
1330 - struct phy_device *phy_dev = mac_dev->phy_dev;
1331 - struct fman_mac *fman_mac;
1332 - bool rx_pause, tx_pause;
1333 - int err;
1334 -
1335 - fman_mac = mac_dev->fman_mac;
1336 - memac_adjust_link(fman_mac, phy_dev->speed);
1337 - mac_dev->update_speed(mac_dev, phy_dev->speed);
1338 -
1339 - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
1340 - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
1341 - if (err < 0)
1342 - dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
1343 - err);
1344 -}
1345 -
1346 static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
1347 u16 pause_time, u16 thresh_time)
1348 {
1349 struct memac_regs __iomem *regs = memac->regs;
1350 u32 tmp;
1351
1352 - if (!is_init_done(memac->memac_drv_param))
1353 - return -EINVAL;
1354 -
1355 tmp = ioread32be(&regs->tx_fifo_sections);
1356
1357 GET_TX_EMPTY_DEFAULT_VALUE(tmp);
1358 @@ -738,9 +607,6 @@ static int memac_accept_rx_pause_frames(
1359 struct memac_regs __iomem *regs = memac->regs;
1360 u32 tmp;
1361
1362 - if (!is_init_done(memac->memac_drv_param))
1363 - return -EINVAL;
1364 -
1365 tmp = ioread32be(&regs->command_config);
1366 if (en)
1367 tmp &= ~CMD_CFG_PAUSE_IGNORE;
1368 @@ -752,12 +618,175 @@ static int memac_accept_rx_pause_frames(
1369 return 0;
1370 }
1371
1372 +static void memac_validate(struct phylink_config *config,
1373 + unsigned long *supported,
1374 + struct phylink_link_state *state)
1375 +{
1376 + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
1377 + unsigned long caps = config->mac_capabilities;
1378 +
1379 + if (phy_interface_mode_is_rgmii(state->interface) &&
1380 + memac->rgmii_no_half_duplex)
1381 + caps &= ~(MAC_10HD | MAC_100HD);
1382 +
1383 + phylink_validate_mask_caps(supported, state, caps);
1384 +}
1385 +
1386 +/**
1387 + * memac_if_mode() - Convert an interface mode into an IF_MODE config
1388 + * @interface: A phy interface mode
1389 + *
1390 + * Return: A configuration word, suitable for programming into the lower bits
1391 + * of %IF_MODE.
1392 + */
1393 +static u32 memac_if_mode(phy_interface_t interface)
1394 +{
1395 + switch (interface) {
1396 + case PHY_INTERFACE_MODE_MII:
1397 + return IF_MODE_MII;
1398 + case PHY_INTERFACE_MODE_RGMII:
1399 + case PHY_INTERFACE_MODE_RGMII_ID:
1400 + case PHY_INTERFACE_MODE_RGMII_RXID:
1401 + case PHY_INTERFACE_MODE_RGMII_TXID:
1402 + return IF_MODE_GMII | IF_MODE_RGMII;
1403 + case PHY_INTERFACE_MODE_SGMII:
1404 + case PHY_INTERFACE_MODE_1000BASEX:
1405 + case PHY_INTERFACE_MODE_QSGMII:
1406 + return IF_MODE_GMII;
1407 + case PHY_INTERFACE_MODE_10GBASER:
1408 + return IF_MODE_10G;
1409 + default:
1410 + WARN_ON_ONCE(1);
1411 + return 0;
1412 + }
1413 +}
1414 +
1415 +static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
1416 + phy_interface_t iface)
1417 +{
1418 + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
1419 +
1420 + switch (iface) {
1421 + case PHY_INTERFACE_MODE_SGMII:
1422 + case PHY_INTERFACE_MODE_1000BASEX:
1423 + return memac->sgmii_pcs;
1424 + case PHY_INTERFACE_MODE_QSGMII:
1425 + return memac->qsgmii_pcs;
1426 + case PHY_INTERFACE_MODE_10GBASER:
1427 + return memac->xfi_pcs;
1428 + default:
1429 + return NULL;
1430 + }
1431 +}
1432 +
1433 +static int memac_prepare(struct phylink_config *config, unsigned int mode,
1434 + phy_interface_t iface)
1435 +{
1436 + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
1437 +
1438 + switch (iface) {
1439 + case PHY_INTERFACE_MODE_SGMII:
1440 + case PHY_INTERFACE_MODE_1000BASEX:
1441 + case PHY_INTERFACE_MODE_QSGMII:
1442 + case PHY_INTERFACE_MODE_10GBASER:
1443 + return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
1444 + iface);
1445 + default:
1446 + return 0;
1447 + }
1448 +}
1449 +
1450 +static void memac_mac_config(struct phylink_config *config, unsigned int mode,
1451 + const struct phylink_link_state *state)
1452 +{
1453 + struct mac_device *mac_dev = fman_config_to_mac(config);
1454 + struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
1455 + u32 tmp = ioread32be(&regs->if_mode);
1456 +
1457 + tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
1458 + tmp |= memac_if_mode(state->interface);
1459 + if (phylink_autoneg_inband(mode))
1460 + tmp |= IF_MODE_RGMII_AUTO;
1461 + iowrite32be(tmp, &regs->if_mode);
1462 +}
1463 +
1464 +static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
1465 + unsigned int mode, phy_interface_t interface,
1466 + int speed, int duplex, bool tx_pause, bool rx_pause)
1467 +{
1468 + struct mac_device *mac_dev = fman_config_to_mac(config);
1469 + struct fman_mac *memac = mac_dev->fman_mac;
1470 + struct memac_regs __iomem *regs = memac->regs;
1471 + u32 tmp = memac_if_mode(interface);
1472 + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
1473 + FSL_FM_PAUSE_TIME_DISABLE;
1474 +
1475 + memac_set_tx_pause_frames(memac, 0, pause_time, 0);
1476 + memac_accept_rx_pause_frames(memac, rx_pause);
1477 +
1478 + if (duplex == DUPLEX_HALF)
1479 + tmp |= IF_MODE_HD;
1480 +
1481 + switch (speed) {
1482 + case SPEED_1000:
1483 + tmp |= IF_MODE_RGMII_1000;
1484 + break;
1485 + case SPEED_100:
1486 + tmp |= IF_MODE_RGMII_100;
1487 + break;
1488 + case SPEED_10:
1489 + tmp |= IF_MODE_RGMII_10;
1490 + break;
1491 + }
1492 + iowrite32be(tmp, &regs->if_mode);
1493 +
1494 + /* TODO: EEE? */
1495 +
1496 + if (speed == SPEED_10000) {
1497 + if (memac->fm_rev_info.major == 6 &&
1498 + memac->fm_rev_info.minor == 4)
1499 + tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
1500 + else
1501 + tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
1502 + tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
1503 + } else {
1504 + tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
1505 + TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
1506 + }
1507 + iowrite32be(tmp, &regs->tx_fifo_sections);
1508 +
1509 + mac_dev->update_speed(mac_dev, speed);
1510 +
1511 + tmp = ioread32be(&regs->command_config);
1512 + tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
1513 + iowrite32be(tmp, &regs->command_config);
1514 +}
1515 +
1516 +static void memac_link_down(struct phylink_config *config, unsigned int mode,
1517 + phy_interface_t interface)
1518 +{
1519 + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
1520 + struct memac_regs __iomem *regs = memac->regs;
1521 + u32 tmp;
1522 +
1523 + /* TODO: graceful */
1524 + tmp = ioread32be(&regs->command_config);
1525 + tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
1526 + iowrite32be(tmp, &regs->command_config);
1527 +}
1528 +
1529 +static const struct phylink_mac_ops memac_mac_ops = {
1530 + .validate = memac_validate,
1531 + .mac_select_pcs = memac_select_pcs,
1532 + .mac_prepare = memac_prepare,
1533 + .mac_config = memac_mac_config,
1534 + .mac_link_up = memac_link_up,
1535 + .mac_link_down = memac_link_down,
1536 +};
1537 +
1538 static int memac_modify_mac_address(struct fman_mac *memac,
1539 const enet_addr_t *enet_addr)
1540 {
1541 - if (!is_init_done(memac->memac_drv_param))
1542 - return -EINVAL;
1543 -
1544 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
1545
1546 return 0;
1547 @@ -771,9 +800,6 @@ static int memac_add_hash_mac_address(st
1548 u32 hash;
1549 u64 addr;
1550
1551 - if (!is_init_done(memac->memac_drv_param))
1552 - return -EINVAL;
1553 -
1554 addr = ENET_ADDR_TO_UINT64(*eth_addr);
1555
1556 if (!(addr & GROUP_ADDRESS)) {
1557 @@ -802,9 +828,6 @@ static int memac_set_allmulti(struct fma
1558 u32 entry;
1559 struct memac_regs __iomem *regs = memac->regs;
1560
1561 - if (!is_init_done(memac->memac_drv_param))
1562 - return -EINVAL;
1563 -
1564 if (enable) {
1565 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
1566 iowrite32be(entry | HASH_CTRL_MCAST_EN,
1567 @@ -834,9 +857,6 @@ static int memac_del_hash_mac_address(st
1568 u32 hash;
1569 u64 addr;
1570
1571 - if (!is_init_done(memac->memac_drv_param))
1572 - return -EINVAL;
1573 -
1574 addr = ENET_ADDR_TO_UINT64(*eth_addr);
1575
1576 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
1577 @@ -864,9 +884,6 @@ static int memac_set_exception(struct fm
1578 {
1579 u32 bit_mask = 0;
1580
1581 - if (!is_init_done(memac->memac_drv_param))
1582 - return -EINVAL;
1583 -
1584 bit_mask = get_exception_flag(exception);
1585 if (bit_mask) {
1586 if (enable)
1587 @@ -886,23 +903,15 @@ static int memac_init(struct fman_mac *m
1588 {
1589 struct memac_cfg *memac_drv_param;
1590 enet_addr_t eth_addr;
1591 - bool slow_10g_if = false;
1592 - struct fixed_phy_status *fixed_link = NULL;
1593 int err;
1594 u32 reg32 = 0;
1595
1596 - if (is_init_done(memac->memac_drv_param))
1597 - return -EINVAL;
1598 -
1599 err = check_init_parameters(memac);
1600 if (err)
1601 return err;
1602
1603 memac_drv_param = memac->memac_drv_param;
1604
1605 - if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
1606 - slow_10g_if = true;
1607 -
1608 /* First, reset the MAC if desired. */
1609 if (memac_drv_param->reset_on_init) {
1610 err = reset(memac->regs);
1611 @@ -918,10 +927,7 @@ static int memac_init(struct fman_mac *m
1612 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
1613 }
1614
1615 - fixed_link = memac_drv_param->fixed_link;
1616 -
1617 - init(memac->regs, memac->memac_drv_param, memac->phy_if,
1618 - memac->max_speed, slow_10g_if, memac->exceptions);
1619 + init(memac->regs, memac->memac_drv_param, memac->exceptions);
1620
1621 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
1622 * Exists only in FMan 6.0 and 6.3.
1623 @@ -937,11 +943,6 @@ static int memac_init(struct fman_mac *m
1624 iowrite32be(reg32, &memac->regs->command_config);
1625 }
1626
1627 - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
1628 - setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
1629 - else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
1630 - setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
1631 -
1632 /* Max Frame Length */
1633 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
1634 memac_drv_param->max_frame_length);
1635 @@ -970,9 +971,6 @@ static int memac_init(struct fman_mac *m
1636 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1637 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
1638
1639 - kfree(memac_drv_param);
1640 - memac->memac_drv_param = NULL;
1641 -
1642 return 0;
1643 }
1644
1645 @@ -995,7 +993,6 @@ static int memac_free(struct fman_mac *m
1646 pcs_put(memac->sgmii_pcs);
1647 pcs_put(memac->qsgmii_pcs);
1648 pcs_put(memac->xfi_pcs);
1649 -
1650 kfree(memac->memac_drv_param);
1651 kfree(memac);
1652
1653 @@ -1028,8 +1025,6 @@ static struct fman_mac *memac_config(str
1654 memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
1655
1656 memac->regs = mac_dev->vaddr;
1657 - memac->max_speed = params->max_speed;
1658 - memac->phy_if = mac_dev->phy_if;
1659 memac->mac_id = params->mac_id;
1660 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1661 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1662 @@ -1037,7 +1032,6 @@ static struct fman_mac *memac_config(str
1663 memac->event_cb = params->event_cb;
1664 memac->dev_id = mac_dev;
1665 memac->fm = params->fm;
1666 - memac->basex_if = params->basex_if;
1667
1668 /* Save FMan revision */
1669 fman_get_revision(memac->fm, &memac->fm_rev_info);
1670 @@ -1064,37 +1058,44 @@ static struct phylink_pcs *memac_pcs_cre
1671 return pcs;
1672 }
1673
1674 +static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
1675 +{
1676 + /* If there's no serdes device, assume that it's been configured for
1677 + * whatever the default interface mode is.
1678 + */
1679 + if (!mac_dev->fman_mac->serdes)
1680 + return mac_dev->phy_if == iface;
1681 + /* Otherwise, ask the serdes */
1682 + return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
1683 + iface, NULL);
1684 +}
1685 +
1686 int memac_initialization(struct mac_device *mac_dev,
1687 struct device_node *mac_node,
1688 struct fman_mac_params *params)
1689 {
1690 int err;
1691 + struct device_node *fixed;
1692 struct phylink_pcs *pcs;
1693 - struct fixed_phy_status *fixed_link;
1694 struct fman_mac *memac;
1695 + unsigned long capabilities;
1696 + unsigned long *supported;
1697
1698 + mac_dev->phylink_ops = &memac_mac_ops;
1699 mac_dev->set_promisc = memac_set_promiscuous;
1700 mac_dev->change_addr = memac_modify_mac_address;
1701 mac_dev->add_hash_mac_addr = memac_add_hash_mac_address;
1702 mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address;
1703 - mac_dev->set_tx_pause = memac_set_tx_pause_frames;
1704 - mac_dev->set_rx_pause = memac_accept_rx_pause_frames;
1705 mac_dev->set_exception = memac_set_exception;
1706 mac_dev->set_allmulti = memac_set_allmulti;
1707 mac_dev->set_tstamp = memac_set_tstamp;
1708 mac_dev->set_multi = fman_set_multi;
1709 - mac_dev->adjust_link = adjust_link_memac;
1710 mac_dev->enable = memac_enable;
1711 mac_dev->disable = memac_disable;
1712
1713 - if (params->max_speed == SPEED_10000)
1714 - mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII;
1715 -
1716 mac_dev->fman_mac = memac_config(mac_dev, params);
1717 - if (!mac_dev->fman_mac) {
1718 - err = -EINVAL;
1719 - goto _return;
1720 - }
1721 + if (!mac_dev->fman_mac)
1722 + return -EINVAL;
1723
1724 memac = mac_dev->fman_mac;
1725 memac->memac_drv_param->max_frame_length = fman_get_max_frm();
1726 @@ -1136,9 +1137,9 @@ int memac_initialization(struct mac_devi
1727 else
1728 pcs = memac_pcs_create(mac_node, err);
1729
1730 - if (!pcs) {
1731 - dev_err(mac_dev->dev, "missing pcs\n");
1732 - err = -ENOENT;
1733 + if (IS_ERR(pcs)) {
1734 + err = PTR_ERR(pcs);
1735 + dev_err_probe(mac_dev->dev, err, "missing pcs\n");
1736 goto _return_fm_mac_free;
1737 }
1738
1739 @@ -1159,84 +1160,100 @@ int memac_initialization(struct mac_devi
1740 } else if (IS_ERR(memac->serdes)) {
1741 dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
1742 goto _return_fm_mac_free;
1743 - } else {
1744 - err = phy_init(memac->serdes);
1745 - if (err) {
1746 - dev_err_probe(mac_dev->dev, err,
1747 - "could not initialize serdes\n");
1748 - goto _return_fm_mac_free;
1749 - }
1750 -
1751 - err = phy_power_on(memac->serdes);
1752 - if (err) {
1753 - dev_err_probe(mac_dev->dev, err,
1754 - "could not power on serdes\n");
1755 - goto _return_phy_exit;
1756 - }
1757 -
1758 - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
1759 - memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
1760 - memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
1761 - memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
1762 - memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
1763 - err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
1764 - memac->phy_if);
1765 - if (err) {
1766 - dev_err_probe(mac_dev->dev, err,
1767 - "could not set serdes mode to %s\n",
1768 - phy_modes(memac->phy_if));
1769 - goto _return_phy_power_off;
1770 - }
1771 - }
1772 }
1773
1774 - if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
1775 - struct phy_device *phy;
1776 -
1777 - err = of_phy_register_fixed_link(mac_node);
1778 - if (err)
1779 - goto _return_phy_power_off;
1780 -
1781 - fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
1782 - if (!fixed_link) {
1783 - err = -ENOMEM;
1784 - goto _return_phy_power_off;
1785 - }
1786 + /* The internal connection to the serdes is XGMII, but this isn't
1787 + * really correct for the phy mode (which is the external connection).
1788 + * However, this is how all older device trees say that they want
1789 + * 10GBASE-R (aka XFI), so just convert it for them.
1790 + */
1791 + if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
1792 + mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
1793
1794 - mac_dev->phy_node = of_node_get(mac_node);
1795 - phy = of_phy_find_device(mac_dev->phy_node);
1796 - if (!phy) {
1797 - err = -EINVAL;
1798 - of_node_put(mac_dev->phy_node);
1799 - goto _return_fixed_link_free;
1800 - }
1801 + /* TODO: The following interface modes are supported by (some) hardware
1802 + * but not by this driver:
1803 + * - 1000BASE-KX
1804 + * - 10GBASE-KR
1805 + * - XAUI/HiGig
1806 + */
1807 + supported = mac_dev->phylink_config.supported_interfaces;
1808
1809 - fixed_link->link = phy->link;
1810 - fixed_link->speed = phy->speed;
1811 - fixed_link->duplex = phy->duplex;
1812 - fixed_link->pause = phy->pause;
1813 - fixed_link->asym_pause = phy->asym_pause;
1814 + /* Note that half duplex is only supported on 10/100M interfaces. */
1815
1816 - put_device(&phy->mdio.dev);
1817 - memac->memac_drv_param->fixed_link = fixed_link;
1818 + if (memac->sgmii_pcs &&
1819 + (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
1820 + memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
1821 + __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
1822 + __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
1823 + }
1824 +
1825 + if (memac->sgmii_pcs &&
1826 + memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
1827 + __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
1828 +
1829 + if (memac->qsgmii_pcs &&
1830 + memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
1831 + __set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
1832 + else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
1833 + dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
1834 +
1835 + if (memac->xfi_pcs &&
1836 + memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
1837 + __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
1838 + } else {
1839 + /* From what I can tell, no 10g macs support RGMII. */
1840 + phy_interface_set_rgmii(supported);
1841 + __set_bit(PHY_INTERFACE_MODE_MII, supported);
1842 }
1843
1844 + capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
1845 + capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
1846 +
1847 + /* These SoCs don't support half duplex at all; there's no different
1848 + * FMan version or compatible, so we just have to check the machine
1849 + * compatible instead
1850 + */
1851 + if (of_machine_is_compatible("fsl,ls1043a") ||
1852 + of_machine_is_compatible("fsl,ls1046a") ||
1853 + of_machine_is_compatible("fsl,B4QDS"))
1854 + capabilities &= ~(MAC_10HD | MAC_100HD);
1855 +
1856 + mac_dev->phylink_config.mac_capabilities = capabilities;
1857 +
1858 + /* The T2080 and T4240 don't support half duplex RGMII. There is no
1859 + * other way to identify these SoCs, so just use the machine
1860 + * compatible.
1861 + */
1862 + if (of_machine_is_compatible("fsl,T2080QDS") ||
1863 + of_machine_is_compatible("fsl,T2080RDB") ||
1864 + of_machine_is_compatible("fsl,T2081QDS") ||
1865 + of_machine_is_compatible("fsl,T4240QDS") ||
1866 + of_machine_is_compatible("fsl,T4240RDB"))
1867 + memac->rgmii_no_half_duplex = true;
1868 +
1869 + /* Most boards should use MLO_AN_INBAND, but existing boards don't have
1870 + * a managed property. Default to MLO_AN_INBAND if nothing else is
1871 + * specified. We need to be careful and not enable this if we have a
1872 + * fixed link or if we are using MII or RGMII, since those
1873 + * configurations modes don't use in-band autonegotiation.
1874 + */
1875 + fixed = of_get_child_by_name(mac_node, "fixed-link");
1876 + if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
1877 + !of_property_read_bool(mac_node, "managed") &&
1878 + mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
1879 + !phy_interface_mode_is_rgmii(mac_dev->phy_if))
1880 + mac_dev->phylink_config.ovr_an_inband = true;
1881 + of_node_put(fixed);
1882 +
1883 err = memac_init(mac_dev->fman_mac);
1884 if (err < 0)
1885 - goto _return_fixed_link_free;
1886 + goto _return_fm_mac_free;
1887
1888 dev_info(mac_dev->dev, "FMan MEMAC\n");
1889
1890 - goto _return;
1891 + return 0;
1892
1893 -_return_phy_power_off:
1894 - phy_power_off(memac->serdes);
1895 -_return_phy_exit:
1896 - phy_exit(memac->serdes);
1897 -_return_fixed_link_free:
1898 - kfree(fixed_link);
1899 _return_fm_mac_free:
1900 memac_free(mac_dev->fman_mac);
1901 -_return:
1902 return err;
1903 }
1904 --- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
1905 +++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
1906 @@ -13,6 +13,7 @@
1907 #include <linux/bitrev.h>
1908 #include <linux/io.h>
1909 #include <linux/crc32.h>
1910 +#include <linux/netdevice.h>
1911
1912 /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
1913 #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
1914 @@ -243,10 +244,6 @@ static int init(struct tgec_regs __iomem
1915
1916 static int check_init_parameters(struct fman_mac *tgec)
1917 {
1918 - if (tgec->max_speed < SPEED_10000) {
1919 - pr_err("10G MAC driver only support 10G speed\n");
1920 - return -EINVAL;
1921 - }
1922 if (!tgec->exception_cb) {
1923 pr_err("uninitialized exception_cb\n");
1924 return -EINVAL;
1925 @@ -384,40 +381,13 @@ static void free_init_resources(struct f
1926 tgec->unicast_addr_hash = NULL;
1927 }
1928
1929 -static bool is_init_done(struct tgec_cfg *cfg)
1930 -{
1931 - /* Checks if tGEC driver parameters were initialized */
1932 - if (!cfg)
1933 - return true;
1934 -
1935 - return false;
1936 -}
1937 -
1938 static int tgec_enable(struct fman_mac *tgec)
1939 {
1940 - struct tgec_regs __iomem *regs = tgec->regs;
1941 - u32 tmp;
1942 -
1943 - if (!is_init_done(tgec->cfg))
1944 - return -EINVAL;
1945 -
1946 - tmp = ioread32be(&regs->command_config);
1947 - tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
1948 - iowrite32be(tmp, &regs->command_config);
1949 -
1950 return 0;
1951 }
1952
1953 static void tgec_disable(struct fman_mac *tgec)
1954 {
1955 - struct tgec_regs __iomem *regs = tgec->regs;
1956 - u32 tmp;
1957 -
1958 - WARN_ON_ONCE(!is_init_done(tgec->cfg));
1959 -
1960 - tmp = ioread32be(&regs->command_config);
1961 - tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
1962 - iowrite32be(tmp, &regs->command_config);
1963 }
1964
1965 static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
1966 @@ -425,9 +395,6 @@ static int tgec_set_promiscuous(struct f
1967 struct tgec_regs __iomem *regs = tgec->regs;
1968 u32 tmp;
1969
1970 - if (!is_init_done(tgec->cfg))
1971 - return -EINVAL;
1972 -
1973 tmp = ioread32be(&regs->command_config);
1974 if (new_val)
1975 tmp |= CMD_CFG_PROMIS_EN;
1976 @@ -444,9 +411,6 @@ static int tgec_set_tx_pause_frames(stru
1977 {
1978 struct tgec_regs __iomem *regs = tgec->regs;
1979
1980 - if (!is_init_done(tgec->cfg))
1981 - return -EINVAL;
1982 -
1983 iowrite32be((u32)pause_time, &regs->pause_quant);
1984
1985 return 0;
1986 @@ -457,9 +421,6 @@ static int tgec_accept_rx_pause_frames(s
1987 struct tgec_regs __iomem *regs = tgec->regs;
1988 u32 tmp;
1989
1990 - if (!is_init_done(tgec->cfg))
1991 - return -EINVAL;
1992 -
1993 tmp = ioread32be(&regs->command_config);
1994 if (!en)
1995 tmp |= CMD_CFG_PAUSE_IGNORE;
1996 @@ -470,12 +431,53 @@ static int tgec_accept_rx_pause_frames(s
1997 return 0;
1998 }
1999
2000 +static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
2001 + const struct phylink_link_state *state)
2002 +{
2003 +}
2004 +
2005 +static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
2006 + unsigned int mode, phy_interface_t interface,
2007 + int speed, int duplex, bool tx_pause, bool rx_pause)
2008 +{
2009 + struct mac_device *mac_dev = fman_config_to_mac(config);
2010 + struct fman_mac *tgec = mac_dev->fman_mac;
2011 + struct tgec_regs __iomem *regs = tgec->regs;
2012 + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
2013 + FSL_FM_PAUSE_TIME_DISABLE;
2014 + u32 tmp;
2015 +
2016 + tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
2017 + tgec_accept_rx_pause_frames(tgec, rx_pause);
2018 + mac_dev->update_speed(mac_dev, speed);
2019 +
2020 + tmp = ioread32be(&regs->command_config);
2021 + tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
2022 + iowrite32be(tmp, &regs->command_config);
2023 +}
2024 +
2025 +static void tgec_link_down(struct phylink_config *config, unsigned int mode,
2026 + phy_interface_t interface)
2027 +{
2028 + struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
2029 + struct tgec_regs __iomem *regs = tgec->regs;
2030 + u32 tmp;
2031 +
2032 + tmp = ioread32be(&regs->command_config);
2033 + tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
2034 + iowrite32be(tmp, &regs->command_config);
2035 +}
2036 +
2037 +static const struct phylink_mac_ops tgec_mac_ops = {
2038 + .validate = phylink_generic_validate,
2039 + .mac_config = tgec_mac_config,
2040 + .mac_link_up = tgec_link_up,
2041 + .mac_link_down = tgec_link_down,
2042 +};
2043 +
2044 static int tgec_modify_mac_address(struct fman_mac *tgec,
2045 const enet_addr_t *p_enet_addr)
2046 {
2047 - if (!is_init_done(tgec->cfg))
2048 - return -EINVAL;
2049 -
2050 tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
2051 set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
2052
2053 @@ -490,9 +492,6 @@ static int tgec_add_hash_mac_address(str
2054 u32 crc = 0xFFFFFFFF, hash;
2055 u64 addr;
2056
2057 - if (!is_init_done(tgec->cfg))
2058 - return -EINVAL;
2059 -
2060 addr = ENET_ADDR_TO_UINT64(*eth_addr);
2061
2062 if (!(addr & GROUP_ADDRESS)) {
2063 @@ -525,9 +524,6 @@ static int tgec_set_allmulti(struct fman
2064 u32 entry;
2065 struct tgec_regs __iomem *regs = tgec->regs;
2066
2067 - if (!is_init_done(tgec->cfg))
2068 - return -EINVAL;
2069 -
2070 if (enable) {
2071 for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
2072 iowrite32be(entry | TGEC_HASH_MCAST_EN,
2073 @@ -548,9 +544,6 @@ static int tgec_set_tstamp(struct fman_m
2074 struct tgec_regs __iomem *regs = tgec->regs;
2075 u32 tmp;
2076
2077 - if (!is_init_done(tgec->cfg))
2078 - return -EINVAL;
2079 -
2080 tmp = ioread32be(&regs->command_config);
2081
2082 if (enable)
2083 @@ -572,9 +565,6 @@ static int tgec_del_hash_mac_address(str
2084 u32 crc = 0xFFFFFFFF, hash;
2085 u64 addr;
2086
2087 - if (!is_init_done(tgec->cfg))
2088 - return -EINVAL;
2089 -
2090 addr = ((*(u64 *)eth_addr) >> 16);
2091
2092 /* CRC calculation */
2093 @@ -601,22 +591,12 @@ static int tgec_del_hash_mac_address(str
2094 return 0;
2095 }
2096
2097 -static void tgec_adjust_link(struct mac_device *mac_dev)
2098 -{
2099 - struct phy_device *phy_dev = mac_dev->phy_dev;
2100 -
2101 - mac_dev->update_speed(mac_dev, phy_dev->speed);
2102 -}
2103 -
2104 static int tgec_set_exception(struct fman_mac *tgec,
2105 enum fman_mac_exceptions exception, bool enable)
2106 {
2107 struct tgec_regs __iomem *regs = tgec->regs;
2108 u32 bit_mask = 0;
2109
2110 - if (!is_init_done(tgec->cfg))
2111 - return -EINVAL;
2112 -
2113 bit_mask = get_exception_flag(exception);
2114 if (bit_mask) {
2115 if (enable)
2116 @@ -641,9 +621,6 @@ static int tgec_init(struct fman_mac *tg
2117 enet_addr_t eth_addr;
2118 int err;
2119
2120 - if (is_init_done(tgec->cfg))
2121 - return -EINVAL;
2122 -
2123 if (DEFAULT_RESET_ON_INIT &&
2124 (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
2125 pr_err("Can't reset MAC!\n");
2126 @@ -753,7 +730,6 @@ static struct fman_mac *tgec_config(stru
2127
2128 tgec->regs = mac_dev->vaddr;
2129 tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
2130 - tgec->max_speed = params->max_speed;
2131 tgec->mac_id = params->mac_id;
2132 tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT |
2133 TGEC_IMASK_REM_FAULT |
2134 @@ -788,17 +764,15 @@ int tgec_initialization(struct mac_devic
2135 int err;
2136 struct fman_mac *tgec;
2137
2138 + mac_dev->phylink_ops = &tgec_mac_ops;
2139 mac_dev->set_promisc = tgec_set_promiscuous;
2140 mac_dev->change_addr = tgec_modify_mac_address;
2141 mac_dev->add_hash_mac_addr = tgec_add_hash_mac_address;
2142 mac_dev->remove_hash_mac_addr = tgec_del_hash_mac_address;
2143 - mac_dev->set_tx_pause = tgec_set_tx_pause_frames;
2144 - mac_dev->set_rx_pause = tgec_accept_rx_pause_frames;
2145 mac_dev->set_exception = tgec_set_exception;
2146 mac_dev->set_allmulti = tgec_set_allmulti;
2147 mac_dev->set_tstamp = tgec_set_tstamp;
2148 mac_dev->set_multi = fman_set_multi;
2149 - mac_dev->adjust_link = tgec_adjust_link;
2150 mac_dev->enable = tgec_enable;
2151 mac_dev->disable = tgec_disable;
2152
2153 @@ -808,6 +782,19 @@ int tgec_initialization(struct mac_devic
2154 goto _return;
2155 }
2156
2157 + /* The internal connection to the serdes is XGMII, but this isn't
2158 + * really correct for the phy mode (which is the external connection).
2159 + * However, this is how all older device trees say that they want
2160 + * XAUI, so just convert it for them.
2161 + */
2162 + if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
2163 + mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
2164 +
2165 + __set_bit(PHY_INTERFACE_MODE_XAUI,
2166 + mac_dev->phylink_config.supported_interfaces);
2167 + mac_dev->phylink_config.mac_capabilities =
2168 + MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
2169 +
2170 tgec = mac_dev->fman_mac;
2171 tgec->cfg->max_frame_length = fman_get_max_frm();
2172 err = tgec_init(tgec);
2173 --- a/drivers/net/ethernet/freescale/fman/mac.c
2174 +++ b/drivers/net/ethernet/freescale/fman/mac.c
2175 @@ -15,6 +15,7 @@
2176 #include <linux/phy.h>
2177 #include <linux/netdevice.h>
2178 #include <linux/phy_fixed.h>
2179 +#include <linux/phylink.h>
2180 #include <linux/etherdevice.h>
2181 #include <linux/libfdt_env.h>
2182
2183 @@ -93,130 +94,8 @@ int fman_set_multi(struct net_device *ne
2184 return 0;
2185 }
2186
2187 -/**
2188 - * fman_set_mac_active_pause
2189 - * @mac_dev: A pointer to the MAC device
2190 - * @rx: Pause frame setting for RX
2191 - * @tx: Pause frame setting for TX
2192 - *
2193 - * Set the MAC RX/TX PAUSE frames settings
2194 - *
2195 - * Avoid redundant calls to FMD, if the MAC driver already contains the desired
2196 - * active PAUSE settings. Otherwise, the new active settings should be reflected
2197 - * in FMan.
2198 - *
2199 - * Return: 0 on success; Error code otherwise.
2200 - */
2201 -int fman_set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx)
2202 -{
2203 - struct fman_mac *fman_mac = mac_dev->fman_mac;
2204 - int err = 0;
2205 -
2206 - if (rx != mac_dev->rx_pause_active) {
2207 - err = mac_dev->set_rx_pause(fman_mac, rx);
2208 - if (likely(err == 0))
2209 - mac_dev->rx_pause_active = rx;
2210 - }
2211 -
2212 - if (tx != mac_dev->tx_pause_active) {
2213 - u16 pause_time = (tx ? FSL_FM_PAUSE_TIME_ENABLE :
2214 - FSL_FM_PAUSE_TIME_DISABLE);
2215 -
2216 - err = mac_dev->set_tx_pause(fman_mac, 0, pause_time, 0);
2217 -
2218 - if (likely(err == 0))
2219 - mac_dev->tx_pause_active = tx;
2220 - }
2221 -
2222 - return err;
2223 -}
2224 -EXPORT_SYMBOL(fman_set_mac_active_pause);
2225 -
2226 -/**
2227 - * fman_get_pause_cfg
2228 - * @mac_dev: A pointer to the MAC device
2229 - * @rx_pause: Return value for RX setting
2230 - * @tx_pause: Return value for TX setting
2231 - *
2232 - * Determine the MAC RX/TX PAUSE frames settings based on PHY
2233 - * autonegotiation or values set by eththool.
2234 - *
2235 - * Return: Pointer to FMan device.
2236 - */
2237 -void fman_get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause,
2238 - bool *tx_pause)
2239 -{
2240 - struct phy_device *phy_dev = mac_dev->phy_dev;
2241 - u16 lcl_adv, rmt_adv;
2242 - u8 flowctrl;
2243 -
2244 - *rx_pause = *tx_pause = false;
2245 -
2246 - if (!phy_dev->duplex)
2247 - return;
2248 -
2249 - /* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings
2250 - * are those set by ethtool.
2251 - */
2252 - if (!mac_dev->autoneg_pause) {
2253 - *rx_pause = mac_dev->rx_pause_req;
2254 - *tx_pause = mac_dev->tx_pause_req;
2255 - return;
2256 - }
2257 -
2258 - /* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE
2259 - * settings depend on the result of the link negotiation.
2260 - */
2261 -
2262 - /* get local capabilities */
2263 - lcl_adv = linkmode_adv_to_lcl_adv_t(phy_dev->advertising);
2264 -
2265 - /* get link partner capabilities */
2266 - rmt_adv = 0;
2267 - if (phy_dev->pause)
2268 - rmt_adv |= LPA_PAUSE_CAP;
2269 - if (phy_dev->asym_pause)
2270 - rmt_adv |= LPA_PAUSE_ASYM;
2271 -
2272 - /* Calculate TX/RX settings based on local and peer advertised
2273 - * symmetric/asymmetric PAUSE capabilities.
2274 - */
2275 - flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
2276 - if (flowctrl & FLOW_CTRL_RX)
2277 - *rx_pause = true;
2278 - if (flowctrl & FLOW_CTRL_TX)
2279 - *tx_pause = true;
2280 -}
2281 -EXPORT_SYMBOL(fman_get_pause_cfg);
2282 -
2283 -#define DTSEC_SUPPORTED \
2284 - (SUPPORTED_10baseT_Half \
2285 - | SUPPORTED_10baseT_Full \
2286 - | SUPPORTED_100baseT_Half \
2287 - | SUPPORTED_100baseT_Full \
2288 - | SUPPORTED_Autoneg \
2289 - | SUPPORTED_Pause \
2290 - | SUPPORTED_Asym_Pause \
2291 - | SUPPORTED_FIBRE \
2292 - | SUPPORTED_MII)
2293 -
2294 static DEFINE_MUTEX(eth_lock);
2295
2296 -static const u16 phy2speed[] = {
2297 - [PHY_INTERFACE_MODE_MII] = SPEED_100,
2298 - [PHY_INTERFACE_MODE_GMII] = SPEED_1000,
2299 - [PHY_INTERFACE_MODE_SGMII] = SPEED_1000,
2300 - [PHY_INTERFACE_MODE_TBI] = SPEED_1000,
2301 - [PHY_INTERFACE_MODE_RMII] = SPEED_100,
2302 - [PHY_INTERFACE_MODE_RGMII] = SPEED_1000,
2303 - [PHY_INTERFACE_MODE_RGMII_ID] = SPEED_1000,
2304 - [PHY_INTERFACE_MODE_RGMII_RXID] = SPEED_1000,
2305 - [PHY_INTERFACE_MODE_RGMII_TXID] = SPEED_1000,
2306 - [PHY_INTERFACE_MODE_RTBI] = SPEED_1000,
2307 - [PHY_INTERFACE_MODE_QSGMII] = SPEED_1000,
2308 - [PHY_INTERFACE_MODE_XGMII] = SPEED_10000
2309 -};
2310 -
2311 static struct platform_device *dpaa_eth_add_device(int fman_id,
2312 struct mac_device *mac_dev)
2313 {
2314 @@ -263,8 +142,8 @@ no_mem:
2315 }
2316
2317 static const struct of_device_id mac_match[] = {
2318 - { .compatible = "fsl,fman-dtsec", .data = dtsec_initialization },
2319 - { .compatible = "fsl,fman-xgec", .data = tgec_initialization },
2320 + { .compatible = "fsl,fman-dtsec", .data = dtsec_initialization },
2321 + { .compatible = "fsl,fman-xgec", .data = tgec_initialization },
2322 { .compatible = "fsl,fman-memac", .data = memac_initialization },
2323 {}
2324 };
2325 @@ -295,6 +174,7 @@ static int mac_probe(struct platform_dev
2326 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2327 if (!priv)
2328 return -ENOMEM;
2329 + platform_set_drvdata(_of_dev, mac_dev);
2330
2331 /* Save private information */
2332 mac_dev->priv = priv;
2333 @@ -424,57 +304,21 @@ static int mac_probe(struct platform_dev
2334 }
2335 mac_dev->phy_if = phy_if;
2336
2337 - priv->speed = phy2speed[mac_dev->phy_if];
2338 - params.max_speed = priv->speed;
2339 - mac_dev->if_support = DTSEC_SUPPORTED;
2340 - /* We don't support half-duplex in SGMII mode */
2341 - if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
2342 - mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
2343 - SUPPORTED_100baseT_Half);
2344 -
2345 - /* Gigabit support (no half-duplex) */
2346 - if (params.max_speed == 1000)
2347 - mac_dev->if_support |= SUPPORTED_1000baseT_Full;
2348 -
2349 - /* The 10G interface only supports one mode */
2350 - if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
2351 - mac_dev->if_support = SUPPORTED_10000baseT_Full;
2352 -
2353 - /* Get the rest of the PHY information */
2354 - mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
2355 -
2356 - params.basex_if = false;
2357 params.mac_id = priv->cell_index;
2358 params.fm = (void *)priv->fman;
2359 params.exception_cb = mac_exception;
2360 params.event_cb = mac_exception;
2361
2362 err = init(mac_dev, mac_node, &params);
2363 - if (err < 0) {
2364 - dev_err(dev, "mac_dev->init() = %d\n", err);
2365 - of_node_put(mac_dev->phy_node);
2366 - return err;
2367 - }
2368 -
2369 - /* pause frame autonegotiation enabled */
2370 - mac_dev->autoneg_pause = true;
2371 -
2372 - /* By intializing the values to false, force FMD to enable PAUSE frames
2373 - * on RX and TX
2374 - */
2375 - mac_dev->rx_pause_req = true;
2376 - mac_dev->tx_pause_req = true;
2377 - mac_dev->rx_pause_active = false;
2378 - mac_dev->tx_pause_active = false;
2379 - err = fman_set_mac_active_pause(mac_dev, true, true);
2380 if (err < 0)
2381 - dev_err(dev, "fman_set_mac_active_pause() = %d\n", err);
2382 + return err;
2383
2384 if (!is_zero_ether_addr(mac_dev->addr))
2385 dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
2386
2387 priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
2388 if (IS_ERR(priv->eth_dev)) {
2389 + err = PTR_ERR(priv->eth_dev);
2390 dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
2391 priv->cell_index);
2392 priv->eth_dev = NULL;
2393 --- a/drivers/net/ethernet/freescale/fman/mac.h
2394 +++ b/drivers/net/ethernet/freescale/fman/mac.h
2395 @@ -9,6 +9,7 @@
2396 #include <linux/device.h>
2397 #include <linux/if_ether.h>
2398 #include <linux/phy.h>
2399 +#include <linux/phylink.h>
2400 #include <linux/list.h>
2401
2402 #include "fman_port.h"
2403 @@ -24,32 +25,22 @@ struct mac_device {
2404 struct resource *res;
2405 u8 addr[ETH_ALEN];
2406 struct fman_port *port[2];
2407 - u32 if_support;
2408 - struct phy_device *phy_dev;
2409 + struct phylink *phylink;
2410 + struct phylink_config phylink_config;
2411 phy_interface_t phy_if;
2412 - struct device_node *phy_node;
2413 - struct net_device *net_dev;
2414
2415 - bool autoneg_pause;
2416 - bool rx_pause_req;
2417 - bool tx_pause_req;
2418 - bool rx_pause_active;
2419 - bool tx_pause_active;
2420 bool promisc;
2421 bool allmulti;
2422
2423 + const struct phylink_mac_ops *phylink_ops;
2424 int (*enable)(struct fman_mac *mac_dev);
2425 void (*disable)(struct fman_mac *mac_dev);
2426 - void (*adjust_link)(struct mac_device *mac_dev);
2427 int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
2428 int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
2429 int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
2430 int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
2431 int (*set_multi)(struct net_device *net_dev,
2432 struct mac_device *mac_dev);
2433 - int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
2434 - int (*set_tx_pause)(struct fman_mac *mac_dev, u8 priority,
2435 - u16 pause_time, u16 thresh_time);
2436 int (*set_exception)(struct fman_mac *mac_dev,
2437 enum fman_mac_exceptions exception, bool enable);
2438 int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
2439 @@ -63,6 +54,12 @@ struct mac_device {
2440 struct mac_priv_s *priv;
2441 };
2442
2443 +static inline struct mac_device
2444 +*fman_config_to_mac(struct phylink_config *config)
2445 +{
2446 + return container_of(config, struct mac_device, phylink_config);
2447 +}
2448 +
2449 struct dpaa_eth_data {
2450 struct mac_device *mac_dev;
2451 int mac_hw_id;
OpenWrt Source Repository