target/linux/generic/backport-6.6/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch

   1 From 813abcd98fb1b2cccf850cdfa092a4bfc50b2363 Mon Sep 17 00:00:00 2001
   2 From: Frank <Frank.Sae@motor-comm.com>
   3 Date: Tue, 22 Nov 2022 16:42:32 +0800
   4 Subject: [PATCH] net: phy: add Motorcomm YT8531S phy id.
   5
   6 We added patch for motorcomm.c to support YT8531S. This patch has
   7 been tested on AM335x platform which has one YT8531S interface
   8 card and passed all test cases.
   9 The tested cases indluding: YT8531S UTP function with support of
  10 10M/100M/1000M; YT8531S Fiber function with support of 100M/1000M;
  11 and YT8531S Combo function that supports auto detection of media type.
  12
  13 Since most functions of YT8531S are similar to YT8521 and we reuse some
  14 codes for YT8521 in the patch file.
  15
  16 Signed-off-by: Frank <Frank.Sae@motor-comm.com>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/phy/Kconfig     |  2 +-
  20  drivers/net/phy/motorcomm.c | 52 +++++++++++++++++++++++++++++++++----
  21  2 files changed, 48 insertions(+), 6 deletions(-)
  22
  23 --- a/drivers/net/phy/Kconfig
  24 +++ b/drivers/net/phy/Kconfig
  25 @@ -257,7 +257,7 @@ config MOTORCOMM_PHY
  26         tristate "Motorcomm PHYs"
  27         help
  28           Enables support for Motorcomm network PHYs.
  29 -         Currently supports the YT8511, YT8521 Gigabit Ethernet PHYs.
  30 +         Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs.
  31
  32  config NATIONAL_PHY
  33         tristate "National Semiconductor PHYs"
  34 --- a/drivers/net/phy/motorcomm.c
  35 +++ b/drivers/net/phy/motorcomm.c
  36 @@ -1,6 +1,6 @@
  37  // SPDX-License-Identifier: GPL-2.0+
  38  /*
  39 - * Motorcomm 8511/8521 PHY driver.
  40 + * Motorcomm 8511/8521/8531S PHY driver.
  41   *
  42   * Author: Peter Geis <pgwipeout@gmail.com>
  43   * Author: Frank <Frank.Sae@motor-comm.com>
  44 @@ -12,9 +12,10 @@
  45  #include <linux/phy.h>
  46
  47  #define PHY_ID_YT8511          0x0000010a
  48 -#define PHY_ID_YT8521                          0x0000011A
  49 +#define PHY_ID_YT8521          0x0000011A
  50 +#define PHY_ID_YT8531S         0x4F51E91A
  51
  52 -/* YT8521 Register Overview
  53 +/* YT8521/YT8531S Register Overview
  54   *     UTP Register space      |       FIBER Register space
  55   *  ------------------------------------------------------------
  56   * |   UTP MII                 |       FIBER MII               |
  57 @@ -147,7 +148,7 @@
  58  #define YT8521_LINK_TIMER_CFG2_REG             0xA5
  59  #define YT8521_LTCR_EN_AUTOSEN                 BIT(15)
  60
  61 -/* 0xA000, 0xA001, 0xA003 ,and 0xA006 ~ 0xA00A  are common ext registers
  62 +/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
  63   * of yt8521 phy. There is no need to switch reg space when operating these
  64   * registers.
  65   */
  66 @@ -221,6 +222,9 @@
  67   */
  68  #define YTPHY_WCR_TYPE_PULSE                   BIT(0)
  69
  70 +#define YT8531S_SYNCE_CFG_REG                  0xA012
  71 +#define YT8531S_SCR_SYNCE_ENABLE               BIT(6)
  72 +
  73  /* Extended Register  end */
  74
  75  struct yt8521_priv {
  76 @@ -648,6 +652,26 @@ static int yt8521_probe(struct phy_devic
  77  }
  78
  79  /**
  80 + * yt8531s_probe() - read chip config then set suitable polling_mode
  81 + * @phydev: a pointer to a &struct phy_device
  82 + *
  83 + * returns 0 or negative errno code
  84 + */
  85 +static int yt8531s_probe(struct phy_device *phydev)
  86 +{
  87 +       int ret;
  88 +
  89 +       /* Disable SyncE clock output by default */
  90 +       ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG,
  91 +                                        YT8531S_SCR_SYNCE_ENABLE, 0);
  92 +       if (ret < 0)
  93 +               return ret;
  94 +
  95 +       /* same as yt8521_probe */
  96 +       return yt8521_probe(phydev);
  97 +}
  98 +
  99 +/**
 100   * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
 101   * @phydev: a pointer to a &struct phy_device
 102   *
 103 @@ -1750,11 +1774,28 @@ static struct phy_driver motorcomm_phy_d
 104                 .suspend        = yt8521_suspend,
 105                 .resume         = yt8521_resume,
 106         },
 107 +       {
 108 +               PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
 109 +               .name           = "YT8531S Gigabit Ethernet",
 110 +               .get_features   = yt8521_get_features,
 111 +               .probe          = yt8531s_probe,
 112 +               .read_page      = yt8521_read_page,
 113 +               .write_page     = yt8521_write_page,
 114 +               .get_wol        = ytphy_get_wol,
 115 +               .set_wol        = ytphy_set_wol,
 116 +               .config_aneg    = yt8521_config_aneg,
 117 +               .aneg_done      = yt8521_aneg_done,
 118 +               .config_init    = yt8521_config_init,
 119 +               .read_status    = yt8521_read_status,
 120 +               .soft_reset     = yt8521_soft_reset,
 121 +               .suspend        = yt8521_suspend,
 122 +               .resume         = yt8521_resume,
 123 +       },
 124  };
 125
 126  module_phy_driver(motorcomm_phy_drvs);
 127
 128 -MODULE_DESCRIPTION("Motorcomm 8511/8521 PHY driver");
 129 +MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver");
 130  MODULE_AUTHOR("Peter Geis");
 131  MODULE_AUTHOR("Frank");
 132  MODULE_LICENSE("GPL");
 133 @@ -1762,6 +1803,7 @@ MODULE_LICENSE("GPL");
 134  static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
 135         { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
 136         { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
 137 +       { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
 138         { /* sentinal */ }
 139  };
 140