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[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
37
38 #include "ar8216.h"
39
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 #define MIB_DESC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 }
51
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
90 };
91
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
132 };
133
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
136
137 static inline void
138 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
139 {
140 regaddr >>= 1;
141 *r1 = regaddr & 0x1e;
142
143 regaddr >>= 5;
144 *r2 = regaddr & 0x7;
145
146 regaddr >>= 3;
147 *page = regaddr & 0x1ff;
148 }
149
150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
151 static int
152 ar8xxx_phy_poll_reset(struct mii_bus *bus)
153 {
154 unsigned int sleep_msecs = 20;
155 int ret, elapsed, i;
156
157 for (elapsed = sleep_msecs; elapsed <= 600;
158 elapsed += sleep_msecs) {
159 msleep(sleep_msecs);
160 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
161 ret = mdiobus_read(bus, i, MII_BMCR);
162 if (ret < 0)
163 return ret;
164 if (ret & BMCR_RESET)
165 break;
166 if (i == AR8XXX_NUM_PHYS - 1) {
167 usleep_range(1000, 2000);
168 return 0;
169 }
170 }
171 }
172 return -ETIMEDOUT;
173 }
174
175 static int
176 ar8xxx_phy_check_aneg(struct phy_device *phydev)
177 {
178 int ret;
179
180 if (phydev->autoneg != AUTONEG_ENABLE)
181 return 0;
182 /*
183 * BMCR_ANENABLE might have been cleared
184 * by phy_init_hw in certain kernel versions
185 * therefore check for it
186 */
187 ret = phy_read(phydev, MII_BMCR);
188 if (ret < 0)
189 return ret;
190 if (ret & BMCR_ANENABLE)
191 return 0;
192
193 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
194 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
195 return phy_write(phydev, MII_BMCR, ret);
196 }
197
198 void
199 ar8xxx_phy_init(struct ar8xxx_priv *priv)
200 {
201 int i;
202 struct mii_bus *bus;
203
204 bus = priv->mii_bus;
205 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
206 if (priv->chip->phy_fixup)
207 priv->chip->phy_fixup(priv, i);
208
209 /* initialize the port itself */
210 mdiobus_write(bus, i, MII_ADVERTISE,
211 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
212 if (ar8xxx_has_gige(priv))
213 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
214 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
215 }
216
217 ar8xxx_phy_poll_reset(bus);
218 }
219
220 static u32
221 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
222 {
223 struct mii_bus *bus = priv->mii_bus;
224 u16 lo, hi;
225
226 lo = bus->read(bus, phy_id, regnum);
227 hi = bus->read(bus, phy_id, regnum + 1);
228
229 return (hi << 16) | lo;
230 }
231
232 static void
233 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
234 {
235 struct mii_bus *bus = priv->mii_bus;
236 u16 lo, hi;
237
238 lo = val & 0xffff;
239 hi = (u16) (val >> 16);
240
241 if (priv->chip->mii_lo_first)
242 {
243 bus->write(bus, phy_id, regnum, lo);
244 bus->write(bus, phy_id, regnum + 1, hi);
245 } else {
246 bus->write(bus, phy_id, regnum + 1, hi);
247 bus->write(bus, phy_id, regnum, lo);
248 }
249 }
250
251 u32
252 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
253 {
254 struct mii_bus *bus = priv->mii_bus;
255 u16 r1, r2, page;
256 u32 val;
257
258 split_addr((u32) reg, &r1, &r2, &page);
259
260 mutex_lock(&bus->mdio_lock);
261
262 bus->write(bus, 0x18, 0, page);
263 usleep_range(1000, 2000); /* wait for the page switch to propagate */
264 val = mii_read32(priv, 0x10 | r2, r1);
265
266 mutex_unlock(&bus->mdio_lock);
267
268 return val;
269 }
270
271 void
272 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
273 {
274 struct mii_bus *bus = priv->mii_bus;
275 u16 r1, r2, page;
276
277 split_addr((u32) reg, &r1, &r2, &page);
278
279 mutex_lock(&bus->mdio_lock);
280
281 bus->write(bus, 0x18, 0, page);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 mii_write32(priv, 0x10 | r2, r1, val);
284
285 mutex_unlock(&bus->mdio_lock);
286 }
287
288 u32
289 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
290 {
291 struct mii_bus *bus = priv->mii_bus;
292 u16 r1, r2, page;
293 u32 ret;
294
295 split_addr((u32) reg, &r1, &r2, &page);
296
297 mutex_lock(&bus->mdio_lock);
298
299 bus->write(bus, 0x18, 0, page);
300 usleep_range(1000, 2000); /* wait for the page switch to propagate */
301
302 ret = mii_read32(priv, 0x10 | r2, r1);
303 ret &= ~mask;
304 ret |= val;
305 mii_write32(priv, 0x10 | r2, r1, ret);
306
307 mutex_unlock(&bus->mdio_lock);
308
309 return ret;
310 }
311
312 void
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
326 {
327 struct mii_bus *bus = priv->mii_bus;
328
329 mutex_lock(&bus->mdio_lock);
330 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
331 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
332 mutex_unlock(&bus->mdio_lock);
333 }
334
335 static int
336 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
337 unsigned timeout)
338 {
339 int i;
340
341 for (i = 0; i < timeout; i++) {
342 u32 t;
343
344 t = ar8xxx_read(priv, reg);
345 if ((t & mask) == val)
346 return 0;
347
348 usleep_range(1000, 2000);
349 }
350
351 return -ETIMEDOUT;
352 }
353
354 static int
355 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
356 {
357 unsigned mib_func = priv->chip->mib_func;
358 int ret;
359
360 lockdep_assert_held(&priv->mib_lock);
361
362 /* Capture the hardware statistics for all ports */
363 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
364
365 /* Wait for the capturing to complete. */
366 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
367 if (ret)
368 goto out;
369
370 ret = 0;
371
372 out:
373 return ret;
374 }
375
376 static int
377 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
378 {
379 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
380 }
381
382 static int
383 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
384 {
385 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
386 }
387
388 static void
389 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
390 {
391 unsigned int base;
392 u64 *mib_stats;
393 int i;
394
395 WARN_ON(port >= priv->dev.ports);
396
397 lockdep_assert_held(&priv->mib_lock);
398
399 base = priv->chip->reg_port_stats_start +
400 priv->chip->reg_port_stats_length * port;
401
402 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
403 for (i = 0; i < priv->chip->num_mibs; i++) {
404 const struct ar8xxx_mib_desc *mib;
405 u64 t;
406
407 mib = &priv->chip->mib_decs[i];
408 t = ar8xxx_read(priv, base + mib->offset);
409 if (mib->size == 2) {
410 u64 hi;
411
412 hi = ar8xxx_read(priv, base + mib->offset + 4);
413 t |= hi << 32;
414 }
415
416 if (flush)
417 mib_stats[i] = 0;
418 else
419 mib_stats[i] += t;
420 }
421 }
422
423 static void
424 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
425 struct switch_port_link *link)
426 {
427 u32 status;
428 u32 speed;
429
430 memset(link, '\0', sizeof(*link));
431
432 status = priv->chip->read_port_status(priv, port);
433
434 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
435 if (link->aneg) {
436 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
437 } else {
438 link->link = true;
439
440 if (priv->get_port_link) {
441 int err;
442
443 err = priv->get_port_link(port);
444 if (err >= 0)
445 link->link = !!err;
446 }
447 }
448
449 if (!link->link)
450 return;
451
452 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
453 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
454 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
455
456 speed = (status & AR8216_PORT_STATUS_SPEED) >>
457 AR8216_PORT_STATUS_SPEED_S;
458
459 switch (speed) {
460 case AR8216_PORT_SPEED_10M:
461 link->speed = SWITCH_PORT_SPEED_10;
462 break;
463 case AR8216_PORT_SPEED_100M:
464 link->speed = SWITCH_PORT_SPEED_100;
465 break;
466 case AR8216_PORT_SPEED_1000M:
467 link->speed = SWITCH_PORT_SPEED_1000;
468 break;
469 default:
470 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
471 break;
472 }
473 }
474
475 static struct sk_buff *
476 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
477 {
478 struct ar8xxx_priv *priv = dev->phy_ptr;
479 unsigned char *buf;
480
481 if (unlikely(!priv))
482 goto error;
483
484 if (!priv->vlan)
485 goto send;
486
487 if (unlikely(skb_headroom(skb) < 2)) {
488 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
489 goto error;
490 }
491
492 buf = skb_push(skb, 2);
493 buf[0] = 0x10;
494 buf[1] = 0x80;
495
496 send:
497 return skb;
498
499 error:
500 dev_kfree_skb_any(skb);
501 return NULL;
502 }
503
504 static void
505 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
506 {
507 struct ar8xxx_priv *priv;
508 unsigned char *buf;
509 int port, vlan;
510
511 priv = dev->phy_ptr;
512 if (!priv)
513 return;
514
515 /* don't strip the header if vlan mode is disabled */
516 if (!priv->vlan)
517 return;
518
519 /* strip header, get vlan id */
520 buf = skb->data;
521 skb_pull(skb, 2);
522
523 /* check for vlan header presence */
524 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
525 return;
526
527 port = buf[0] & 0xf;
528
529 /* no need to fix up packets coming from a tagged source */
530 if (priv->vlan_tagged & (1 << port))
531 return;
532
533 /* lookup port vid from local table, the switch passes an invalid vlan id */
534 vlan = priv->vlan_id[priv->pvid[port]];
535
536 buf[14 + 2] &= 0xf0;
537 buf[14 + 2] |= vlan >> 8;
538 buf[15 + 2] = vlan & 0xff;
539 }
540
541 int
542 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
543 {
544 int timeout = 20;
545 u32 t = 0;
546
547 while (1) {
548 t = ar8xxx_read(priv, reg);
549 if ((t & mask) == val)
550 return 0;
551
552 if (timeout-- <= 0)
553 break;
554
555 udelay(10);
556 }
557
558 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
559 (unsigned int) reg, t, mask, val);
560 return -ETIMEDOUT;
561 }
562
563 static void
564 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
565 {
566 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
567 return;
568 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
569 val &= AR8216_VTUDATA_MEMBER;
570 val |= AR8216_VTUDATA_VALID;
571 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
572 }
573 op |= AR8216_VTU_ACTIVE;
574 ar8xxx_write(priv, AR8216_REG_VTU, op);
575 }
576
577 static void
578 ar8216_vtu_flush(struct ar8xxx_priv *priv)
579 {
580 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
581 }
582
583 static void
584 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
585 {
586 u32 op;
587
588 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
589 ar8216_vtu_op(priv, op, port_mask);
590 }
591
592 static int
593 ar8216_atu_flush(struct ar8xxx_priv *priv)
594 {
595 int ret;
596
597 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
598 if (!ret)
599 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
600
601 return ret;
602 }
603
604 static u32
605 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
606 {
607 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
608 }
609
610 static void
611 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
612 {
613 u32 header;
614 u32 egress, ingress;
615 u32 pvid;
616
617 if (priv->vlan) {
618 pvid = priv->vlan_id[priv->pvid[port]];
619 if (priv->vlan_tagged & (1 << port))
620 egress = AR8216_OUT_ADD_VLAN;
621 else
622 egress = AR8216_OUT_STRIP_VLAN;
623 ingress = AR8216_IN_SECURE;
624 } else {
625 pvid = port;
626 egress = AR8216_OUT_KEEP;
627 ingress = AR8216_IN_PORT_ONLY;
628 }
629
630 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
631 header = AR8216_PORT_CTRL_HEADER;
632 else
633 header = 0;
634
635 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
636 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
637 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
638 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
639 AR8216_PORT_CTRL_LEARN | header |
640 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
641 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
642
643 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
644 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
645 AR8216_PORT_VLAN_DEFAULT_ID,
646 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
647 (ingress << AR8216_PORT_VLAN_MODE_S) |
648 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
649 }
650
651 static int
652 ar8216_hw_init(struct ar8xxx_priv *priv)
653 {
654 if (priv->initialized)
655 return 0;
656
657 ar8xxx_phy_init(priv);
658
659 priv->initialized = true;
660 return 0;
661 }
662
663 static void
664 ar8216_init_globals(struct ar8xxx_priv *priv)
665 {
666 /* standard atheros magic */
667 ar8xxx_write(priv, 0x38, 0xc000050e);
668
669 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
670 AR8216_GCTRL_MTU, 1518 + 8 + 2);
671 }
672
673 static void
674 ar8216_init_port(struct ar8xxx_priv *priv, int port)
675 {
676 /* Enable port learning and tx */
677 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
678 AR8216_PORT_CTRL_LEARN |
679 (4 << AR8216_PORT_CTRL_STATE_S));
680
681 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
682
683 if (port == AR8216_PORT_CPU) {
684 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
685 AR8216_PORT_STATUS_LINK_UP |
686 (ar8xxx_has_gige(priv) ?
687 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
688 AR8216_PORT_STATUS_TXMAC |
689 AR8216_PORT_STATUS_RXMAC |
690 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
691 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
692 AR8216_PORT_STATUS_DUPLEX);
693 } else {
694 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
695 AR8216_PORT_STATUS_LINK_AUTO);
696 }
697 }
698
699 static void
700 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
701 {
702 u32 egress, ingress;
703 u32 pvid;
704
705 if (priv->vlan) {
706 pvid = priv->vlan_id[priv->pvid[port]];
707 if (priv->vlan_tagged & (1 << port))
708 egress = AR8216_OUT_ADD_VLAN;
709 else
710 egress = AR8216_OUT_STRIP_VLAN;
711 ingress = AR8216_IN_SECURE;
712 } else {
713 pvid = port;
714 egress = AR8216_OUT_KEEP;
715 ingress = AR8216_IN_PORT_ONLY;
716 }
717
718 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
719 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
720 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
721 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
722 AR8216_PORT_CTRL_LEARN |
723 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
724 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
725
726 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
727 AR8236_PORT_VLAN_DEFAULT_ID,
728 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
729
730 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
731 AR8236_PORT_VLAN2_VLAN_MODE |
732 AR8236_PORT_VLAN2_MEMBER,
733 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
734 (members << AR8236_PORT_VLAN2_MEMBER_S));
735 }
736
737 static void
738 ar8236_init_globals(struct ar8xxx_priv *priv)
739 {
740 /* enable jumbo frames */
741 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
742 AR8316_GCTRL_MTU, 9018 + 8 + 2);
743
744 /* enable cpu port to receive arp frames */
745 ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
746 AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
747
748 /* enable cpu port to receive multicast and broadcast frames */
749 ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
750 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
751 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
752
753 /* Enable MIB counters */
754 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
755 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
756 AR8236_MIB_EN);
757 }
758
759 static int
760 ar8316_hw_init(struct ar8xxx_priv *priv)
761 {
762 u32 val, newval;
763
764 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
765
766 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
767 if (priv->port4_phy) {
768 /* value taken from Ubiquiti RouterStation Pro */
769 newval = 0x81461bea;
770 pr_info("ar8316: Using port 4 as PHY\n");
771 } else {
772 newval = 0x01261be2;
773 pr_info("ar8316: Using port 4 as switch port\n");
774 }
775 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
776 /* value taken from AVM Fritz!Box 7390 sources */
777 newval = 0x010e5b71;
778 } else {
779 /* no known value for phy interface */
780 pr_err("ar8316: unsupported mii mode: %d.\n",
781 priv->phy->interface);
782 return -EINVAL;
783 }
784
785 if (val == newval)
786 goto out;
787
788 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
789
790 if (priv->port4_phy &&
791 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
792 /* work around for phy4 rgmii mode */
793 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
794 /* rx delay */
795 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
796 /* tx delay */
797 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
798 msleep(1000);
799 }
800
801 ar8xxx_phy_init(priv);
802
803 out:
804 priv->initialized = true;
805 return 0;
806 }
807
808 static void
809 ar8316_init_globals(struct ar8xxx_priv *priv)
810 {
811 /* standard atheros magic */
812 ar8xxx_write(priv, 0x38, 0xc000050e);
813
814 /* enable cpu port to receive multicast and broadcast frames */
815 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
816
817 /* enable jumbo frames */
818 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
819 AR8316_GCTRL_MTU, 9018 + 8 + 2);
820
821 /* Enable MIB counters */
822 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
823 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
824 AR8236_MIB_EN);
825 }
826
827 int
828 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
829 struct switch_val *val)
830 {
831 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
832 priv->vlan = !!val->value.i;
833 return 0;
834 }
835
836 int
837 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
838 struct switch_val *val)
839 {
840 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
841 val->value.i = priv->vlan;
842 return 0;
843 }
844
845
846 int
847 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
848 {
849 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
850
851 /* make sure no invalid PVIDs get set */
852
853 if (vlan >= dev->vlans)
854 return -EINVAL;
855
856 priv->pvid[port] = vlan;
857 return 0;
858 }
859
860 int
861 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
862 {
863 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
864 *vlan = priv->pvid[port];
865 return 0;
866 }
867
868 static int
869 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
870 struct switch_val *val)
871 {
872 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
873 priv->vlan_id[val->port_vlan] = val->value.i;
874 return 0;
875 }
876
877 static int
878 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
879 struct switch_val *val)
880 {
881 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
882 val->value.i = priv->vlan_id[val->port_vlan];
883 return 0;
884 }
885
886 int
887 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
888 struct switch_port_link *link)
889 {
890 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
891
892 ar8216_read_port_link(priv, port, link);
893 return 0;
894 }
895
896 static int
897 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
898 {
899 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
900 u8 ports = priv->vlan_table[val->port_vlan];
901 int i;
902
903 val->len = 0;
904 for (i = 0; i < dev->ports; i++) {
905 struct switch_port *p;
906
907 if (!(ports & (1 << i)))
908 continue;
909
910 p = &val->value.ports[val->len++];
911 p->id = i;
912 if (priv->vlan_tagged & (1 << i))
913 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
914 else
915 p->flags = 0;
916 }
917 return 0;
918 }
919
920 static int
921 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
922 {
923 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
924 u8 *vt = &priv->vlan_table[val->port_vlan];
925 int i, j;
926
927 *vt = 0;
928 for (i = 0; i < val->len; i++) {
929 struct switch_port *p = &val->value.ports[i];
930
931 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
932 priv->vlan_tagged |= (1 << p->id);
933 } else {
934 priv->vlan_tagged &= ~(1 << p->id);
935 priv->pvid[p->id] = val->port_vlan;
936
937 /* make sure that an untagged port does not
938 * appear in other vlans */
939 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
940 if (j == val->port_vlan)
941 continue;
942 priv->vlan_table[j] &= ~(1 << p->id);
943 }
944 }
945
946 *vt |= 1 << p->id;
947 }
948 return 0;
949 }
950
951 static void
952 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
953 {
954 int port;
955
956 /* reset all mirror registers */
957 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
958 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
959 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
960 for (port = 0; port < AR8216_NUM_PORTS; port++) {
961 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
962 AR8216_PORT_CTRL_MIRROR_RX,
963 0);
964
965 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
966 AR8216_PORT_CTRL_MIRROR_TX,
967 0);
968 }
969
970 /* now enable mirroring if necessary */
971 if (priv->source_port >= AR8216_NUM_PORTS ||
972 priv->monitor_port >= AR8216_NUM_PORTS ||
973 priv->source_port == priv->monitor_port) {
974 return;
975 }
976
977 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
978 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
979 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
980
981 if (priv->mirror_rx)
982 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
983 AR8216_PORT_CTRL_MIRROR_RX,
984 AR8216_PORT_CTRL_MIRROR_RX);
985
986 if (priv->mirror_tx)
987 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
988 AR8216_PORT_CTRL_MIRROR_TX,
989 AR8216_PORT_CTRL_MIRROR_TX);
990 }
991
992 int
993 ar8xxx_sw_hw_apply(struct switch_dev *dev)
994 {
995 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
996 u8 portmask[AR8X16_MAX_PORTS];
997 int i, j;
998
999 mutex_lock(&priv->reg_mutex);
1000 /* flush all vlan translation unit entries */
1001 priv->chip->vtu_flush(priv);
1002
1003 memset(portmask, 0, sizeof(portmask));
1004 if (!priv->init) {
1005 /* calculate the port destination masks and load vlans
1006 * into the vlan translation unit */
1007 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1008 u8 vp = priv->vlan_table[j];
1009
1010 if (!vp)
1011 continue;
1012
1013 for (i = 0; i < dev->ports; i++) {
1014 u8 mask = (1 << i);
1015 if (vp & mask)
1016 portmask[i] |= vp & ~mask;
1017 }
1018
1019 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1020 priv->vlan_table[j]);
1021 }
1022 } else {
1023 /* vlan disabled:
1024 * isolate all ports, but connect them to the cpu port */
1025 for (i = 0; i < dev->ports; i++) {
1026 if (i == AR8216_PORT_CPU)
1027 continue;
1028
1029 portmask[i] = 1 << AR8216_PORT_CPU;
1030 portmask[AR8216_PORT_CPU] |= (1 << i);
1031 }
1032 }
1033
1034 /* update the port destination mask registers and tag settings */
1035 for (i = 0; i < dev->ports; i++) {
1036 priv->chip->setup_port(priv, i, portmask[i]);
1037 }
1038
1039 priv->chip->set_mirror_regs(priv);
1040
1041 mutex_unlock(&priv->reg_mutex);
1042 return 0;
1043 }
1044
1045 int
1046 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1047 {
1048 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1049 int i;
1050
1051 mutex_lock(&priv->reg_mutex);
1052 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1053 offsetof(struct ar8xxx_priv, vlan));
1054
1055 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1056 priv->vlan_id[i] = i;
1057
1058 /* Configure all ports */
1059 for (i = 0; i < dev->ports; i++)
1060 priv->chip->init_port(priv, i);
1061
1062 priv->mirror_rx = false;
1063 priv->mirror_tx = false;
1064 priv->source_port = 0;
1065 priv->monitor_port = 0;
1066
1067 priv->chip->init_globals(priv);
1068
1069 mutex_unlock(&priv->reg_mutex);
1070
1071 return ar8xxx_sw_hw_apply(dev);
1072 }
1073
1074 int
1075 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1076 const struct switch_attr *attr,
1077 struct switch_val *val)
1078 {
1079 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1080 unsigned int len;
1081 int ret;
1082
1083 if (!ar8xxx_has_mib_counters(priv))
1084 return -EOPNOTSUPP;
1085
1086 mutex_lock(&priv->mib_lock);
1087
1088 len = priv->dev.ports * priv->chip->num_mibs *
1089 sizeof(*priv->mib_stats);
1090 memset(priv->mib_stats, '\0', len);
1091 ret = ar8xxx_mib_flush(priv);
1092 if (ret)
1093 goto unlock;
1094
1095 ret = 0;
1096
1097 unlock:
1098 mutex_unlock(&priv->mib_lock);
1099 return ret;
1100 }
1101
1102 int
1103 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1104 const struct switch_attr *attr,
1105 struct switch_val *val)
1106 {
1107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1108
1109 mutex_lock(&priv->reg_mutex);
1110 priv->mirror_rx = !!val->value.i;
1111 priv->chip->set_mirror_regs(priv);
1112 mutex_unlock(&priv->reg_mutex);
1113
1114 return 0;
1115 }
1116
1117 int
1118 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1119 const struct switch_attr *attr,
1120 struct switch_val *val)
1121 {
1122 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1123 val->value.i = priv->mirror_rx;
1124 return 0;
1125 }
1126
1127 int
1128 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1129 const struct switch_attr *attr,
1130 struct switch_val *val)
1131 {
1132 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1133
1134 mutex_lock(&priv->reg_mutex);
1135 priv->mirror_tx = !!val->value.i;
1136 priv->chip->set_mirror_regs(priv);
1137 mutex_unlock(&priv->reg_mutex);
1138
1139 return 0;
1140 }
1141
1142 int
1143 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1144 const struct switch_attr *attr,
1145 struct switch_val *val)
1146 {
1147 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1148 val->value.i = priv->mirror_tx;
1149 return 0;
1150 }
1151
1152 int
1153 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1154 const struct switch_attr *attr,
1155 struct switch_val *val)
1156 {
1157 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1158
1159 mutex_lock(&priv->reg_mutex);
1160 priv->monitor_port = val->value.i;
1161 priv->chip->set_mirror_regs(priv);
1162 mutex_unlock(&priv->reg_mutex);
1163
1164 return 0;
1165 }
1166
1167 int
1168 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1169 const struct switch_attr *attr,
1170 struct switch_val *val)
1171 {
1172 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1173 val->value.i = priv->monitor_port;
1174 return 0;
1175 }
1176
1177 int
1178 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1179 const struct switch_attr *attr,
1180 struct switch_val *val)
1181 {
1182 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1183
1184 mutex_lock(&priv->reg_mutex);
1185 priv->source_port = val->value.i;
1186 priv->chip->set_mirror_regs(priv);
1187 mutex_unlock(&priv->reg_mutex);
1188
1189 return 0;
1190 }
1191
1192 int
1193 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1194 const struct switch_attr *attr,
1195 struct switch_val *val)
1196 {
1197 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1198 val->value.i = priv->source_port;
1199 return 0;
1200 }
1201
1202 static int
1203 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1204 const struct switch_attr *attr,
1205 struct switch_val *val)
1206 {
1207 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1208 int port;
1209 int ret;
1210
1211 if (!ar8xxx_has_mib_counters(priv))
1212 return -EOPNOTSUPP;
1213
1214 port = val->port_vlan;
1215 if (port >= dev->ports)
1216 return -EINVAL;
1217
1218 mutex_lock(&priv->mib_lock);
1219 ret = ar8xxx_mib_capture(priv);
1220 if (ret)
1221 goto unlock;
1222
1223 ar8xxx_mib_fetch_port_stat(priv, port, true);
1224
1225 ret = 0;
1226
1227 unlock:
1228 mutex_unlock(&priv->mib_lock);
1229 return ret;
1230 }
1231
1232 static int
1233 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1234 const struct switch_attr *attr,
1235 struct switch_val *val)
1236 {
1237 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1238 const struct ar8xxx_chip *chip = priv->chip;
1239 u64 *mib_stats;
1240 int port;
1241 int ret;
1242 char *buf = priv->buf;
1243 int i, len = 0;
1244
1245 if (!ar8xxx_has_mib_counters(priv))
1246 return -EOPNOTSUPP;
1247
1248 port = val->port_vlan;
1249 if (port >= dev->ports)
1250 return -EINVAL;
1251
1252 mutex_lock(&priv->mib_lock);
1253 ret = ar8xxx_mib_capture(priv);
1254 if (ret)
1255 goto unlock;
1256
1257 ar8xxx_mib_fetch_port_stat(priv, port, false);
1258
1259 len += snprintf(buf + len, sizeof(priv->buf) - len,
1260 "Port %d MIB counters\n",
1261 port);
1262
1263 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1264 for (i = 0; i < chip->num_mibs; i++)
1265 len += snprintf(buf + len, sizeof(priv->buf) - len,
1266 "%-12s: %llu\n",
1267 chip->mib_decs[i].name,
1268 mib_stats[i]);
1269
1270 val->value.s = buf;
1271 val->len = len;
1272
1273 ret = 0;
1274
1275 unlock:
1276 mutex_unlock(&priv->mib_lock);
1277 return ret;
1278 }
1279
1280 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1281 {
1282 .type = SWITCH_TYPE_INT,
1283 .name = "enable_vlan",
1284 .description = "Enable VLAN mode",
1285 .set = ar8xxx_sw_set_vlan,
1286 .get = ar8xxx_sw_get_vlan,
1287 .max = 1
1288 },
1289 {
1290 .type = SWITCH_TYPE_NOVAL,
1291 .name = "reset_mibs",
1292 .description = "Reset all MIB counters",
1293 .set = ar8xxx_sw_set_reset_mibs,
1294 },
1295 {
1296 .type = SWITCH_TYPE_INT,
1297 .name = "enable_mirror_rx",
1298 .description = "Enable mirroring of RX packets",
1299 .set = ar8xxx_sw_set_mirror_rx_enable,
1300 .get = ar8xxx_sw_get_mirror_rx_enable,
1301 .max = 1
1302 },
1303 {
1304 .type = SWITCH_TYPE_INT,
1305 .name = "enable_mirror_tx",
1306 .description = "Enable mirroring of TX packets",
1307 .set = ar8xxx_sw_set_mirror_tx_enable,
1308 .get = ar8xxx_sw_get_mirror_tx_enable,
1309 .max = 1
1310 },
1311 {
1312 .type = SWITCH_TYPE_INT,
1313 .name = "mirror_monitor_port",
1314 .description = "Mirror monitor port",
1315 .set = ar8xxx_sw_set_mirror_monitor_port,
1316 .get = ar8xxx_sw_get_mirror_monitor_port,
1317 .max = AR8216_NUM_PORTS - 1
1318 },
1319 {
1320 .type = SWITCH_TYPE_INT,
1321 .name = "mirror_source_port",
1322 .description = "Mirror source port",
1323 .set = ar8xxx_sw_set_mirror_source_port,
1324 .get = ar8xxx_sw_get_mirror_source_port,
1325 .max = AR8216_NUM_PORTS - 1
1326 },
1327 };
1328
1329 struct switch_attr ar8xxx_sw_attr_port[2] = {
1330 {
1331 .type = SWITCH_TYPE_NOVAL,
1332 .name = "reset_mib",
1333 .description = "Reset single port MIB counters",
1334 .set = ar8xxx_sw_set_port_reset_mib,
1335 },
1336 {
1337 .type = SWITCH_TYPE_STRING,
1338 .name = "mib",
1339 .description = "Get port's MIB counters",
1340 .set = NULL,
1341 .get = ar8xxx_sw_get_port_mib,
1342 },
1343 };
1344
1345 struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1346 {
1347 .type = SWITCH_TYPE_INT,
1348 .name = "vid",
1349 .description = "VLAN ID (0-4094)",
1350 .set = ar8xxx_sw_set_vid,
1351 .get = ar8xxx_sw_get_vid,
1352 .max = 4094,
1353 },
1354 };
1355
1356 static const struct switch_dev_ops ar8xxx_sw_ops = {
1357 .attr_global = {
1358 .attr = ar8xxx_sw_attr_globals,
1359 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1360 },
1361 .attr_port = {
1362 .attr = ar8xxx_sw_attr_port,
1363 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1364 },
1365 .attr_vlan = {
1366 .attr = ar8xxx_sw_attr_vlan,
1367 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1368 },
1369 .get_port_pvid = ar8xxx_sw_get_pvid,
1370 .set_port_pvid = ar8xxx_sw_set_pvid,
1371 .get_vlan_ports = ar8xxx_sw_get_ports,
1372 .set_vlan_ports = ar8xxx_sw_set_ports,
1373 .apply_config = ar8xxx_sw_hw_apply,
1374 .reset_switch = ar8xxx_sw_reset_switch,
1375 .get_port_link = ar8xxx_sw_get_port_link,
1376 };
1377
1378 static const struct ar8xxx_chip ar8216_chip = {
1379 .caps = AR8XXX_CAP_MIB_COUNTERS,
1380
1381 .reg_port_stats_start = 0x19000,
1382 .reg_port_stats_length = 0xa0,
1383
1384 .name = "Atheros AR8216",
1385 .ports = AR8216_NUM_PORTS,
1386 .vlans = AR8216_NUM_VLANS,
1387 .swops = &ar8xxx_sw_ops,
1388
1389 .hw_init = ar8216_hw_init,
1390 .init_globals = ar8216_init_globals,
1391 .init_port = ar8216_init_port,
1392 .setup_port = ar8216_setup_port,
1393 .read_port_status = ar8216_read_port_status,
1394 .atu_flush = ar8216_atu_flush,
1395 .vtu_flush = ar8216_vtu_flush,
1396 .vtu_load_vlan = ar8216_vtu_load_vlan,
1397 .set_mirror_regs = ar8216_set_mirror_regs,
1398
1399 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1400 .mib_decs = ar8216_mibs,
1401 .mib_func = AR8216_REG_MIB_FUNC
1402 };
1403
1404 static const struct ar8xxx_chip ar8236_chip = {
1405 .caps = AR8XXX_CAP_MIB_COUNTERS,
1406
1407 .reg_port_stats_start = 0x20000,
1408 .reg_port_stats_length = 0x100,
1409
1410 .name = "Atheros AR8236",
1411 .ports = AR8216_NUM_PORTS,
1412 .vlans = AR8216_NUM_VLANS,
1413 .swops = &ar8xxx_sw_ops,
1414
1415 .hw_init = ar8216_hw_init,
1416 .init_globals = ar8236_init_globals,
1417 .init_port = ar8216_init_port,
1418 .setup_port = ar8236_setup_port,
1419 .read_port_status = ar8216_read_port_status,
1420 .atu_flush = ar8216_atu_flush,
1421 .vtu_flush = ar8216_vtu_flush,
1422 .vtu_load_vlan = ar8216_vtu_load_vlan,
1423 .set_mirror_regs = ar8216_set_mirror_regs,
1424
1425 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1426 .mib_decs = ar8236_mibs,
1427 .mib_func = AR8216_REG_MIB_FUNC
1428 };
1429
1430 static const struct ar8xxx_chip ar8316_chip = {
1431 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1432
1433 .reg_port_stats_start = 0x20000,
1434 .reg_port_stats_length = 0x100,
1435
1436 .name = "Atheros AR8316",
1437 .ports = AR8216_NUM_PORTS,
1438 .vlans = AR8X16_MAX_VLANS,
1439 .swops = &ar8xxx_sw_ops,
1440
1441 .hw_init = ar8316_hw_init,
1442 .init_globals = ar8316_init_globals,
1443 .init_port = ar8216_init_port,
1444 .setup_port = ar8216_setup_port,
1445 .read_port_status = ar8216_read_port_status,
1446 .atu_flush = ar8216_atu_flush,
1447 .vtu_flush = ar8216_vtu_flush,
1448 .vtu_load_vlan = ar8216_vtu_load_vlan,
1449 .set_mirror_regs = ar8216_set_mirror_regs,
1450
1451 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1452 .mib_decs = ar8236_mibs,
1453 .mib_func = AR8216_REG_MIB_FUNC
1454 };
1455
1456 static int
1457 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1458 {
1459 u32 val;
1460 u16 id;
1461 int i;
1462
1463 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1464 if (val == ~0)
1465 return -ENODEV;
1466
1467 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1468 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1469 u16 t;
1470
1471 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1472 if (val == ~0)
1473 return -ENODEV;
1474
1475 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1476 if (t != id)
1477 return -ENODEV;
1478 }
1479
1480 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1481 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1482
1483 switch (priv->chip_ver) {
1484 case AR8XXX_VER_AR8216:
1485 priv->chip = &ar8216_chip;
1486 break;
1487 case AR8XXX_VER_AR8236:
1488 priv->chip = &ar8236_chip;
1489 break;
1490 case AR8XXX_VER_AR8316:
1491 priv->chip = &ar8316_chip;
1492 break;
1493 case AR8XXX_VER_AR8327:
1494 priv->chip = &ar8327_chip;
1495 break;
1496 case AR8XXX_VER_AR8337:
1497 priv->chip = &ar8337_chip;
1498 break;
1499 default:
1500 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1501 priv->chip_ver, priv->chip_rev);
1502
1503 return -ENODEV;
1504 }
1505
1506 return 0;
1507 }
1508
1509 static void
1510 ar8xxx_mib_work_func(struct work_struct *work)
1511 {
1512 struct ar8xxx_priv *priv;
1513 int err;
1514
1515 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1516
1517 mutex_lock(&priv->mib_lock);
1518
1519 err = ar8xxx_mib_capture(priv);
1520 if (err)
1521 goto next_port;
1522
1523 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1524
1525 next_port:
1526 priv->mib_next_port++;
1527 if (priv->mib_next_port >= priv->dev.ports)
1528 priv->mib_next_port = 0;
1529
1530 mutex_unlock(&priv->mib_lock);
1531 schedule_delayed_work(&priv->mib_work,
1532 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1533 }
1534
1535 static int
1536 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1537 {
1538 unsigned int len;
1539
1540 if (!ar8xxx_has_mib_counters(priv))
1541 return 0;
1542
1543 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1544
1545 len = priv->dev.ports * priv->chip->num_mibs *
1546 sizeof(*priv->mib_stats);
1547 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1548
1549 if (!priv->mib_stats)
1550 return -ENOMEM;
1551
1552 return 0;
1553 }
1554
1555 static void
1556 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1557 {
1558 if (!ar8xxx_has_mib_counters(priv))
1559 return;
1560
1561 schedule_delayed_work(&priv->mib_work,
1562 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1563 }
1564
1565 static void
1566 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1567 {
1568 if (!ar8xxx_has_mib_counters(priv))
1569 return;
1570
1571 cancel_delayed_work(&priv->mib_work);
1572 }
1573
1574 static struct ar8xxx_priv *
1575 ar8xxx_create(void)
1576 {
1577 struct ar8xxx_priv *priv;
1578
1579 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1580 if (priv == NULL)
1581 return NULL;
1582
1583 mutex_init(&priv->reg_mutex);
1584 mutex_init(&priv->mib_lock);
1585 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1586
1587 return priv;
1588 }
1589
1590 static void
1591 ar8xxx_free(struct ar8xxx_priv *priv)
1592 {
1593 if (priv->chip && priv->chip->cleanup)
1594 priv->chip->cleanup(priv);
1595
1596 kfree(priv->chip_data);
1597 kfree(priv->mib_stats);
1598 kfree(priv);
1599 }
1600
1601 static int
1602 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1603 {
1604 const struct ar8xxx_chip *chip;
1605 struct switch_dev *swdev;
1606 int ret;
1607
1608 ret = ar8xxx_id_chip(priv);
1609 if (ret)
1610 return ret;
1611
1612 chip = priv->chip;
1613
1614 swdev = &priv->dev;
1615 swdev->cpu_port = AR8216_PORT_CPU;
1616 swdev->name = chip->name;
1617 swdev->vlans = chip->vlans;
1618 swdev->ports = chip->ports;
1619 swdev->ops = chip->swops;
1620
1621 ret = ar8xxx_mib_init(priv);
1622 if (ret)
1623 return ret;
1624
1625 return 0;
1626 }
1627
1628 static int
1629 ar8xxx_start(struct ar8xxx_priv *priv)
1630 {
1631 int ret;
1632
1633 priv->init = true;
1634
1635 ret = priv->chip->hw_init(priv);
1636 if (ret)
1637 return ret;
1638
1639 ret = ar8xxx_sw_reset_switch(&priv->dev);
1640 if (ret)
1641 return ret;
1642
1643 priv->init = false;
1644
1645 ar8xxx_mib_start(priv);
1646
1647 return 0;
1648 }
1649
1650 static int
1651 ar8xxx_phy_config_init(struct phy_device *phydev)
1652 {
1653 struct ar8xxx_priv *priv = phydev->priv;
1654 struct net_device *dev = phydev->attached_dev;
1655 int ret;
1656
1657 if (WARN_ON(!priv))
1658 return -ENODEV;
1659
1660 if (priv->chip->config_at_probe)
1661 return ar8xxx_phy_check_aneg(phydev);
1662
1663 priv->phy = phydev;
1664
1665 if (phydev->addr != 0) {
1666 if (chip_is_ar8316(priv)) {
1667 /* switch device has been initialized, reinit */
1668 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1669 priv->initialized = false;
1670 priv->port4_phy = true;
1671 ar8316_hw_init(priv);
1672 return 0;
1673 }
1674
1675 return 0;
1676 }
1677
1678 ret = ar8xxx_start(priv);
1679 if (ret)
1680 return ret;
1681
1682 /* VID fixup only needed on ar8216 */
1683 if (chip_is_ar8216(priv)) {
1684 dev->phy_ptr = priv;
1685 dev->priv_flags |= IFF_NO_IP_ALIGN;
1686 dev->eth_mangle_rx = ar8216_mangle_rx;
1687 dev->eth_mangle_tx = ar8216_mangle_tx;
1688 }
1689
1690 return 0;
1691 }
1692
1693 static int
1694 ar8xxx_phy_read_status(struct phy_device *phydev)
1695 {
1696 struct ar8xxx_priv *priv = phydev->priv;
1697 struct switch_port_link link;
1698 int ret;
1699
1700 if (phydev->addr != 0)
1701 return genphy_read_status(phydev);
1702
1703 ar8216_read_port_link(priv, phydev->addr, &link);
1704 phydev->link = !!link.link;
1705 if (!phydev->link)
1706 return 0;
1707
1708 switch (link.speed) {
1709 case SWITCH_PORT_SPEED_10:
1710 phydev->speed = SPEED_10;
1711 break;
1712 case SWITCH_PORT_SPEED_100:
1713 phydev->speed = SPEED_100;
1714 break;
1715 case SWITCH_PORT_SPEED_1000:
1716 phydev->speed = SPEED_1000;
1717 break;
1718 default:
1719 phydev->speed = 0;
1720 }
1721 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1722
1723 /* flush the address translation unit */
1724 mutex_lock(&priv->reg_mutex);
1725 ret = priv->chip->atu_flush(priv);
1726 mutex_unlock(&priv->reg_mutex);
1727
1728 phydev->state = PHY_RUNNING;
1729 netif_carrier_on(phydev->attached_dev);
1730 phydev->adjust_link(phydev->attached_dev);
1731
1732 return ret;
1733 }
1734
1735 static int
1736 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1737 {
1738 if (phydev->addr == 0)
1739 return 0;
1740
1741 return genphy_config_aneg(phydev);
1742 }
1743
1744 static const u32 ar8xxx_phy_ids[] = {
1745 0x004dd033,
1746 0x004dd034, /* AR8327 */
1747 0x004dd036, /* AR8337 */
1748 0x004dd041,
1749 0x004dd042,
1750 0x004dd043, /* AR8236 */
1751 };
1752
1753 static bool
1754 ar8xxx_phy_match(u32 phy_id)
1755 {
1756 int i;
1757
1758 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1759 if (phy_id == ar8xxx_phy_ids[i])
1760 return true;
1761
1762 return false;
1763 }
1764
1765 static bool
1766 ar8xxx_is_possible(struct mii_bus *bus)
1767 {
1768 unsigned i;
1769
1770 for (i = 0; i < 4; i++) {
1771 u32 phy_id;
1772
1773 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1774 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1775 if (!ar8xxx_phy_match(phy_id)) {
1776 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1777 dev_name(&bus->dev), i, phy_id);
1778 return false;
1779 }
1780 }
1781
1782 return true;
1783 }
1784
1785 static int
1786 ar8xxx_phy_probe(struct phy_device *phydev)
1787 {
1788 struct ar8xxx_priv *priv;
1789 struct switch_dev *swdev;
1790 int ret;
1791
1792 /* skip PHYs at unused adresses */
1793 if (phydev->addr != 0 && phydev->addr != 4)
1794 return -ENODEV;
1795
1796 if (!ar8xxx_is_possible(phydev->bus))
1797 return -ENODEV;
1798
1799 mutex_lock(&ar8xxx_dev_list_lock);
1800 list_for_each_entry(priv, &ar8xxx_dev_list, list)
1801 if (priv->mii_bus == phydev->bus)
1802 goto found;
1803
1804 priv = ar8xxx_create();
1805 if (priv == NULL) {
1806 ret = -ENOMEM;
1807 goto unlock;
1808 }
1809
1810 priv->mii_bus = phydev->bus;
1811
1812 ret = ar8xxx_probe_switch(priv);
1813 if (ret)
1814 goto free_priv;
1815
1816 swdev = &priv->dev;
1817 swdev->alias = dev_name(&priv->mii_bus->dev);
1818 ret = register_switch(swdev, NULL);
1819 if (ret)
1820 goto free_priv;
1821
1822 pr_info("%s: %s rev. %u switch registered on %s\n",
1823 swdev->devname, swdev->name, priv->chip_rev,
1824 dev_name(&priv->mii_bus->dev));
1825
1826 found:
1827 priv->use_count++;
1828
1829 if (phydev->addr == 0) {
1830 if (ar8xxx_has_gige(priv)) {
1831 phydev->supported = SUPPORTED_1000baseT_Full;
1832 phydev->advertising = ADVERTISED_1000baseT_Full;
1833 } else {
1834 phydev->supported = SUPPORTED_100baseT_Full;
1835 phydev->advertising = ADVERTISED_100baseT_Full;
1836 }
1837
1838 if (priv->chip->config_at_probe) {
1839 priv->phy = phydev;
1840
1841 ret = ar8xxx_start(priv);
1842 if (ret)
1843 goto err_unregister_switch;
1844 }
1845 } else {
1846 if (ar8xxx_has_gige(priv)) {
1847 phydev->supported |= SUPPORTED_1000baseT_Full;
1848 phydev->advertising |= ADVERTISED_1000baseT_Full;
1849 }
1850 }
1851
1852 phydev->priv = priv;
1853
1854 list_add(&priv->list, &ar8xxx_dev_list);
1855
1856 mutex_unlock(&ar8xxx_dev_list_lock);
1857
1858 return 0;
1859
1860 err_unregister_switch:
1861 if (--priv->use_count)
1862 goto unlock;
1863
1864 unregister_switch(&priv->dev);
1865
1866 free_priv:
1867 ar8xxx_free(priv);
1868 unlock:
1869 mutex_unlock(&ar8xxx_dev_list_lock);
1870 return ret;
1871 }
1872
1873 static void
1874 ar8xxx_phy_detach(struct phy_device *phydev)
1875 {
1876 struct net_device *dev = phydev->attached_dev;
1877
1878 if (!dev)
1879 return;
1880
1881 dev->phy_ptr = NULL;
1882 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1883 dev->eth_mangle_rx = NULL;
1884 dev->eth_mangle_tx = NULL;
1885 }
1886
1887 static void
1888 ar8xxx_phy_remove(struct phy_device *phydev)
1889 {
1890 struct ar8xxx_priv *priv = phydev->priv;
1891
1892 if (WARN_ON(!priv))
1893 return;
1894
1895 phydev->priv = NULL;
1896 if (--priv->use_count > 0)
1897 return;
1898
1899 mutex_lock(&ar8xxx_dev_list_lock);
1900 list_del(&priv->list);
1901 mutex_unlock(&ar8xxx_dev_list_lock);
1902
1903 unregister_switch(&priv->dev);
1904 ar8xxx_mib_stop(priv);
1905 ar8xxx_free(priv);
1906 }
1907
1908 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1909 static int
1910 ar8xxx_phy_soft_reset(struct phy_device *phydev)
1911 {
1912 /* we don't need an extra reset */
1913 return 0;
1914 }
1915 #endif
1916
1917 static struct phy_driver ar8xxx_phy_driver = {
1918 .phy_id = 0x004d0000,
1919 .name = "Atheros AR8216/AR8236/AR8316",
1920 .phy_id_mask = 0xffff0000,
1921 .features = PHY_BASIC_FEATURES,
1922 .probe = ar8xxx_phy_probe,
1923 .remove = ar8xxx_phy_remove,
1924 .detach = ar8xxx_phy_detach,
1925 .config_init = ar8xxx_phy_config_init,
1926 .config_aneg = ar8xxx_phy_config_aneg,
1927 .read_status = ar8xxx_phy_read_status,
1928 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1929 .soft_reset = ar8xxx_phy_soft_reset,
1930 #endif
1931 .driver = { .owner = THIS_MODULE },
1932 };
1933
1934 int __init
1935 ar8xxx_init(void)
1936 {
1937 return phy_driver_register(&ar8xxx_phy_driver);
1938 }
1939
1940 void __exit
1941 ar8xxx_exit(void)
1942 {
1943 phy_driver_unregister(&ar8xxx_phy_driver);
1944 }
1945
1946 module_init(ar8xxx_init);
1947 module_exit(ar8xxx_exit);
1948 MODULE_LICENSE("GPL");
1949
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