target/linux/generic/files/drivers/net/phy/ar8327.c

   1 /*
   2  * ar8327.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/list.h>
  19 #include <linux/bitops.h>
  20 #include <linux/switch.h>
  21 #include <linux/delay.h>
  22 #include <linux/phy.h>
  23 #include <linux/lockdep.h>
  24 #include <linux/ar8216_platform.h>
  25 #include <linux/workqueue.h>
  26 #include <linux/of_device.h>
  27 #include <linux/leds.h>
  28
  29 #include "ar8216.h"
  30 #include "ar8327.h"
  31
  32 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
  33 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
  34
  35 static u32
  36 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
  37 {
  38         u32 t;
  39
  40         if (!cfg)
  41                 return 0;
  42
  43         t = 0;
  44         switch (cfg->mode) {
  45         case AR8327_PAD_NC:
  46                 break;
  47
  48         case AR8327_PAD_MAC2MAC_MII:
  49                 t = AR8327_PAD_MAC_MII_EN;
  50                 if (cfg->rxclk_sel)
  51                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
  52                 if (cfg->txclk_sel)
  53                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
  54                 break;
  55
  56         case AR8327_PAD_MAC2MAC_GMII:
  57                 t = AR8327_PAD_MAC_GMII_EN;
  58                 if (cfg->rxclk_sel)
  59                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
  60                 if (cfg->txclk_sel)
  61                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
  62                 break;
  63
  64         case AR8327_PAD_MAC_SGMII:
  65                 t = AR8327_PAD_SGMII_EN;
  66
  67                 /*
  68                  * WAR for the QUalcomm Atheros AP136 board.
  69                  * It seems that RGMII TX/RX delay settings needs to be
  70                  * applied for SGMII mode as well, The ethernet is not
  71                  * reliable without this.
  72                  */
  73                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  74                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  75                 if (cfg->rxclk_delay_en)
  76                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  77                 if (cfg->txclk_delay_en)
  78                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  79
  80                 if (cfg->sgmii_delay_en)
  81                         t |= AR8327_PAD_SGMII_DELAY_EN;
  82
  83                 break;
  84
  85         case AR8327_PAD_MAC2PHY_MII:
  86                 t = AR8327_PAD_PHY_MII_EN;
  87                 if (cfg->rxclk_sel)
  88                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
  89                 if (cfg->txclk_sel)
  90                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
  91                 break;
  92
  93         case AR8327_PAD_MAC2PHY_GMII:
  94                 t = AR8327_PAD_PHY_GMII_EN;
  95                 if (cfg->pipe_rxclk_sel)
  96                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
  97                 if (cfg->rxclk_sel)
  98                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
  99                 if (cfg->txclk_sel)
 100                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 101                 break;
 102
 103         case AR8327_PAD_MAC_RGMII:
 104                 t = AR8327_PAD_RGMII_EN;
 105                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 106                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 107                 if (cfg->rxclk_delay_en)
 108                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 109                 if (cfg->txclk_delay_en)
 110                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 111                 break;
 112
 113         case AR8327_PAD_PHY_GMII:
 114                 t = AR8327_PAD_PHYX_GMII_EN;
 115                 break;
 116
 117         case AR8327_PAD_PHY_RGMII:
 118                 t = AR8327_PAD_PHYX_RGMII_EN;
 119                 break;
 120
 121         case AR8327_PAD_PHY_MII:
 122                 t = AR8327_PAD_PHYX_MII_EN;
 123                 break;
 124         }
 125
 126         return t;
 127 }
 128
 129 static void
 130 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
 131 {
 132         switch (priv->chip_rev) {
 133         case 1:
 134                 /* For 100M waveform */
 135                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
 136                 /* Turn on Gigabit clock */
 137                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
 138                 break;
 139
 140         case 2:
 141                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
 142                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
 143                 /* fallthrough */
 144         case 4:
 145                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
 146                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
 147
 148                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
 149                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
 150                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
 151                 break;
 152         }
 153 }
 154
 155 static u32
 156 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
 157 {
 158         u32 t;
 159
 160         if (!cfg->force_link)
 161                 return AR8216_PORT_STATUS_LINK_AUTO;
 162
 163         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
 164         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
 165         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
 166         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
 167
 168         switch (cfg->speed) {
 169         case AR8327_PORT_SPEED_10:
 170                 t |= AR8216_PORT_SPEED_10M;
 171                 break;
 172         case AR8327_PORT_SPEED_100:
 173                 t |= AR8216_PORT_SPEED_100M;
 174                 break;
 175         case AR8327_PORT_SPEED_1000:
 176                 t |= AR8216_PORT_SPEED_1000M;
 177                 break;
 178         }
 179
 180         return t;
 181 }
 182
 183 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
 184         [_num] = { .reg = (_reg), .shift = (_shift) }
 185
 186 static const struct ar8327_led_entry
 187 ar8327_led_map[AR8327_NUM_LEDS] = {
 188         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
 189         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
 190         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
 191
 192         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
 193         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
 194         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
 195
 196         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
 197         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
 198         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
 199
 200         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
 201         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
 202         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
 203
 204         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
 205         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
 206         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
 207 };
 208
 209 static void
 210 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
 211                        enum ar8327_led_pattern pattern)
 212 {
 213         const struct ar8327_led_entry *entry;
 214
 215         entry = &ar8327_led_map[led_num];
 216         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
 217                    (3 << entry->shift), pattern << entry->shift);
 218 }
 219
 220 static void
 221 ar8327_led_work_func(struct work_struct *work)
 222 {
 223         struct ar8327_led *aled;
 224         u8 pattern;
 225
 226         aled = container_of(work, struct ar8327_led, led_work);
 227
 228         spin_lock(&aled->lock);
 229         pattern = aled->pattern;
 230         spin_unlock(&aled->lock);
 231
 232         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
 233                                pattern);
 234 }
 235
 236 static void
 237 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
 238 {
 239         if (aled->pattern == pattern)
 240                 return;
 241
 242         aled->pattern = pattern;
 243         schedule_work(&aled->led_work);
 244 }
 245
 246 static inline struct ar8327_led *
 247 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
 248 {
 249         return container_of(led_cdev, struct ar8327_led, cdev);
 250 }
 251
 252 static int
 253 ar8327_led_blink_set(struct led_classdev *led_cdev,
 254                      unsigned long *delay_on,
 255                      unsigned long *delay_off)
 256 {
 257         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 258
 259         if (*delay_on == 0 && *delay_off == 0) {
 260                 *delay_on = 125;
 261                 *delay_off = 125;
 262         }
 263
 264         if (*delay_on != 125 || *delay_off != 125) {
 265                 /*
 266                  * The hardware only supports blinking at 4Hz. Fall back
 267                  * to software implementation in other cases.
 268                  */
 269                 return -EINVAL;
 270         }
 271
 272         spin_lock(&aled->lock);
 273
 274         aled->enable_hw_mode = false;
 275         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
 276
 277         spin_unlock(&aled->lock);
 278
 279         return 0;
 280 }
 281
 282 static void
 283 ar8327_led_set_brightness(struct led_classdev *led_cdev,
 284                           enum led_brightness brightness)
 285 {
 286         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 287         u8 pattern;
 288         bool active;
 289
 290         active = (brightness != LED_OFF);
 291         active ^= aled->active_low;
 292
 293         pattern = (active) ? AR8327_LED_PATTERN_ON :
 294                              AR8327_LED_PATTERN_OFF;
 295
 296         spin_lock(&aled->lock);
 297
 298         aled->enable_hw_mode = false;
 299         ar8327_led_schedule_change(aled, pattern);
 300
 301         spin_unlock(&aled->lock);
 302 }
 303
 304 static ssize_t
 305 ar8327_led_enable_hw_mode_show(struct device *dev,
 306                                struct device_attribute *attr,
 307                                char *buf)
 308 {
 309         struct led_classdev *led_cdev = dev_get_drvdata(dev);
 310         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 311         ssize_t ret = 0;
 312
 313         spin_lock(&aled->lock);
 314         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
 315         spin_unlock(&aled->lock);
 316
 317         return ret;
 318 }
 319
 320 static ssize_t
 321 ar8327_led_enable_hw_mode_store(struct device *dev,
 322                                 struct device_attribute *attr,
 323                                 const char *buf,
 324                                 size_t size)
 325 {
 326         struct led_classdev *led_cdev = dev_get_drvdata(dev);
 327         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
 328         u8 pattern;
 329         u8 value;
 330         int ret;
 331
 332         ret = kstrtou8(buf, 10, &value);
 333         if (ret < 0)
 334                 return -EINVAL;
 335
 336         spin_lock(&aled->lock);
 337
 338         aled->enable_hw_mode = !!value;
 339         if (aled->enable_hw_mode)
 340                 pattern = AR8327_LED_PATTERN_RULE;
 341         else
 342                 pattern = AR8327_LED_PATTERN_OFF;
 343
 344         ar8327_led_schedule_change(aled, pattern);
 345
 346         spin_unlock(&aled->lock);
 347
 348         return size;
 349 }
 350
 351 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
 352                    ar8327_led_enable_hw_mode_show,
 353                    ar8327_led_enable_hw_mode_store);
 354
 355 static int
 356 ar8327_led_register(struct ar8327_led *aled)
 357 {
 358         int ret;
 359
 360         ret = led_classdev_register(NULL, &aled->cdev);
 361         if (ret < 0)
 362                 return ret;
 363
 364         if (aled->mode == AR8327_LED_MODE_HW) {
 365                 ret = device_create_file(aled->cdev.dev,
 366                                          &dev_attr_enable_hw_mode);
 367                 if (ret)
 368                         goto err_unregister;
 369         }
 370
 371         return 0;
 372
 373 err_unregister:
 374         led_classdev_unregister(&aled->cdev);
 375         return ret;
 376 }
 377
 378 static void
 379 ar8327_led_unregister(struct ar8327_led *aled)
 380 {
 381         if (aled->mode == AR8327_LED_MODE_HW)
 382                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
 383
 384         led_classdev_unregister(&aled->cdev);
 385         cancel_work_sync(&aled->led_work);
 386 }
 387
 388 static int
 389 ar8327_led_create(struct ar8xxx_priv *priv,
 390                   const struct ar8327_led_info *led_info)
 391 {
 392         struct ar8327_data *data = priv->chip_data;
 393         struct ar8327_led *aled;
 394         int ret;
 395
 396         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 397                 return 0;
 398
 399         if (!led_info->name)
 400                 return -EINVAL;
 401
 402         if (led_info->led_num >= AR8327_NUM_LEDS)
 403                 return -EINVAL;
 404
 405         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
 406                        GFP_KERNEL);
 407         if (!aled)
 408                 return -ENOMEM;
 409
 410         aled->sw_priv = priv;
 411         aled->led_num = led_info->led_num;
 412         aled->active_low = led_info->active_low;
 413         aled->mode = led_info->mode;
 414
 415         if (aled->mode == AR8327_LED_MODE_HW)
 416                 aled->enable_hw_mode = true;
 417
 418         aled->name = (char *)(aled + 1);
 419         strcpy(aled->name, led_info->name);
 420
 421         aled->cdev.name = aled->name;
 422         aled->cdev.brightness_set = ar8327_led_set_brightness;
 423         aled->cdev.blink_set = ar8327_led_blink_set;
 424         aled->cdev.default_trigger = led_info->default_trigger;
 425
 426         spin_lock_init(&aled->lock);
 427         mutex_init(&aled->mutex);
 428         INIT_WORK(&aled->led_work, ar8327_led_work_func);
 429
 430         ret = ar8327_led_register(aled);
 431         if (ret)
 432                 goto err_free;
 433
 434         data->leds[data->num_leds++] = aled;
 435
 436         return 0;
 437
 438 err_free:
 439         kfree(aled);
 440         return ret;
 441 }
 442
 443 static void
 444 ar8327_led_destroy(struct ar8327_led *aled)
 445 {
 446         ar8327_led_unregister(aled);
 447         kfree(aled);
 448 }
 449
 450 static void
 451 ar8327_leds_init(struct ar8xxx_priv *priv)
 452 {
 453         struct ar8327_data *data = priv->chip_data;
 454         unsigned i;
 455
 456         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 457                 return;
 458
 459         for (i = 0; i < data->num_leds; i++) {
 460                 struct ar8327_led *aled;
 461
 462                 aled = data->leds[i];
 463
 464                 if (aled->enable_hw_mode)
 465                         aled->pattern = AR8327_LED_PATTERN_RULE;
 466                 else
 467                         aled->pattern = AR8327_LED_PATTERN_OFF;
 468
 469                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
 470         }
 471 }
 472
 473 static void
 474 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
 475 {
 476         struct ar8327_data *data = priv->chip_data;
 477         unsigned i;
 478
 479         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
 480                 return;
 481
 482         for (i = 0; i < data->num_leds; i++) {
 483                 struct ar8327_led *aled;
 484
 485                 aled = data->leds[i];
 486                 ar8327_led_destroy(aled);
 487         }
 488
 489         kfree(data->leds);
 490 }
 491
 492 static int
 493 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
 494                        struct ar8327_platform_data *pdata)
 495 {
 496         struct ar8327_led_cfg *led_cfg;
 497         struct ar8327_data *data = priv->chip_data;
 498         u32 pos, new_pos;
 499         u32 t;
 500
 501         if (!pdata)
 502                 return -EINVAL;
 503
 504         priv->get_port_link = pdata->get_port_link;
 505
 506         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
 507         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
 508
 509         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
 510         if (chip_is_ar8337(priv))
 511                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
 512
 513         ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
 514         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
 515         ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
 516         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
 517         ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
 518
 519         pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
 520         new_pos = pos;
 521
 522         led_cfg = pdata->led_cfg;
 523         if (led_cfg) {
 524                 if (led_cfg->open_drain)
 525                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 526                 else
 527                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 528
 529                 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
 530                 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
 531                 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
 532                 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
 533
 534                 if (new_pos != pos)
 535                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
 536         }
 537
 538         if (pdata->sgmii_cfg) {
 539                 t = pdata->sgmii_cfg->sgmii_ctrl;
 540                 if (priv->chip_rev == 1)
 541                         t |= AR8327_SGMII_CTRL_EN_PLL |
 542                              AR8327_SGMII_CTRL_EN_RX |
 543                              AR8327_SGMII_CTRL_EN_TX;
 544                 else
 545                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
 546                                AR8327_SGMII_CTRL_EN_RX |
 547                                AR8327_SGMII_CTRL_EN_TX);
 548
 549                 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
 550
 551                 if (pdata->sgmii_cfg->serdes_aen)
 552                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
 553                 else
 554                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
 555         }
 556
 557         ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
 558
 559         if (pdata->leds && pdata->num_leds) {
 560                 int i;
 561
 562                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
 563                                      GFP_KERNEL);
 564                 if (!data->leds)
 565                         return -ENOMEM;
 566
 567                 for (i = 0; i < pdata->num_leds; i++)
 568                         ar8327_led_create(priv, &pdata->leds[i]);
 569         }
 570
 571         return 0;
 572 }
 573
 574 #ifdef CONFIG_OF
 575 static int
 576 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
 577 {
 578         struct ar8327_data *data = priv->chip_data;
 579         const __be32 *paddr;
 580         int len;
 581         int i;
 582
 583         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
 584         if (!paddr || len < (2 * sizeof(*paddr)))
 585                 return -EINVAL;
 586
 587         len /= sizeof(*paddr);
 588
 589         for (i = 0; i < len - 1; i += 2) {
 590                 u32 reg;
 591                 u32 val;
 592
 593                 reg = be32_to_cpup(paddr + i);
 594                 val = be32_to_cpup(paddr + i + 1);
 595
 596                 switch (reg) {
 597                 case AR8327_REG_PORT_STATUS(0):
 598                         data->port0_status = val;
 599                         break;
 600                 case AR8327_REG_PORT_STATUS(6):
 601                         data->port6_status = val;
 602                         break;
 603                 default:
 604                         ar8xxx_write(priv, reg, val);
 605                         break;
 606                 }
 607         }
 608
 609         return 0;
 610 }
 611 #else
 612 static inline int
 613 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
 614 {
 615         return -EINVAL;
 616 }
 617 #endif
 618
 619 static int
 620 ar8327_hw_init(struct ar8xxx_priv *priv)
 621 {
 622         int ret;
 623
 624         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
 625         if (!priv->chip_data)
 626                 return -ENOMEM;
 627
 628         if (priv->phy->dev.of_node)
 629                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
 630         else
 631                 ret = ar8327_hw_config_pdata(priv,
 632                                              priv->phy->dev.platform_data);
 633
 634         if (ret)
 635                 return ret;
 636
 637         ar8327_leds_init(priv);
 638
 639         ar8xxx_phy_init(priv);
 640
 641         return 0;
 642 }
 643
 644 static void
 645 ar8327_cleanup(struct ar8xxx_priv *priv)
 646 {
 647         ar8327_leds_cleanup(priv);
 648 }
 649
 650 static void
 651 ar8327_init_globals(struct ar8xxx_priv *priv)
 652 {
 653         struct ar8327_data *data = priv->chip_data;
 654         u32 t;
 655         int i;
 656
 657         /* enable CPU port and disable mirror port */
 658         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
 659             AR8327_FWD_CTRL0_MIRROR_PORT;
 660         ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
 661
 662         /* forward multicast and broadcast frames to CPU */
 663         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
 664             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
 665             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
 666         ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
 667
 668         /* enable jumbo frames */
 669         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
 670                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
 671
 672         /* Enable MIB counters */
 673         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
 674                        AR8327_MODULE_EN_MIB);
 675
 676         /* Disable EEE on all phy's due to stability issues */
 677         for (i = 0; i < AR8XXX_NUM_PHYS; i++)
 678                 data->eee[i] = false;
 679 }
 680
 681 static void
 682 ar8327_init_port(struct ar8xxx_priv *priv, int port)
 683 {
 684         struct ar8327_data *data = priv->chip_data;
 685         u32 t;
 686
 687         if (port == AR8216_PORT_CPU)
 688                 t = data->port0_status;
 689         else if (port == 6)
 690                 t = data->port6_status;
 691         else
 692                 t = AR8216_PORT_STATUS_LINK_AUTO;
 693
 694         ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
 695         ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
 696
 697         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
 698         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
 699         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
 700
 701         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
 702         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
 703
 704         t = AR8327_PORT_LOOKUP_LEARN;
 705         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
 706         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
 707 }
 708
 709 static u32
 710 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
 711 {
 712         return ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
 713 }
 714
 715 static int
 716 ar8327_atu_flush(struct ar8xxx_priv *priv)
 717 {
 718         int ret;
 719
 720         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
 721                               AR8327_ATU_FUNC_BUSY, 0);
 722         if (!ret)
 723                 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
 724                             AR8327_ATU_FUNC_OP_FLUSH);
 725
 726         return ret;
 727 }
 728
 729 static void
 730 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 731 {
 732         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
 733                             AR8327_VTU_FUNC1_BUSY, 0))
 734                 return;
 735
 736         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
 737                 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
 738
 739         op |= AR8327_VTU_FUNC1_BUSY;
 740         ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
 741 }
 742
 743 static void
 744 ar8327_vtu_flush(struct ar8xxx_priv *priv)
 745 {
 746         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
 747 }
 748
 749 static void
 750 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 751 {
 752         u32 op;
 753         u32 val;
 754         int i;
 755
 756         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
 757         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
 758         for (i = 0; i < AR8327_NUM_PORTS; i++) {
 759                 u32 mode;
 760
 761                 if ((port_mask & BIT(i)) == 0)
 762                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
 763                 else if (priv->vlan == 0)
 764                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
 765                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
 766                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
 767                 else
 768                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
 769
 770                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
 771         }
 772         ar8327_vtu_op(priv, op, val);
 773 }
 774
 775 static void
 776 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 777 {
 778         u32 t;
 779         u32 egress, ingress;
 780         u32 pvid = priv->vlan_id[priv->pvid[port]];
 781
 782         if (priv->vlan) {
 783                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
 784                 ingress = AR8216_IN_SECURE;
 785         } else {
 786                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
 787                 ingress = AR8216_IN_PORT_ONLY;
 788         }
 789
 790         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
 791         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
 792         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
 793
 794         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
 795         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
 796         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
 797
 798         t = members;
 799         t |= AR8327_PORT_LOOKUP_LEARN;
 800         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
 801         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
 802         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
 803 }
 804
 805 static int
 806 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 807 {
 808         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 809         u8 ports = priv->vlan_table[val->port_vlan];
 810         int i;
 811
 812         val->len = 0;
 813         for (i = 0; i < dev->ports; i++) {
 814                 struct switch_port *p;
 815
 816                 if (!(ports & (1 << i)))
 817                         continue;
 818
 819                 p = &val->value.ports[val->len++];
 820                 p->id = i;
 821                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
 822                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 823                 else
 824                         p->flags = 0;
 825         }
 826         return 0;
 827 }
 828
 829 static int
 830 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
 831 {
 832         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 833         u8 *vt = &priv->vlan_table[val->port_vlan];
 834         int i;
 835
 836         *vt = 0;
 837         for (i = 0; i < val->len; i++) {
 838                 struct switch_port *p = &val->value.ports[i];
 839
 840                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
 841                         if (val->port_vlan == priv->pvid[p->id]) {
 842                                 priv->vlan_tagged |= (1 << p->id);
 843                         }
 844                 } else {
 845                         priv->vlan_tagged &= ~(1 << p->id);
 846                         priv->pvid[p->id] = val->port_vlan;
 847                 }
 848
 849                 *vt |= 1 << p->id;
 850         }
 851         return 0;
 852 }
 853
 854 static void
 855 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
 856 {
 857         int port;
 858
 859         /* reset all mirror registers */
 860         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
 861                    AR8327_FWD_CTRL0_MIRROR_PORT,
 862                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
 863         for (port = 0; port < AR8327_NUM_PORTS; port++) {
 864                 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
 865                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
 866
 867                 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
 868                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
 869         }
 870
 871         /* now enable mirroring if necessary */
 872         if (priv->source_port >= AR8327_NUM_PORTS ||
 873             priv->monitor_port >= AR8327_NUM_PORTS ||
 874             priv->source_port == priv->monitor_port) {
 875                 return;
 876         }
 877
 878         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
 879                    AR8327_FWD_CTRL0_MIRROR_PORT,
 880                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
 881
 882         if (priv->mirror_rx)
 883                 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
 884                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
 885
 886         if (priv->mirror_tx)
 887                 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
 888                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
 889 }
 890
 891 static int
 892 ar8327_sw_set_eee(struct switch_dev *dev,
 893                   const struct switch_attr *attr,
 894                   struct switch_val *val)
 895 {
 896         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 897         struct ar8327_data *data = priv->chip_data;
 898         int port = val->port_vlan;
 899         int phy;
 900
 901         if (port >= dev->ports)
 902                 return -EINVAL;
 903         if (port == 0 || port == 6)
 904                 return -EOPNOTSUPP;
 905
 906         phy = port - 1;
 907
 908         data->eee[phy] = !!(val->value.i);
 909
 910         return 0;
 911 }
 912
 913 static int
 914 ar8327_sw_get_eee(struct switch_dev *dev,
 915                   const struct switch_attr *attr,
 916                   struct switch_val *val)
 917 {
 918         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 919         const struct ar8327_data *data = priv->chip_data;
 920         int port = val->port_vlan;
 921         int phy;
 922
 923         if (port >= dev->ports)
 924                 return -EINVAL;
 925         if (port == 0 || port == 6)
 926                 return -EOPNOTSUPP;
 927
 928         phy = port - 1;
 929
 930         val->value.i = data->eee[phy];
 931
 932         return 0;
 933 }
 934
 935 static int
 936 ar8327_sw_hw_apply(struct switch_dev *dev)
 937 {
 938         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 939         const struct ar8327_data *data = priv->chip_data;
 940         int ret, i;
 941
 942         ret = ar8xxx_sw_hw_apply(dev);
 943         if (ret)
 944                 return ret;
 945
 946         for (i=0; i < AR8XXX_NUM_PHYS; i++) {
 947                 if (data->eee[i])
 948                         ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
 949                                AR8327_EEE_CTRL_DISABLE_PHY(i));
 950                 else
 951                         ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
 952                                AR8327_EEE_CTRL_DISABLE_PHY(i));
 953         }
 954
 955         return 0;
 956 }
 957
 958 static const struct switch_attr ar8327_sw_attr_globals[] = {
 959         {
 960                 .type = SWITCH_TYPE_INT,
 961                 .name = "enable_vlan",
 962                 .description = "Enable VLAN mode",
 963                 .set = ar8xxx_sw_set_vlan,
 964                 .get = ar8xxx_sw_get_vlan,
 965                 .max = 1
 966         },
 967         {
 968                 .type = SWITCH_TYPE_NOVAL,
 969                 .name = "reset_mibs",
 970                 .description = "Reset all MIB counters",
 971                 .set = ar8xxx_sw_set_reset_mibs,
 972         },
 973         {
 974                 .type = SWITCH_TYPE_INT,
 975                 .name = "enable_mirror_rx",
 976                 .description = "Enable mirroring of RX packets",
 977                 .set = ar8xxx_sw_set_mirror_rx_enable,
 978                 .get = ar8xxx_sw_get_mirror_rx_enable,
 979                 .max = 1
 980         },
 981         {
 982                 .type = SWITCH_TYPE_INT,
 983                 .name = "enable_mirror_tx",
 984                 .description = "Enable mirroring of TX packets",
 985                 .set = ar8xxx_sw_set_mirror_tx_enable,
 986                 .get = ar8xxx_sw_get_mirror_tx_enable,
 987                 .max = 1
 988         },
 989         {
 990                 .type = SWITCH_TYPE_INT,
 991                 .name = "mirror_monitor_port",
 992                 .description = "Mirror monitor port",
 993                 .set = ar8xxx_sw_set_mirror_monitor_port,
 994                 .get = ar8xxx_sw_get_mirror_monitor_port,
 995                 .max = AR8327_NUM_PORTS - 1
 996         },
 997         {
 998                 .type = SWITCH_TYPE_INT,
 999                 .name = "mirror_source_port",
1000                 .description = "Mirror source port",
1001                 .set = ar8xxx_sw_set_mirror_source_port,
1002                 .get = ar8xxx_sw_get_mirror_source_port,
1003                 .max = AR8327_NUM_PORTS - 1
1004         },
1005 };
1006
1007 static const struct switch_attr ar8327_sw_attr_port[] = {
1008         {
1009                 .type = SWITCH_TYPE_NOVAL,
1010                 .name = "reset_mib",
1011                 .description = "Reset single port MIB counters",
1012                 .set = ar8xxx_sw_set_port_reset_mib,
1013         },
1014         {
1015                 .type = SWITCH_TYPE_STRING,
1016                 .name = "mib",
1017                 .description = "Get port's MIB counters",
1018                 .set = NULL,
1019                 .get = ar8xxx_sw_get_port_mib,
1020         },
1021         {
1022                 .type = SWITCH_TYPE_INT,
1023                 .name = "enable_eee",
1024                 .description = "Enable EEE PHY sleep mode",
1025                 .set = ar8327_sw_set_eee,
1026                 .get = ar8327_sw_get_eee,
1027                 .max = 1,
1028         },
1029 };
1030
1031 static const struct switch_dev_ops ar8327_sw_ops = {
1032         .attr_global = {
1033                 .attr = ar8327_sw_attr_globals,
1034                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1035         },
1036         .attr_port = {
1037                 .attr = ar8327_sw_attr_port,
1038                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1039         },
1040         .attr_vlan = {
1041                 .attr = ar8xxx_sw_attr_vlan,
1042                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1043         },
1044         .get_port_pvid = ar8xxx_sw_get_pvid,
1045         .set_port_pvid = ar8xxx_sw_set_pvid,
1046         .get_vlan_ports = ar8327_sw_get_ports,
1047         .set_vlan_ports = ar8327_sw_set_ports,
1048         .apply_config = ar8327_sw_hw_apply,
1049         .reset_switch = ar8xxx_sw_reset_switch,
1050         .get_port_link = ar8xxx_sw_get_port_link,
1051 };
1052
1053 const struct ar8xxx_chip ar8327_chip = {
1054         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1055         .config_at_probe = true,
1056         .mii_lo_first = true,
1057
1058         .name = "Atheros AR8327",
1059         .ports = AR8327_NUM_PORTS,
1060         .vlans = AR8X16_MAX_VLANS,
1061         .swops = &ar8327_sw_ops,
1062
1063         .reg_port_stats_start = 0x1000,
1064         .reg_port_stats_length = 0x100,
1065
1066         .hw_init = ar8327_hw_init,
1067         .cleanup = ar8327_cleanup,
1068         .init_globals = ar8327_init_globals,
1069         .init_port = ar8327_init_port,
1070         .setup_port = ar8327_setup_port,
1071         .read_port_status = ar8327_read_port_status,
1072         .atu_flush = ar8327_atu_flush,
1073         .vtu_flush = ar8327_vtu_flush,
1074         .vtu_load_vlan = ar8327_vtu_load_vlan,
1075         .phy_fixup = ar8327_phy_fixup,
1076         .set_mirror_regs = ar8327_set_mirror_regs,
1077         .sw_hw_apply = ar8327_sw_hw_apply,
1078
1079         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1080         .mib_decs = ar8236_mibs,
1081         .mib_func = AR8327_REG_MIB_FUNC
1082 };
1083
1084 const struct ar8xxx_chip ar8337_chip = {
1085         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1086         .config_at_probe = true,
1087         .mii_lo_first = true,
1088
1089         .name = "Atheros AR8337",
1090         .ports = AR8327_NUM_PORTS,
1091         .vlans = AR8X16_MAX_VLANS,
1092         .swops = &ar8327_sw_ops,
1093
1094         .reg_port_stats_start = 0x1000,
1095         .reg_port_stats_length = 0x100,
1096
1097         .hw_init = ar8327_hw_init,
1098         .cleanup = ar8327_cleanup,
1099         .init_globals = ar8327_init_globals,
1100         .init_port = ar8327_init_port,
1101         .setup_port = ar8327_setup_port,
1102         .read_port_status = ar8327_read_port_status,
1103         .atu_flush = ar8327_atu_flush,
1104         .vtu_flush = ar8327_vtu_flush,
1105         .vtu_load_vlan = ar8327_vtu_load_vlan,
1106         .phy_fixup = ar8327_phy_fixup,
1107         .set_mirror_regs = ar8327_set_mirror_regs,
1108         .sw_hw_apply = ar8327_sw_hw_apply,
1109
1110         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1111         .mib_decs = ar8236_mibs,
1112         .mib_func = AR8327_REG_MIB_FUNC
1113 };
1114