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generic: provide get_port_stats() on b53 switches
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/of.h>
28 #include <linux/of_net.h>
29 #include <linux/platform_data/b53.h>
30
31 #include "b53_regs.h"
32 #include "b53_priv.h"
33
34 /* buffer size needed for displaying all MIBs with max'd values */
35 #define B53_BUF_SIZE 1188
36
37 struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41 };
42
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77 { },
78 };
79
80 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
81 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
82
83 /* BCM63xx MIB counters */
84 static const struct b53_mib_desc b53_mibs_63xx[] = {
85 { 8, 0x00, "TxOctets" },
86 { 4, 0x08, "TxDropPkts" },
87 { 4, 0x0c, "TxQoSPkts" },
88 { 4, 0x10, "TxBroadcastPkts" },
89 { 4, 0x14, "TxMulticastPkts" },
90 { 4, 0x18, "TxUnicastPkts" },
91 { 4, 0x1c, "TxCollisions" },
92 { 4, 0x20, "TxSingleCollision" },
93 { 4, 0x24, "TxMultipleCollision" },
94 { 4, 0x28, "TxDeferredTransmit" },
95 { 4, 0x2c, "TxLateCollision" },
96 { 4, 0x30, "TxExcessiveCollision" },
97 { 4, 0x38, "TxPausePkts" },
98 { 8, 0x3c, "TxQoSOctets" },
99 { 8, 0x44, "RxOctets" },
100 { 4, 0x4c, "RxUndersizePkts" },
101 { 4, 0x50, "RxPausePkts" },
102 { 4, 0x54, "Pkts64Octets" },
103 { 4, 0x58, "Pkts65to127Octets" },
104 { 4, 0x5c, "Pkts128to255Octets" },
105 { 4, 0x60, "Pkts256to511Octets" },
106 { 4, 0x64, "Pkts512to1023Octets" },
107 { 4, 0x68, "Pkts1024to1522Octets" },
108 { 4, 0x6c, "RxOversizePkts" },
109 { 4, 0x70, "RxJabbers" },
110 { 4, 0x74, "RxAlignmentErrors" },
111 { 4, 0x78, "RxFCSErrors" },
112 { 8, 0x7c, "RxGoodOctets" },
113 { 4, 0x84, "RxDropPkts" },
114 { 4, 0x88, "RxUnicastPkts" },
115 { 4, 0x8c, "RxMulticastPkts" },
116 { 4, 0x90, "RxBroadcastPkts" },
117 { 4, 0x94, "RxSAChanges" },
118 { 4, 0x98, "RxFragments" },
119 { 4, 0xa0, "RxSymbolErrors" },
120 { 4, 0xa4, "RxQoSPkts" },
121 { 8, 0xa8, "RxQoSOctets" },
122 { 4, 0xb0, "Pkts1523to2047Octets" },
123 { 4, 0xb4, "Pkts2048to4095Octets" },
124 { 4, 0xb8, "Pkts4096to8191Octets" },
125 { 4, 0xbc, "Pkts8192to9728Octets" },
126 { 4, 0xc0, "RxDiscarded" },
127 { }
128 };
129
130 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
131 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
132
133 /* MIB counters */
134 static const struct b53_mib_desc b53_mibs[] = {
135 { 8, 0x00, "TxOctets" },
136 { 4, 0x08, "TxDropPkts" },
137 { 4, 0x10, "TxBroadcastPkts" },
138 { 4, 0x14, "TxMulticastPkts" },
139 { 4, 0x18, "TxUnicastPkts" },
140 { 4, 0x1c, "TxCollisions" },
141 { 4, 0x20, "TxSingleCollision" },
142 { 4, 0x24, "TxMultipleCollision" },
143 { 4, 0x28, "TxDeferredTransmit" },
144 { 4, 0x2c, "TxLateCollision" },
145 { 4, 0x30, "TxExcessiveCollision" },
146 { 4, 0x38, "TxPausePkts" },
147 { 8, 0x50, "RxOctets" },
148 { 4, 0x58, "RxUndersizePkts" },
149 { 4, 0x5c, "RxPausePkts" },
150 { 4, 0x60, "Pkts64Octets" },
151 { 4, 0x64, "Pkts65to127Octets" },
152 { 4, 0x68, "Pkts128to255Octets" },
153 { 4, 0x6c, "Pkts256to511Octets" },
154 { 4, 0x70, "Pkts512to1023Octets" },
155 { 4, 0x74, "Pkts1024to1522Octets" },
156 { 4, 0x78, "RxOversizePkts" },
157 { 4, 0x7c, "RxJabbers" },
158 { 4, 0x80, "RxAlignmentErrors" },
159 { 4, 0x84, "RxFCSErrors" },
160 { 8, 0x88, "RxGoodOctets" },
161 { 4, 0x90, "RxDropPkts" },
162 { 4, 0x94, "RxUnicastPkts" },
163 { 4, 0x98, "RxMulticastPkts" },
164 { 4, 0x9c, "RxBroadcastPkts" },
165 { 4, 0xa0, "RxSAChanges" },
166 { 4, 0xa4, "RxFragments" },
167 { 4, 0xa8, "RxJumboPkts" },
168 { 4, 0xac, "RxSymbolErrors" },
169 { 4, 0xc0, "RxDiscarded" },
170 { }
171 };
172
173 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
174 {
175 unsigned int i;
176
177 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
178
179 for (i = 0; i < 10; i++) {
180 u8 vta;
181
182 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
183 if (!(vta & VTA_START_CMD))
184 return 0;
185
186 usleep_range(100, 200);
187 }
188
189 return -EIO;
190 }
191
192 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
193 u16 untag)
194 {
195 if (is5325(dev)) {
196 u32 entry = 0;
197
198 if (members) {
199 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
200 members;
201 if (dev->core_rev >= 3)
202 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
203 else
204 entry |= VA_VALID_25;
205 }
206
207 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
208 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
209 VTA_RW_STATE_WR | VTA_RW_OP_EN);
210 } else if (is5365(dev)) {
211 u16 entry = 0;
212
213 if (members)
214 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
215 members | VA_VALID_65;
216
217 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
218 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
219 VTA_RW_STATE_WR | VTA_RW_OP_EN);
220 } else {
221 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
222 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
223 (untag << VTE_UNTAG_S) | members);
224
225 b53_do_vlan_op(dev, VTA_CMD_WRITE);
226 }
227 }
228
229 void b53_set_forwarding(struct b53_device *dev, int enable)
230 {
231 u8 mgmt;
232
233 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
234
235 if (enable)
236 mgmt |= SM_SW_FWD_EN;
237 else
238 mgmt &= ~SM_SW_FWD_EN;
239
240 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
241 }
242
243 static void b53_enable_vlan(struct b53_device *dev, int enable)
244 {
245 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
246
247 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
250
251 if (is5325(dev) || is5365(dev)) {
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
254 } else if (is63xx(dev)) {
255 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
256 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
257 } else {
258 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
259 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
260 }
261
262 mgmt &= ~SM_SW_FWD_MODE;
263
264 if (enable) {
265 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
266 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
267 vc4 &= ~VC4_ING_VID_CHECK_MASK;
268 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
269 vc5 |= VC5_DROP_VTABLE_MISS;
270
271 if (is5325(dev))
272 vc0 &= ~VC0_RESERVED_1;
273
274 if (is5325(dev) || is5365(dev))
275 vc1 |= VC1_RX_MCST_TAG_EN;
276
277 if (!is5325(dev) && !is5365(dev)) {
278 if (dev->allow_vid_4095)
279 vc5 |= VC5_VID_FFF_EN;
280 else
281 vc5 &= ~VC5_VID_FFF_EN;
282 }
283 } else {
284 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
285 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
286 vc4 &= ~VC4_ING_VID_CHECK_MASK;
287 vc5 &= ~VC5_DROP_VTABLE_MISS;
288
289 if (is5325(dev) || is5365(dev))
290 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
291 else
292 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
293
294 if (is5325(dev) || is5365(dev))
295 vc1 &= ~VC1_RX_MCST_TAG_EN;
296
297 if (!is5325(dev) && !is5365(dev))
298 vc5 &= ~VC5_VID_FFF_EN;
299 }
300
301 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
303
304 if (is5325(dev) || is5365(dev)) {
305 /* enable the high 8 bit vid check on 5325 */
306 if (is5325(dev) && enable)
307 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
308 VC3_HIGH_8BIT_EN);
309 else
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
311
312 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
314 } else if (is63xx(dev)) {
315 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
316 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
318 } else {
319 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
320 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
321 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
322 }
323
324 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
325 }
326
327 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
328 {
329 u32 port_mask = 0;
330 u16 max_size = JMS_MIN_SIZE;
331
332 if (is5325(dev) || is5365(dev))
333 return -EINVAL;
334
335 if (enable) {
336 port_mask = dev->enabled_ports;
337 max_size = JMS_MAX_SIZE;
338 if (allow_10_100)
339 port_mask |= JPM_10_100_JUMBO_EN;
340 }
341
342 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
343 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
344 }
345
346 static int b53_flush_arl(struct b53_device *dev)
347 {
348 unsigned int i;
349
350 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
351 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
352
353 for (i = 0; i < 10; i++) {
354 u8 fast_age_ctrl;
355
356 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
357 &fast_age_ctrl);
358
359 if (!(fast_age_ctrl & FAST_AGE_DONE))
360 return 0;
361
362 mdelay(1);
363 }
364
365 pr_warn("time out while flushing ARL\n");
366
367 return -EINVAL;
368 }
369
370 static void b53_enable_ports(struct b53_device *dev)
371 {
372 unsigned i;
373
374 b53_for_each_port(dev, i) {
375 u8 port_ctrl;
376 u16 pvlan_mask;
377
378 /*
379 * prevent leaking packets between wan and lan in unmanaged
380 * mode through port vlans.
381 */
382 if (dev->enable_vlan || is_cpu_port(dev, i))
383 pvlan_mask = 0x1ff;
384 else if (is531x5(dev) || is5301x(dev))
385 /* BCM53115 may use a different port as cpu port */
386 pvlan_mask = BIT(dev->sw_dev.cpu_port);
387 else
388 pvlan_mask = BIT(B53_CPU_PORT);
389
390 /* BCM5325 CPU port is at 8 */
391 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
392 i = B53_CPU_PORT;
393
394 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
395 /* disable unused ports 6 & 7 */
396 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
397 else if (i == B53_CPU_PORT)
398 port_ctrl = PORT_CTRL_RX_BCST_EN |
399 PORT_CTRL_RX_MCST_EN |
400 PORT_CTRL_RX_UCST_EN;
401 else
402 port_ctrl = 0;
403
404 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
405 pvlan_mask);
406
407 /* port state is handled by bcm63xx_enet driver */
408 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
409 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
410 port_ctrl);
411 }
412 }
413
414 static void b53_enable_mib(struct b53_device *dev)
415 {
416 u8 gc;
417
418 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
419
420 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
421
422 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
423 }
424
425 static int b53_apply(struct b53_device *dev)
426 {
427 int i;
428
429 /* clear all vlan entries */
430 if (is5325(dev) || is5365(dev)) {
431 for (i = 1; i < dev->sw_dev.vlans; i++)
432 b53_set_vlan_entry(dev, i, 0, 0);
433 } else {
434 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
435 }
436
437 b53_enable_vlan(dev, dev->enable_vlan);
438
439 /* fill VLAN table */
440 if (dev->enable_vlan) {
441 for (i = 0; i < dev->sw_dev.vlans; i++) {
442 struct b53_vlan *vlan = &dev->vlans[i];
443
444 if (!vlan->members)
445 continue;
446
447 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
448 }
449
450 b53_for_each_port(dev, i)
451 b53_write16(dev, B53_VLAN_PAGE,
452 B53_VLAN_PORT_DEF_TAG(i),
453 dev->ports[i].pvid);
454 } else {
455 b53_for_each_port(dev, i)
456 b53_write16(dev, B53_VLAN_PAGE,
457 B53_VLAN_PORT_DEF_TAG(i), 1);
458
459 }
460
461 b53_enable_ports(dev);
462
463 if (!is5325(dev) && !is5365(dev))
464 b53_set_jumbo(dev, dev->enable_jumbo, 1);
465
466 return 0;
467 }
468
469 static void b53_switch_reset_gpio(struct b53_device *dev)
470 {
471 int gpio = dev->reset_gpio;
472
473 if (gpio < 0)
474 return;
475
476 /*
477 * Reset sequence: RESET low(50ms)->high(20ms)
478 */
479 gpio_set_value(gpio, 0);
480 mdelay(50);
481
482 gpio_set_value(gpio, 1);
483 mdelay(20);
484
485 dev->current_page = 0xff;
486 }
487
488 static int b53_configure_ports_of(struct b53_device *dev)
489 {
490 struct device_node *dn, *pn;
491 u32 port_num;
492
493 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
494
495 for_each_available_child_of_node(dn, pn) {
496 struct device_node *fixed_link;
497
498 if (of_property_read_u32(pn, "reg", &port_num))
499 continue;
500
501 if (port_num > B53_CPU_PORT)
502 continue;
503
504 fixed_link = of_get_child_by_name(pn, "fixed-link");
505 if (fixed_link) {
506 u32 spd;
507 u8 po = GMII_PO_LINK;
508 int mode = of_get_phy_mode(pn);
509
510 if (!of_property_read_u32(fixed_link, "speed", &spd)) {
511 switch (spd) {
512 case 10:
513 po |= GMII_PO_SPEED_10M;
514 break;
515 case 100:
516 po |= GMII_PO_SPEED_100M;
517 break;
518 case 2000:
519 if (is_imp_port(dev, port_num))
520 po |= PORT_OVERRIDE_SPEED_2000M;
521 else
522 po |= GMII_PO_SPEED_2000M;
523 /* fall through */
524 case 1000:
525 po |= GMII_PO_SPEED_1000M;
526 break;
527 }
528 }
529
530 if (of_property_read_bool(fixed_link, "full-duplex"))
531 po |= PORT_OVERRIDE_FULL_DUPLEX;
532 if (of_property_read_bool(fixed_link, "pause"))
533 po |= GMII_PO_RX_FLOW;
534 if (of_property_read_bool(fixed_link, "asym-pause"))
535 po |= GMII_PO_TX_FLOW;
536
537 if (is_imp_port(dev, port_num)) {
538 po |= PORT_OVERRIDE_EN;
539
540 if (is5325(dev) &&
541 mode == PHY_INTERFACE_MODE_REVMII)
542 po |= PORT_OVERRIDE_RV_MII_25;
543
544 b53_write8(dev, B53_CTRL_PAGE,
545 B53_PORT_OVERRIDE_CTRL, po);
546
547 if (is5325(dev) &&
548 mode == PHY_INTERFACE_MODE_REVMII) {
549 b53_read8(dev, B53_CTRL_PAGE,
550 B53_PORT_OVERRIDE_CTRL, &po);
551 if (!(po & PORT_OVERRIDE_RV_MII_25))
552 pr_err("Failed to enable reverse MII mode\n");
553 return -EINVAL;
554 }
555 } else {
556 po |= GMII_PO_EN;
557 b53_write8(dev, B53_CTRL_PAGE,
558 B53_GMII_PORT_OVERRIDE_CTRL(port_num),
559 po);
560 }
561 }
562 }
563
564 return 0;
565 }
566
567 static int b53_configure_ports(struct b53_device *dev)
568 {
569 u8 cpu_port = dev->sw_dev.cpu_port;
570
571 /* configure MII port if necessary */
572 if (is5325(dev)) {
573 u8 mii_port_override;
574
575 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
576 &mii_port_override);
577 /* reverse mii needs to be enabled */
578 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
579 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
580 mii_port_override | PORT_OVERRIDE_RV_MII_25);
581 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
582 &mii_port_override);
583
584 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
585 pr_err("Failed to enable reverse MII mode\n");
586 return -EINVAL;
587 }
588 }
589 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
590 u8 mii_port_override;
591
592 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
593 &mii_port_override);
594 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
595 mii_port_override | PORT_OVERRIDE_EN |
596 PORT_OVERRIDE_LINK);
597
598 /* BCM47189 has another interface connected to the port 5 */
599 if (dev->enabled_ports & BIT(5)) {
600 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
601 u8 gmii_po;
602
603 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
604 gmii_po |= GMII_PO_LINK |
605 GMII_PO_RX_FLOW |
606 GMII_PO_TX_FLOW |
607 GMII_PO_EN;
608 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
609 }
610 } else if (is5301x(dev)) {
611 if (cpu_port == 8) {
612 u8 mii_port_override;
613
614 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
615 &mii_port_override);
616 mii_port_override |= PORT_OVERRIDE_LINK |
617 PORT_OVERRIDE_RX_FLOW |
618 PORT_OVERRIDE_TX_FLOW |
619 PORT_OVERRIDE_SPEED_2000M |
620 PORT_OVERRIDE_EN;
621 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
622 mii_port_override);
623
624 /* TODO: Ports 5 & 7 require some extra handling */
625 } else {
626 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
627 u8 gmii_po;
628
629 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
630 gmii_po |= GMII_PO_LINK |
631 GMII_PO_RX_FLOW |
632 GMII_PO_TX_FLOW |
633 GMII_PO_EN |
634 GMII_PO_SPEED_2000M;
635 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
636 }
637 }
638
639 return 0;
640 }
641
642 static int b53_switch_reset(struct b53_device *dev)
643 {
644 int ret = 0;
645 u8 mgmt;
646
647 b53_switch_reset_gpio(dev);
648
649 if (is539x(dev)) {
650 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
651 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
652 }
653
654 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
655
656 if (!(mgmt & SM_SW_FWD_EN)) {
657 mgmt &= ~SM_SW_FWD_MODE;
658 mgmt |= SM_SW_FWD_EN;
659
660 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
661 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
662
663 if (!(mgmt & SM_SW_FWD_EN)) {
664 pr_err("Failed to enable switch!\n");
665 return -EINVAL;
666 }
667 }
668
669 /* enable all ports */
670 b53_enable_ports(dev);
671
672 if (dev->dev->of_node)
673 ret = b53_configure_ports_of(dev);
674 else
675 ret = b53_configure_ports(dev);
676
677 if (ret)
678 return ret;
679
680 b53_enable_mib(dev);
681
682 return b53_flush_arl(dev);
683 }
684
685 /*
686 * Swconfig glue functions
687 */
688
689 static int b53_global_get_vlan_enable(struct switch_dev *dev,
690 const struct switch_attr *attr,
691 struct switch_val *val)
692 {
693 struct b53_device *priv = sw_to_b53(dev);
694
695 val->value.i = priv->enable_vlan;
696
697 return 0;
698 }
699
700 static int b53_global_set_vlan_enable(struct switch_dev *dev,
701 const struct switch_attr *attr,
702 struct switch_val *val)
703 {
704 struct b53_device *priv = sw_to_b53(dev);
705
706 priv->enable_vlan = val->value.i;
707
708 return 0;
709 }
710
711 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
712 const struct switch_attr *attr,
713 struct switch_val *val)
714 {
715 struct b53_device *priv = sw_to_b53(dev);
716
717 val->value.i = priv->enable_jumbo;
718
719 return 0;
720 }
721
722 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
723 const struct switch_attr *attr,
724 struct switch_val *val)
725 {
726 struct b53_device *priv = sw_to_b53(dev);
727
728 priv->enable_jumbo = val->value.i;
729
730 return 0;
731 }
732
733 static int b53_global_get_4095_enable(struct switch_dev *dev,
734 const struct switch_attr *attr,
735 struct switch_val *val)
736 {
737 struct b53_device *priv = sw_to_b53(dev);
738
739 val->value.i = priv->allow_vid_4095;
740
741 return 0;
742 }
743
744 static int b53_global_set_4095_enable(struct switch_dev *dev,
745 const struct switch_attr *attr,
746 struct switch_val *val)
747 {
748 struct b53_device *priv = sw_to_b53(dev);
749
750 priv->allow_vid_4095 = val->value.i;
751
752 return 0;
753 }
754
755 static int b53_global_get_ports(struct switch_dev *dev,
756 const struct switch_attr *attr,
757 struct switch_val *val)
758 {
759 struct b53_device *priv = sw_to_b53(dev);
760
761 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
762 priv->enabled_ports);
763 val->value.s = priv->buf;
764
765 return 0;
766 }
767
768 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
769 {
770 struct b53_device *priv = sw_to_b53(dev);
771
772 *val = priv->ports[port].pvid;
773
774 return 0;
775 }
776
777 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
778 {
779 struct b53_device *priv = sw_to_b53(dev);
780
781 if (val > 15 && is5325(priv))
782 return -EINVAL;
783 if (val == 4095 && !priv->allow_vid_4095)
784 return -EINVAL;
785
786 priv->ports[port].pvid = val;
787
788 return 0;
789 }
790
791 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
792 {
793 struct b53_device *priv = sw_to_b53(dev);
794 struct switch_port *port = &val->value.ports[0];
795 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
796 int i;
797
798 val->len = 0;
799
800 if (!vlan->members)
801 return 0;
802
803 for (i = 0; i < dev->ports; i++) {
804 if (!(vlan->members & BIT(i)))
805 continue;
806
807
808 if (!(vlan->untag & BIT(i)))
809 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
810 else
811 port->flags = 0;
812
813 port->id = i;
814 val->len++;
815 port++;
816 }
817
818 return 0;
819 }
820
821 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
822 {
823 struct b53_device *priv = sw_to_b53(dev);
824 struct switch_port *port;
825 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
826 int i;
827
828 /* only BCM5325 and BCM5365 supports VID 0 */
829 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
830 return -EINVAL;
831
832 /* VLAN 4095 needs special handling */
833 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
834 return -EINVAL;
835
836 port = &val->value.ports[0];
837 vlan->members = 0;
838 vlan->untag = 0;
839 for (i = 0; i < val->len; i++, port++) {
840 vlan->members |= BIT(port->id);
841
842 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
843 vlan->untag |= BIT(port->id);
844 priv->ports[port->id].pvid = val->port_vlan;
845 };
846 }
847
848 /* ignore disabled ports */
849 vlan->members &= priv->enabled_ports;
850 vlan->untag &= priv->enabled_ports;
851
852 return 0;
853 }
854
855 static int b53_port_get_link(struct switch_dev *dev, int port,
856 struct switch_port_link *link)
857 {
858 struct b53_device *priv = sw_to_b53(dev);
859
860 if (is_cpu_port(priv, port)) {
861 link->link = 1;
862 link->duplex = 1;
863 link->speed = is5325(priv) || is5365(priv) ?
864 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
865 link->aneg = 0;
866 } else if (priv->enabled_ports & BIT(port)) {
867 u32 speed;
868 u16 lnk, duplex;
869
870 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
871 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
872
873 lnk = (lnk >> port) & 1;
874 duplex = (duplex >> port) & 1;
875
876 if (is5325(priv) || is5365(priv)) {
877 u16 tmp;
878
879 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
880 speed = SPEED_PORT_FE(tmp, port);
881 } else {
882 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
883 speed = SPEED_PORT_GE(speed, port);
884 }
885
886 link->link = lnk;
887 if (lnk) {
888 link->duplex = duplex;
889 switch (speed) {
890 case SPEED_STAT_10M:
891 link->speed = SWITCH_PORT_SPEED_10;
892 break;
893 case SPEED_STAT_100M:
894 link->speed = SWITCH_PORT_SPEED_100;
895 break;
896 case SPEED_STAT_1000M:
897 link->speed = SWITCH_PORT_SPEED_1000;
898 break;
899 }
900 }
901
902 link->aneg = 1;
903 } else {
904 link->link = 0;
905 }
906
907 return 0;
908
909 }
910
911 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
912 struct switch_port_link *link)
913 {
914 struct b53_device *dev = sw_to_b53(sw_dev);
915
916 /*
917 * TODO: BCM63XX requires special handling as it can have external phys
918 * and ports might be GE or only FE
919 */
920 if (is63xx(dev))
921 return -ENOTSUPP;
922
923 if (port == sw_dev->cpu_port)
924 return -EINVAL;
925
926 if (!(BIT(port) & dev->enabled_ports))
927 return -EINVAL;
928
929 if (link->speed == SWITCH_PORT_SPEED_1000 &&
930 (is5325(dev) || is5365(dev)))
931 return -EINVAL;
932
933 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
934 return -EINVAL;
935
936 return switch_generic_set_link(sw_dev, port, link);
937 }
938
939 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
940 {
941 struct b53_device *priv = sw_to_b53(dev);
942
943 if (priv->ops->phy_read16)
944 return priv->ops->phy_read16(priv, addr, reg, value);
945
946 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
947 }
948
949 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
950 {
951 struct b53_device *priv = sw_to_b53(dev);
952
953 if (priv->ops->phy_write16)
954 return priv->ops->phy_write16(priv, addr, reg, value);
955
956 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
957 }
958
959 static int b53_global_reset_switch(struct switch_dev *dev)
960 {
961 struct b53_device *priv = sw_to_b53(dev);
962
963 /* reset vlans */
964 priv->enable_vlan = 0;
965 priv->enable_jumbo = 0;
966 priv->allow_vid_4095 = 0;
967
968 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
969 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
970
971 return b53_switch_reset(priv);
972 }
973
974 static int b53_global_apply_config(struct switch_dev *dev)
975 {
976 struct b53_device *priv = sw_to_b53(dev);
977
978 /* disable switching */
979 b53_set_forwarding(priv, 0);
980
981 b53_apply(priv);
982
983 /* enable switching */
984 b53_set_forwarding(priv, 1);
985
986 return 0;
987 }
988
989
990 static int b53_global_reset_mib(struct switch_dev *dev,
991 const struct switch_attr *attr,
992 struct switch_val *val)
993 {
994 struct b53_device *priv = sw_to_b53(dev);
995 u8 gc;
996
997 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
998
999 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1000 mdelay(1);
1001 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1002 mdelay(1);
1003
1004 return 0;
1005 }
1006
1007 static int b53_port_get_mib(struct switch_dev *sw_dev,
1008 const struct switch_attr *attr,
1009 struct switch_val *val)
1010 {
1011 struct b53_device *dev = sw_to_b53(sw_dev);
1012 const struct b53_mib_desc *mibs;
1013 int port = val->port_vlan;
1014 int len = 0;
1015
1016 if (!(BIT(port) & dev->enabled_ports))
1017 return -1;
1018
1019 if (is5365(dev)) {
1020 if (port == 5)
1021 port = 8;
1022
1023 mibs = b53_mibs_65;
1024 } else if (is63xx(dev)) {
1025 mibs = b53_mibs_63xx;
1026 } else {
1027 mibs = b53_mibs;
1028 }
1029
1030 dev->buf[0] = 0;
1031
1032 for (; mibs->size > 0; mibs++) {
1033 u64 val;
1034
1035 if (mibs->size == 8) {
1036 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
1037 } else {
1038 u32 val32;
1039
1040 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
1041 &val32);
1042 val = val32;
1043 }
1044
1045 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
1046 "%-20s: %llu\n", mibs->name, val);
1047 }
1048
1049 val->len = len;
1050 val->value.s = dev->buf;
1051
1052 return 0;
1053 }
1054
1055 static int b53_port_get_stats(struct switch_dev *sw_dev, int port,
1056 struct switch_port_stats *stats)
1057 {
1058 struct b53_device *dev = sw_to_b53(sw_dev);
1059 const struct b53_mib_desc *mibs;
1060 int txb_id, rxb_id;
1061 u64 rxb, txb;
1062
1063 if (!(BIT(port) & dev->enabled_ports))
1064 return -EINVAL;
1065
1066 txb_id = B53XX_MIB_TXB_ID;
1067 rxb_id = B53XX_MIB_RXB_ID;
1068
1069 if (is5365(dev)) {
1070 if (port == 5)
1071 port = 8;
1072
1073 mibs = b53_mibs_65;
1074 } else if (is63xx(dev)) {
1075 mibs = b53_mibs_63xx;
1076 txb_id = B63XX_MIB_TXB_ID;
1077 rxb_id = B63XX_MIB_RXB_ID;
1078 } else {
1079 mibs = b53_mibs;
1080 }
1081
1082 dev->buf[0] = 0;
1083
1084 if (mibs->size == 8) {
1085 b53_read64(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &txb);
1086 b53_read64(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &rxb);
1087 } else {
1088 u32 val32;
1089
1090 b53_read32(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &val32);
1091 txb = val32;
1092
1093 b53_read32(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &val32);
1094 rxb = val32;
1095 }
1096
1097 stats->tx_bytes = txb;
1098 stats->rx_bytes = rxb;
1099
1100 return 0;
1101 }
1102
1103 static struct switch_attr b53_global_ops_25[] = {
1104 {
1105 .type = SWITCH_TYPE_INT,
1106 .name = "enable_vlan",
1107 .description = "Enable VLAN mode",
1108 .set = b53_global_set_vlan_enable,
1109 .get = b53_global_get_vlan_enable,
1110 .max = 1,
1111 },
1112 {
1113 .type = SWITCH_TYPE_STRING,
1114 .name = "ports",
1115 .description = "Available ports (as bitmask)",
1116 .get = b53_global_get_ports,
1117 },
1118 };
1119
1120 static struct switch_attr b53_global_ops_65[] = {
1121 {
1122 .type = SWITCH_TYPE_INT,
1123 .name = "enable_vlan",
1124 .description = "Enable VLAN mode",
1125 .set = b53_global_set_vlan_enable,
1126 .get = b53_global_get_vlan_enable,
1127 .max = 1,
1128 },
1129 {
1130 .type = SWITCH_TYPE_STRING,
1131 .name = "ports",
1132 .description = "Available ports (as bitmask)",
1133 .get = b53_global_get_ports,
1134 },
1135 {
1136 .type = SWITCH_TYPE_INT,
1137 .name = "reset_mib",
1138 .description = "Reset MIB counters",
1139 .set = b53_global_reset_mib,
1140 },
1141 };
1142
1143 static struct switch_attr b53_global_ops[] = {
1144 {
1145 .type = SWITCH_TYPE_INT,
1146 .name = "enable_vlan",
1147 .description = "Enable VLAN mode",
1148 .set = b53_global_set_vlan_enable,
1149 .get = b53_global_get_vlan_enable,
1150 .max = 1,
1151 },
1152 {
1153 .type = SWITCH_TYPE_STRING,
1154 .name = "ports",
1155 .description = "Available Ports (as bitmask)",
1156 .get = b53_global_get_ports,
1157 },
1158 {
1159 .type = SWITCH_TYPE_INT,
1160 .name = "reset_mib",
1161 .description = "Reset MIB counters",
1162 .set = b53_global_reset_mib,
1163 },
1164 {
1165 .type = SWITCH_TYPE_INT,
1166 .name = "enable_jumbo",
1167 .description = "Enable Jumbo Frames",
1168 .set = b53_global_set_jumbo_enable,
1169 .get = b53_global_get_jumbo_enable,
1170 .max = 1,
1171 },
1172 {
1173 .type = SWITCH_TYPE_INT,
1174 .name = "allow_vid_4095",
1175 .description = "Allow VID 4095",
1176 .set = b53_global_set_4095_enable,
1177 .get = b53_global_get_4095_enable,
1178 .max = 1,
1179 },
1180 };
1181
1182 static struct switch_attr b53_port_ops[] = {
1183 {
1184 .type = SWITCH_TYPE_STRING,
1185 .name = "mib",
1186 .description = "Get port's MIB counters",
1187 .get = b53_port_get_mib,
1188 },
1189 };
1190
1191 static struct switch_attr b53_no_ops[] = {
1192 };
1193
1194 static const struct switch_dev_ops b53_switch_ops_25 = {
1195 .attr_global = {
1196 .attr = b53_global_ops_25,
1197 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1198 },
1199 .attr_port = {
1200 .attr = b53_no_ops,
1201 .n_attr = ARRAY_SIZE(b53_no_ops),
1202 },
1203 .attr_vlan = {
1204 .attr = b53_no_ops,
1205 .n_attr = ARRAY_SIZE(b53_no_ops),
1206 },
1207
1208 .get_vlan_ports = b53_vlan_get_ports,
1209 .set_vlan_ports = b53_vlan_set_ports,
1210 .get_port_pvid = b53_port_get_pvid,
1211 .set_port_pvid = b53_port_set_pvid,
1212 .apply_config = b53_global_apply_config,
1213 .reset_switch = b53_global_reset_switch,
1214 .get_port_link = b53_port_get_link,
1215 .set_port_link = b53_port_set_link,
1216 .get_port_stats = b53_port_get_stats,
1217 .phy_read16 = b53_phy_read16,
1218 .phy_write16 = b53_phy_write16,
1219 };
1220
1221 static const struct switch_dev_ops b53_switch_ops_65 = {
1222 .attr_global = {
1223 .attr = b53_global_ops_65,
1224 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1225 },
1226 .attr_port = {
1227 .attr = b53_port_ops,
1228 .n_attr = ARRAY_SIZE(b53_port_ops),
1229 },
1230 .attr_vlan = {
1231 .attr = b53_no_ops,
1232 .n_attr = ARRAY_SIZE(b53_no_ops),
1233 },
1234
1235 .get_vlan_ports = b53_vlan_get_ports,
1236 .set_vlan_ports = b53_vlan_set_ports,
1237 .get_port_pvid = b53_port_get_pvid,
1238 .set_port_pvid = b53_port_set_pvid,
1239 .apply_config = b53_global_apply_config,
1240 .reset_switch = b53_global_reset_switch,
1241 .get_port_link = b53_port_get_link,
1242 .set_port_link = b53_port_set_link,
1243 .get_port_stats = b53_port_get_stats,
1244 .phy_read16 = b53_phy_read16,
1245 .phy_write16 = b53_phy_write16,
1246 };
1247
1248 static const struct switch_dev_ops b53_switch_ops = {
1249 .attr_global = {
1250 .attr = b53_global_ops,
1251 .n_attr = ARRAY_SIZE(b53_global_ops),
1252 },
1253 .attr_port = {
1254 .attr = b53_port_ops,
1255 .n_attr = ARRAY_SIZE(b53_port_ops),
1256 },
1257 .attr_vlan = {
1258 .attr = b53_no_ops,
1259 .n_attr = ARRAY_SIZE(b53_no_ops),
1260 },
1261
1262 .get_vlan_ports = b53_vlan_get_ports,
1263 .set_vlan_ports = b53_vlan_set_ports,
1264 .get_port_pvid = b53_port_get_pvid,
1265 .set_port_pvid = b53_port_set_pvid,
1266 .apply_config = b53_global_apply_config,
1267 .reset_switch = b53_global_reset_switch,
1268 .get_port_link = b53_port_get_link,
1269 .set_port_link = b53_port_set_link,
1270 .get_port_stats = b53_port_get_stats,
1271 .phy_read16 = b53_phy_read16,
1272 .phy_write16 = b53_phy_write16,
1273 };
1274
1275 struct b53_chip_data {
1276 u32 chip_id;
1277 const char *dev_name;
1278 const char *alias;
1279 u16 vlans;
1280 u16 enabled_ports;
1281 u8 cpu_port;
1282 u8 vta_regs[3];
1283 u8 duplex_reg;
1284 u8 jumbo_pm_reg;
1285 u8 jumbo_size_reg;
1286 const struct switch_dev_ops *sw_ops;
1287 };
1288
1289 #define B53_VTA_REGS \
1290 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1291 #define B53_VTA_REGS_9798 \
1292 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1293 #define B53_VTA_REGS_63XX \
1294 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1295
1296 static const struct b53_chip_data b53_switch_chips[] = {
1297 {
1298 .chip_id = BCM5325_DEVICE_ID,
1299 .dev_name = "BCM5325",
1300 .alias = "bcm5325",
1301 .vlans = 16,
1302 .enabled_ports = 0x1f,
1303 .cpu_port = B53_CPU_PORT_25,
1304 .duplex_reg = B53_DUPLEX_STAT_FE,
1305 .sw_ops = &b53_switch_ops_25,
1306 },
1307 {
1308 .chip_id = BCM5365_DEVICE_ID,
1309 .dev_name = "BCM5365",
1310 .alias = "bcm5365",
1311 .vlans = 256,
1312 .enabled_ports = 0x1f,
1313 .cpu_port = B53_CPU_PORT_25,
1314 .duplex_reg = B53_DUPLEX_STAT_FE,
1315 .sw_ops = &b53_switch_ops_65,
1316 },
1317 {
1318 .chip_id = BCM5395_DEVICE_ID,
1319 .dev_name = "BCM5395",
1320 .alias = "bcm5395",
1321 .vlans = 4096,
1322 .enabled_ports = 0x1f,
1323 .cpu_port = B53_CPU_PORT,
1324 .vta_regs = B53_VTA_REGS,
1325 .duplex_reg = B53_DUPLEX_STAT_GE,
1326 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1327 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1328 .sw_ops = &b53_switch_ops,
1329 },
1330 {
1331 .chip_id = BCM5397_DEVICE_ID,
1332 .dev_name = "BCM5397",
1333 .alias = "bcm5397",
1334 .vlans = 4096,
1335 .enabled_ports = 0x1f,
1336 .cpu_port = B53_CPU_PORT,
1337 .vta_regs = B53_VTA_REGS_9798,
1338 .duplex_reg = B53_DUPLEX_STAT_GE,
1339 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1340 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1341 .sw_ops = &b53_switch_ops,
1342 },
1343 {
1344 .chip_id = BCM5398_DEVICE_ID,
1345 .dev_name = "BCM5398",
1346 .alias = "bcm5398",
1347 .vlans = 4096,
1348 .enabled_ports = 0x7f,
1349 .cpu_port = B53_CPU_PORT,
1350 .vta_regs = B53_VTA_REGS_9798,
1351 .duplex_reg = B53_DUPLEX_STAT_GE,
1352 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1353 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1354 .sw_ops = &b53_switch_ops,
1355 },
1356 {
1357 .chip_id = BCM53115_DEVICE_ID,
1358 .dev_name = "BCM53115",
1359 .alias = "bcm53115",
1360 .vlans = 4096,
1361 .enabled_ports = 0x1f,
1362 .vta_regs = B53_VTA_REGS,
1363 .cpu_port = B53_CPU_PORT,
1364 .duplex_reg = B53_DUPLEX_STAT_GE,
1365 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1366 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1367 .sw_ops = &b53_switch_ops,
1368 },
1369 {
1370 .chip_id = BCM53125_DEVICE_ID,
1371 .dev_name = "BCM53125",
1372 .alias = "bcm53125",
1373 .vlans = 4096,
1374 .enabled_ports = 0x1f,
1375 .cpu_port = B53_CPU_PORT,
1376 .vta_regs = B53_VTA_REGS,
1377 .duplex_reg = B53_DUPLEX_STAT_GE,
1378 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1379 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1380 .sw_ops = &b53_switch_ops,
1381 },
1382 {
1383 .chip_id = BCM53128_DEVICE_ID,
1384 .dev_name = "BCM53128",
1385 .alias = "bcm53128",
1386 .vlans = 4096,
1387 .enabled_ports = 0x1ff,
1388 .cpu_port = B53_CPU_PORT,
1389 .vta_regs = B53_VTA_REGS,
1390 .duplex_reg = B53_DUPLEX_STAT_GE,
1391 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1392 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1393 .sw_ops = &b53_switch_ops,
1394 },
1395 {
1396 .chip_id = BCM63XX_DEVICE_ID,
1397 .dev_name = "BCM63xx",
1398 .alias = "bcm63xx",
1399 .vlans = 4096,
1400 .enabled_ports = 0, /* pdata must provide them */
1401 .cpu_port = B53_CPU_PORT,
1402 .vta_regs = B53_VTA_REGS_63XX,
1403 .duplex_reg = B53_DUPLEX_STAT_63XX,
1404 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1405 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1406 .sw_ops = &b53_switch_ops,
1407 },
1408 {
1409 .chip_id = BCM53010_DEVICE_ID,
1410 .dev_name = "BCM53010",
1411 .alias = "bcm53011",
1412 .vlans = 4096,
1413 .enabled_ports = 0x1f,
1414 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1415 .vta_regs = B53_VTA_REGS,
1416 .duplex_reg = B53_DUPLEX_STAT_GE,
1417 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1418 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1419 .sw_ops = &b53_switch_ops,
1420 },
1421 {
1422 .chip_id = BCM53011_DEVICE_ID,
1423 .dev_name = "BCM53011",
1424 .alias = "bcm53011",
1425 .vlans = 4096,
1426 .enabled_ports = 0x1bf,
1427 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1428 .vta_regs = B53_VTA_REGS,
1429 .duplex_reg = B53_DUPLEX_STAT_GE,
1430 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1431 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1432 .sw_ops = &b53_switch_ops,
1433 },
1434 {
1435 .chip_id = BCM53012_DEVICE_ID,
1436 .dev_name = "BCM53012",
1437 .alias = "bcm53011",
1438 .vlans = 4096,
1439 .enabled_ports = 0x1bf,
1440 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1441 .vta_regs = B53_VTA_REGS,
1442 .duplex_reg = B53_DUPLEX_STAT_GE,
1443 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1444 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1445 .sw_ops = &b53_switch_ops,
1446 },
1447 {
1448 .chip_id = BCM53018_DEVICE_ID,
1449 .dev_name = "BCM53018",
1450 .alias = "bcm53018",
1451 .vlans = 4096,
1452 .enabled_ports = 0x1f,
1453 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1454 .vta_regs = B53_VTA_REGS,
1455 .duplex_reg = B53_DUPLEX_STAT_GE,
1456 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1457 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1458 .sw_ops = &b53_switch_ops,
1459 },
1460 {
1461 .chip_id = BCM53019_DEVICE_ID,
1462 .dev_name = "BCM53019",
1463 .alias = "bcm53019",
1464 .vlans = 4096,
1465 .enabled_ports = 0x1f,
1466 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1467 .vta_regs = B53_VTA_REGS,
1468 .duplex_reg = B53_DUPLEX_STAT_GE,
1469 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1470 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1471 .sw_ops = &b53_switch_ops,
1472 },
1473 };
1474
1475 static int b53_switch_init_of(struct b53_device *dev)
1476 {
1477 struct device_node *dn, *pn;
1478 const char *alias;
1479 u32 port_num;
1480 u16 ports = 0;
1481
1482 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
1483 if (!dn)
1484 return -EINVAL;
1485
1486 for_each_available_child_of_node(dn, pn) {
1487 const char *label;
1488 int len;
1489
1490 if (of_property_read_u32(pn, "reg", &port_num))
1491 continue;
1492
1493 if (port_num > B53_CPU_PORT)
1494 continue;
1495
1496 ports |= BIT(port_num);
1497
1498 label = of_get_property(pn, "label", &len);
1499 if (label && !strcmp(label, "cpu"))
1500 dev->sw_dev.cpu_port = port_num;
1501 }
1502
1503 dev->enabled_ports = ports;
1504
1505 if (!of_property_read_string(dev_of_node(dev->dev), "lede,alias",
1506 &alias))
1507 dev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);
1508
1509 return 0;
1510 }
1511
1512 static int b53_switch_init(struct b53_device *dev)
1513 {
1514 struct switch_dev *sw_dev = &dev->sw_dev;
1515 unsigned i;
1516 int ret;
1517
1518 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1519 const struct b53_chip_data *chip = &b53_switch_chips[i];
1520
1521 if (chip->chip_id == dev->chip_id) {
1522 sw_dev->name = chip->dev_name;
1523 if (!sw_dev->alias)
1524 sw_dev->alias = chip->alias;
1525 if (!dev->enabled_ports)
1526 dev->enabled_ports = chip->enabled_ports;
1527 dev->duplex_reg = chip->duplex_reg;
1528 dev->vta_regs[0] = chip->vta_regs[0];
1529 dev->vta_regs[1] = chip->vta_regs[1];
1530 dev->vta_regs[2] = chip->vta_regs[2];
1531 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1532 sw_dev->ops = chip->sw_ops;
1533 sw_dev->cpu_port = chip->cpu_port;
1534 sw_dev->vlans = chip->vlans;
1535 break;
1536 }
1537 }
1538
1539 if (!sw_dev->name)
1540 return -EINVAL;
1541
1542 /* check which BCM5325x version we have */
1543 if (is5325(dev)) {
1544 u8 vc4;
1545
1546 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1547
1548 /* check reserved bits */
1549 switch (vc4 & 3) {
1550 case 1:
1551 /* BCM5325E */
1552 break;
1553 case 3:
1554 /* BCM5325F - do not use port 4 */
1555 dev->enabled_ports &= ~BIT(4);
1556 break;
1557 default:
1558 /* On the BCM47XX SoCs this is the supported internal switch.*/
1559 #ifndef CONFIG_BCM47XX
1560 /* BCM5325M */
1561 return -EINVAL;
1562 #else
1563 break;
1564 #endif
1565 }
1566 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1567 u64 strap_value;
1568
1569 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1570 /* use second IMP port if GMII is enabled */
1571 if (strap_value & SV_GMII_CTRL_115)
1572 sw_dev->cpu_port = 5;
1573 }
1574
1575 if (dev_of_node(dev->dev)) {
1576 ret = b53_switch_init_of(dev);
1577 if (ret)
1578 return ret;
1579 }
1580
1581 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1582 sw_dev->ports = fls(dev->enabled_ports);
1583
1584 dev->ports = devm_kzalloc(dev->dev,
1585 sizeof(struct b53_port) * sw_dev->ports,
1586 GFP_KERNEL);
1587 if (!dev->ports)
1588 return -ENOMEM;
1589
1590 dev->vlans = devm_kzalloc(dev->dev,
1591 sizeof(struct b53_vlan) * sw_dev->vlans,
1592 GFP_KERNEL);
1593 if (!dev->vlans)
1594 return -ENOMEM;
1595
1596 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1597 if (!dev->buf)
1598 return -ENOMEM;
1599
1600 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1601 if (dev->reset_gpio >= 0) {
1602 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1603 GPIOF_OUT_INIT_HIGH, "robo_reset");
1604 if (ret)
1605 return ret;
1606 }
1607
1608 return b53_switch_reset(dev);
1609 }
1610
1611 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1612 void *priv)
1613 {
1614 struct b53_device *dev;
1615
1616 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1617 if (!dev)
1618 return NULL;
1619
1620 dev->dev = base;
1621 dev->ops = ops;
1622 dev->priv = priv;
1623 mutex_init(&dev->reg_mutex);
1624
1625 return dev;
1626 }
1627 EXPORT_SYMBOL(b53_switch_alloc);
1628
1629 int b53_switch_detect(struct b53_device *dev)
1630 {
1631 u32 id32;
1632 u16 tmp;
1633 u8 id8;
1634 int ret;
1635
1636 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1637 if (ret)
1638 return ret;
1639
1640 switch (id8) {
1641 case 0:
1642 /*
1643 * BCM5325 and BCM5365 do not have this register so reads
1644 * return 0. But the read operation did succeed, so assume
1645 * this is one of them.
1646 *
1647 * Next check if we can write to the 5325's VTA register; for
1648 * 5365 it is read only.
1649 */
1650
1651 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1652 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1653
1654 if (tmp == 0xf)
1655 dev->chip_id = BCM5325_DEVICE_ID;
1656 else
1657 dev->chip_id = BCM5365_DEVICE_ID;
1658 break;
1659 case BCM5395_DEVICE_ID:
1660 case BCM5397_DEVICE_ID:
1661 case BCM5398_DEVICE_ID:
1662 dev->chip_id = id8;
1663 break;
1664 default:
1665 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1666 if (ret)
1667 return ret;
1668
1669 switch (id32) {
1670 case BCM53115_DEVICE_ID:
1671 case BCM53125_DEVICE_ID:
1672 case BCM53128_DEVICE_ID:
1673 case BCM53010_DEVICE_ID:
1674 case BCM53011_DEVICE_ID:
1675 case BCM53012_DEVICE_ID:
1676 case BCM53018_DEVICE_ID:
1677 case BCM53019_DEVICE_ID:
1678 dev->chip_id = id32;
1679 break;
1680 default:
1681 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1682 id8, id32);
1683 return -ENODEV;
1684 }
1685 }
1686
1687 if (dev->chip_id == BCM5325_DEVICE_ID)
1688 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1689 &dev->core_rev);
1690 else
1691 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1692 &dev->core_rev);
1693 }
1694 EXPORT_SYMBOL(b53_switch_detect);
1695
1696 int b53_switch_register(struct b53_device *dev)
1697 {
1698 int ret;
1699
1700 if (dev->pdata) {
1701 dev->chip_id = dev->pdata->chip_id;
1702 dev->enabled_ports = dev->pdata->enabled_ports;
1703 dev->sw_dev.alias = dev->pdata->alias;
1704 }
1705
1706 if (!dev->chip_id && b53_switch_detect(dev))
1707 return -EINVAL;
1708
1709 ret = b53_switch_init(dev);
1710 if (ret)
1711 return ret;
1712
1713 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1714
1715 return register_switch(&dev->sw_dev, NULL);
1716 }
1717 EXPORT_SYMBOL(b53_switch_register);
1718
1719 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1720 MODULE_DESCRIPTION("B53 switch library");
1721 MODULE_LICENSE("Dual BSD/GPL");
OpenWrt Source Repository