2 * rtl8306.c: RTL8306S switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <net/genetlink.h>
25 #include <linux/switch.h>
26 #include <linux/delay.h>
27 #include <linux/phy.h>
32 #define RTL8306_REG_PAGE 16
33 #define RTL8306_REG_PAGE_LO (1 << 15)
34 #define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
36 #define RTL8306_NUM_VLANS 16
37 #define RTL8306_NUM_PORTS 6
38 #define RTL8306_PORT_CPU 5
39 #define RTL8306_NUM_PAGES 4
40 #define RTL8306_NUM_REGS 32
42 #define RTL_NAME_S "RTL8306S"
43 #define RTL_NAME_SD "RTL8306SD"
44 #define RTL_NAME_SDM "RTL8306SDM"
45 #define RTL_NAME_UNKNOWN "RTL8306(unknown)"
47 #define RTL8306_MAGIC 0x8306
49 static LIST_HEAD(phydevs
);
52 struct list_head list
;
53 struct switch_dev dev
;
58 char hwname
[sizeof(RTL_NAME_UNKNOWN
)];
68 #define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
85 #define RTL_VLAN_REGOFS(name) \
86 (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
88 #define RTL_PORT_REGOFS(name) \
89 (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
91 #define RTL_PORT_REG(id, reg) \
92 (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
94 #define RTL_VLAN_REG(id, reg) \
95 (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
97 #define RTL_GLOBAL_REGATTR(reg) \
98 .id = RTL_REG_##reg, \
99 .type = SWITCH_TYPE_INT, \
101 .set = rtl_attr_set_int, \
102 .get = rtl_attr_get_int
104 #define RTL_PORT_REGATTR(reg) \
105 .id = RTL_REG_PORT0_##reg, \
106 .type = SWITCH_TYPE_INT, \
107 .ofs = RTL_PORT_REGOFS(reg), \
108 .set = rtl_attr_set_port_int, \
109 .get = rtl_attr_get_port_int
111 #define RTL_VLAN_REGATTR(reg) \
112 .id = RTL_REG_VLAN0_##reg, \
113 .type = SWITCH_TYPE_INT, \
114 .ofs = RTL_VLAN_REGOFS(reg), \
115 .set = rtl_attr_set_vlan_int, \
116 .get = rtl_attr_get_vlan_int
130 RTL_REG_TRUNK_PORTSEL
,
136 RTL_REG_VLAN_TAG_ONLY
,
137 RTL_REG_VLAN_TAG_AWARE
,
138 #define RTL_VLAN_ENUM(id) \
139 RTL_REG_VLAN##id##_VID, \
140 RTL_REG_VLAN##id##_PORTMASK
157 #define RTL_PORT_ENUM(id) \
158 RTL_REG_PORT##id##_PVID, \
159 RTL_REG_PORT##id##_NULL_VID_REPLACE, \
160 RTL_REG_PORT##id##_NON_PVID_DISCARD, \
161 RTL_REG_PORT##id##_VID_INSERT, \
162 RTL_REG_PORT##id##_TAG_INSERT, \
163 RTL_REG_PORT##id##_LINK, \
164 RTL_REG_PORT##id##_SPEED, \
165 RTL_REG_PORT##id##_NWAY, \
166 RTL_REG_PORT##id##_NRESTART, \
167 RTL_REG_PORT##id##_DUPLEX, \
168 RTL_REG_PORT##id##_RXEN, \
169 RTL_REG_PORT##id##_TXEN
178 static const struct rtl_reg rtl_regs
[] = {
179 [RTL_REG_CHIPID
] = { 0, 4, 30, 16, 0, 0 },
180 [RTL_REG_CHIPVER
] = { 0, 4, 31, 8, 0, 0 },
181 [RTL_REG_CHIPTYPE
] = { 0, 4, 31, 2, 8, 0 },
183 /* CPU port number */
184 [RTL_REG_CPUPORT
] = { 2, 4, 21, 3, 0, 0 },
185 /* Enable CPU port function */
186 [RTL_REG_EN_CPUPORT
] = { 3, 2, 21, 1, 15, 1 },
187 /* Enable CPU port tag insertion */
188 [RTL_REG_EN_TAG_OUT
] = { 3, 2, 21, 1, 12, 0 },
189 /* Enable CPU port tag removal */
190 [RTL_REG_EN_TAG_CLR
] = { 3, 2, 21, 1, 11, 0 },
191 /* Enable CPU port tag checking */
192 [RTL_REG_EN_TAG_IN
] = { 0, 4, 21, 1, 7, 0 },
193 [RTL_REG_EN_TRUNK
] = { 0, 0, 19, 1, 11, 1 },
194 [RTL_REG_TRUNK_PORTSEL
] = { 0, 0, 16, 1, 6, 1 },
195 [RTL_REG_RESET
] = { 0, 0, 16, 1, 12, 0 },
197 [RTL_REG_TRAP_CPU
] = { 3, 2, 22, 1, 6, 0 },
198 [RTL_REG_CPU_LINKUP
] = { 0, 6, 22, 1, 15, 0 },
200 [RTL_REG_VLAN_TAG_ONLY
] = { 0, 0, 16, 1, 8, 1 },
201 [RTL_REG_VLAN_FILTER
] = { 0, 0, 16, 1, 9, 1 },
202 [RTL_REG_VLAN_TAG_AWARE
] = { 0, 0, 16, 1, 10, 1 },
203 [RTL_REG_VLAN_ENABLE
] = { 0, 0, 18, 1, 8, 1 },
205 #define RTL_VLAN_REGS(id, phy, page, regofs) \
206 [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
207 [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
208 RTL_VLAN_REGS( 0, 0, 0, 0),
209 RTL_VLAN_REGS( 1, 1, 0, 0),
210 RTL_VLAN_REGS( 2, 2, 0, 0),
211 RTL_VLAN_REGS( 3, 3, 0, 0),
212 RTL_VLAN_REGS( 4, 4, 0, 0),
213 RTL_VLAN_REGS( 5, 0, 1, 2),
214 RTL_VLAN_REGS( 6, 1, 1, 2),
215 RTL_VLAN_REGS( 7, 2, 1, 2),
216 RTL_VLAN_REGS( 8, 3, 1, 2),
217 RTL_VLAN_REGS( 9, 4, 1, 2),
218 RTL_VLAN_REGS(10, 0, 1, 4),
219 RTL_VLAN_REGS(11, 1, 1, 4),
220 RTL_VLAN_REGS(12, 2, 1, 4),
221 RTL_VLAN_REGS(13, 3, 1, 4),
222 RTL_VLAN_REGS(14, 4, 1, 4),
223 RTL_VLAN_REGS(15, 0, 1, 6),
225 #define REG_PORT_SETTING(port, phy) \
226 [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
227 [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
228 [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
229 [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
230 [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
231 [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
232 [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
233 [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
234 [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
235 [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
236 [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
238 REG_PORT_SETTING(0, 0),
239 REG_PORT_SETTING(1, 1),
240 REG_PORT_SETTING(2, 2),
241 REG_PORT_SETTING(3, 3),
242 REG_PORT_SETTING(4, 4),
243 REG_PORT_SETTING(5, 6),
245 #define REG_PORT_PVID(phy, page, regofs) \
246 { page, phy, 24 + regofs, 4, 12, 0 }
247 [RTL_REG_PORT0_PVID
] = REG_PORT_PVID(0, 0, 0),
248 [RTL_REG_PORT1_PVID
] = REG_PORT_PVID(1, 0, 0),
249 [RTL_REG_PORT2_PVID
] = REG_PORT_PVID(2, 0, 0),
250 [RTL_REG_PORT3_PVID
] = REG_PORT_PVID(3, 0, 0),
251 [RTL_REG_PORT4_PVID
] = REG_PORT_PVID(4, 0, 0),
252 [RTL_REG_PORT5_PVID
] = REG_PORT_PVID(0, 1, 2),
257 rtl_set_page(struct rtl_priv
*priv
, unsigned int page
)
259 struct mii_bus
*bus
= priv
->bus
;
265 if (priv
->page
== page
)
268 BUG_ON(page
> RTL8306_NUM_PAGES
);
269 pgsel
= bus
->read(bus
, 0, RTL8306_REG_PAGE
);
270 pgsel
&= ~(RTL8306_REG_PAGE_LO
| RTL8306_REG_PAGE_HI
);
272 pgsel
|= RTL8306_REG_PAGE_LO
;
273 if (!(page
& (1 << 1))) /* bit is inverted */
274 pgsel
|= RTL8306_REG_PAGE_HI
;
275 bus
->write(bus
, 0, RTL8306_REG_PAGE
, pgsel
);
279 rtl_w16(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
, u16 val
)
281 struct rtl_priv
*priv
= to_rtl(dev
);
282 struct mii_bus
*bus
= priv
->bus
;
284 rtl_set_page(priv
, page
);
285 bus
->write(bus
, phy
, reg
, val
);
286 bus
->read(bus
, phy
, reg
); /* flush */
291 rtl_r16(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
)
293 struct rtl_priv
*priv
= to_rtl(dev
);
294 struct mii_bus
*bus
= priv
->bus
;
296 rtl_set_page(priv
, page
);
297 return bus
->read(bus
, phy
, reg
);
301 rtl_rmw(struct switch_dev
*dev
, unsigned int page
, unsigned int phy
, unsigned int reg
, u16 mask
, u16 val
)
303 struct rtl_priv
*priv
= to_rtl(dev
);
304 struct mii_bus
*bus
= priv
->bus
;
307 rtl_set_page(priv
, page
);
308 r
= bus
->read(bus
, phy
, reg
);
311 bus
->write(bus
, phy
, reg
, r
);
312 return bus
->read(bus
, phy
, reg
); /* flush */
317 rtl_get(struct switch_dev
*dev
, enum rtl_regidx s
)
319 const struct rtl_reg
*r
= &rtl_regs
[s
];
322 BUG_ON(s
>= ARRAY_SIZE(rtl_regs
));
323 if (r
->bits
== 0) /* unimplemented */
326 val
= rtl_r16(dev
, r
->page
, r
->phy
, r
->reg
);
334 val
&= (1 << r
->bits
) - 1;
340 rtl_set(struct switch_dev
*dev
, enum rtl_regidx s
, unsigned int val
)
342 const struct rtl_reg
*r
= &rtl_regs
[s
];
345 BUG_ON(s
>= ARRAY_SIZE(rtl_regs
));
347 if (r
->bits
== 0) /* unimplemented */
357 mask
= (1 << r
->bits
) - 1;
361 return rtl_rmw(dev
, r
->page
, r
->phy
, r
->reg
, mask
, val
);
365 rtl_phy_save(struct switch_dev
*dev
, int port
, struct rtl_phyregs
*regs
)
367 regs
->nway
= rtl_get(dev
, RTL_PORT_REG(port
, NWAY
));
368 regs
->speed
= rtl_get(dev
, RTL_PORT_REG(port
, SPEED
));
369 regs
->duplex
= rtl_get(dev
, RTL_PORT_REG(port
, DUPLEX
));
373 rtl_phy_restore(struct switch_dev
*dev
, int port
, struct rtl_phyregs
*regs
)
375 rtl_set(dev
, RTL_PORT_REG(port
, NWAY
), regs
->nway
);
376 rtl_set(dev
, RTL_PORT_REG(port
, SPEED
), regs
->speed
);
377 rtl_set(dev
, RTL_PORT_REG(port
, DUPLEX
), regs
->duplex
);
381 rtl_port_set_enable(struct switch_dev
*dev
, int port
, int enabled
)
383 rtl_set(dev
, RTL_PORT_REG(port
, RXEN
), enabled
);
384 rtl_set(dev
, RTL_PORT_REG(port
, TXEN
), enabled
);
386 if ((port
>= 5) || !enabled
)
389 /* restart autonegotiation if enabled */
390 rtl_set(dev
, RTL_PORT_REG(port
, NRESTART
), 1);
394 rtl_hw_apply(struct switch_dev
*dev
)
397 int trunk_en
, trunk_psel
;
398 struct rtl_phyregs port5
;
400 rtl_phy_save(dev
, 5, &port5
);
402 /* disable rx/tx from PHYs */
403 for (i
= 0; i
< RTL8306_NUM_PORTS
- 1; i
++) {
404 rtl_port_set_enable(dev
, i
, 0);
407 /* save trunking status */
408 trunk_en
= rtl_get(dev
, RTL_REG_EN_TRUNK
);
409 trunk_psel
= rtl_get(dev
, RTL_REG_TRUNK_PORTSEL
);
411 /* trunk port 3 and 4
412 * XXX: Big WTF, but RealTek seems to do it */
413 rtl_set(dev
, RTL_REG_EN_TRUNK
, 1);
414 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, 1);
416 /* execute the software reset */
417 rtl_set(dev
, RTL_REG_RESET
, 1);
419 /* wait for the reset to complete,
420 * but don't wait for too long */
421 for (i
= 0; i
< 10; i
++) {
422 if (rtl_get(dev
, RTL_REG_RESET
) == 0)
428 /* enable rx/tx from PHYs */
429 for (i
= 0; i
< RTL8306_NUM_PORTS
- 1; i
++) {
430 rtl_port_set_enable(dev
, i
, 1);
433 /* restore trunking settings */
434 rtl_set(dev
, RTL_REG_EN_TRUNK
, trunk_en
);
435 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, trunk_psel
);
436 rtl_phy_restore(dev
, 5, &port5
);
438 rtl_set(dev
, RTL_REG_CPU_LINKUP
, 1);
444 rtl_hw_init(struct switch_dev
*dev
)
446 struct rtl_priv
*priv
= to_rtl(dev
);
447 int cpu_mask
= 1 << dev
->cpu_port
;
450 rtl_set(dev
, RTL_REG_VLAN_ENABLE
, 0);
451 rtl_set(dev
, RTL_REG_VLAN_FILTER
, 0);
452 rtl_set(dev
, RTL_REG_EN_TRUNK
, 0);
453 rtl_set(dev
, RTL_REG_TRUNK_PORTSEL
, 0);
455 /* initialize cpu port settings */
457 rtl_set(dev
, RTL_REG_CPUPORT
, dev
->cpu_port
);
458 rtl_set(dev
, RTL_REG_EN_CPUPORT
, 1);
460 rtl_set(dev
, RTL_REG_CPUPORT
, 7);
461 rtl_set(dev
, RTL_REG_EN_CPUPORT
, 0);
463 rtl_set(dev
, RTL_REG_EN_TAG_OUT
, 0);
464 rtl_set(dev
, RTL_REG_EN_TAG_IN
, 0);
465 rtl_set(dev
, RTL_REG_EN_TAG_CLR
, 0);
467 /* reset all vlans */
468 for (i
= 0; i
< RTL8306_NUM_VLANS
; i
++) {
469 rtl_set(dev
, RTL_VLAN_REG(i
, VID
), i
);
470 rtl_set(dev
, RTL_VLAN_REG(i
, PORTMASK
), 0);
473 /* default to port isolation */
474 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
477 if ((1 << i
) == cpu_mask
)
478 mask
= ((1 << RTL8306_NUM_PORTS
) - 1) & ~cpu_mask
; /* all bits set */
480 mask
= cpu_mask
| (1 << i
);
482 rtl_set(dev
, RTL_VLAN_REG(i
, PORTMASK
), mask
);
483 rtl_set(dev
, RTL_PORT_REG(i
, PVID
), i
);
484 rtl_set(dev
, RTL_PORT_REG(i
, NULL_VID_REPLACE
), 1);
485 rtl_set(dev
, RTL_PORT_REG(i
, VID_INSERT
), 1);
486 rtl_set(dev
, RTL_PORT_REG(i
, TAG_INSERT
), 3);
493 rtl_set_use_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
495 struct rtl_priv
*priv
= to_rtl(dev
);
496 priv
->do_cpu
= val
->value
.i
;
502 rtl_get_use_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
504 struct rtl_priv
*priv
= to_rtl(dev
);
505 val
->value
.i
= priv
->do_cpu
;
510 rtl_set_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
512 dev
->cpu_port
= val
->value
.i
;
518 rtl_get_cpuport(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
520 val
->value
.i
= dev
->cpu_port
;
526 rtl_reset(struct switch_dev
*dev
)
533 rtl_attr_set_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
535 int idx
= attr
->id
+ (val
->port_vlan
* attr
->ofs
);
536 struct rtl_phyregs port
;
538 if (attr
->id
>= ARRAY_SIZE(rtl_regs
))
541 if ((attr
->max
> 0) && (val
->value
.i
> attr
->max
))
544 /* access to phy register 22 on port 4/5
545 * needs phy status save/restore */
546 if ((val
->port_vlan
> 3) &&
547 (rtl_regs
[idx
].reg
== 22) &&
548 (rtl_regs
[idx
].page
== 0)) {
550 rtl_phy_save(dev
, val
->port_vlan
, &port
);
551 rtl_set(dev
, idx
, val
->value
.i
);
552 rtl_phy_restore(dev
, val
->port_vlan
, &port
);
554 rtl_set(dev
, idx
, val
->value
.i
);
561 rtl_attr_get_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
563 int idx
= attr
->id
+ (val
->port_vlan
* attr
->ofs
);
565 if (idx
>= ARRAY_SIZE(rtl_regs
))
568 val
->value
.i
= rtl_get(dev
, idx
);
573 rtl_attr_set_port_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
575 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
578 return rtl_attr_set_int(dev
, attr
, val
);
582 rtl_attr_get_port_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
584 if (val
->port_vlan
>= RTL8306_NUM_PORTS
)
586 return rtl_attr_get_int(dev
, attr
, val
);
590 rtl_get_port_link(struct switch_dev
*dev
, int port
, struct switch_port_link
*link
)
592 if (port
>= RTL8306_NUM_PORTS
)
595 /* in case the link changes from down to up, the register is only updated on read */
596 link
->link
= rtl_get(dev
, RTL_PORT_REG(port
, LINK
));
598 link
->link
= rtl_get(dev
, RTL_PORT_REG(port
, LINK
));
603 link
->duplex
= rtl_get(dev
, RTL_PORT_REG(port
, DUPLEX
));
604 link
->aneg
= rtl_get(dev
, RTL_PORT_REG(port
, NWAY
));
606 if (rtl_get(dev
, RTL_PORT_REG(port
, SPEED
)))
607 link
->speed
= SWITCH_PORT_SPEED_100
;
609 link
->speed
= SWITCH_PORT_SPEED_10
;
615 rtl_attr_set_vlan_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
617 if (val
->port_vlan
>= dev
->vlans
)
620 return rtl_attr_set_int(dev
, attr
, val
);
624 rtl_attr_get_vlan_int(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
626 if (val
->port_vlan
>= dev
->vlans
)
629 return rtl_attr_get_int(dev
, attr
, val
);
633 rtl_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
635 unsigned int i
, mask
;
637 mask
= rtl_get(dev
, RTL_VLAN_REG(val
->port_vlan
, PORTMASK
));
638 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
639 struct switch_port
*port
;
641 if (!(mask
& (1 << i
)))
644 port
= &val
->value
.ports
[val
->len
];
646 if (rtl_get(dev
, RTL_PORT_REG(i
, TAG_INSERT
)) == 2 || i
== dev
->cpu_port
)
647 port
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
655 rtl_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
657 struct rtl_priv
*priv
= to_rtl(dev
);
658 struct rtl_phyregs port
;
659 int en
= val
->value
.i
;
662 rtl_set(dev
, RTL_REG_EN_TAG_OUT
, en
&& priv
->do_cpu
);
663 rtl_set(dev
, RTL_REG_EN_TAG_IN
, en
&& priv
->do_cpu
);
664 rtl_set(dev
, RTL_REG_EN_TAG_CLR
, en
&& priv
->do_cpu
);
665 rtl_set(dev
, RTL_REG_VLAN_TAG_AWARE
, en
);
667 rtl_set(dev
, RTL_REG_VLAN_FILTER
, en
);
669 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
671 rtl_phy_save(dev
, val
->port_vlan
, &port
);
672 rtl_set(dev
, RTL_PORT_REG(i
, NULL_VID_REPLACE
), 1);
673 rtl_set(dev
, RTL_PORT_REG(i
, VID_INSERT
), (en
? (i
== dev
->cpu_port
? 0 : 1) : 1));
674 rtl_set(dev
, RTL_PORT_REG(i
, TAG_INSERT
), (en
? (i
== dev
->cpu_port
? 2 : 1) : 3));
676 rtl_phy_restore(dev
, val
->port_vlan
, &port
);
678 rtl_set(dev
, RTL_REG_VLAN_ENABLE
, en
);
684 rtl_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
, struct switch_val
*val
)
686 val
->value
.i
= rtl_get(dev
, RTL_REG_VLAN_ENABLE
);
691 rtl_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
693 unsigned int mask
= 0;
694 unsigned int oldmask
;
697 for(i
= 0; i
< val
->len
; i
++)
699 struct switch_port
*port
= &val
->value
.ports
[i
];
702 mask
|= (1 << port
->id
);
704 if (port
->id
== dev
->cpu_port
)
707 if ((i
== dev
->cpu_port
) ||
708 (port
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)))
711 /* fix up PVIDs for added ports */
713 rtl_set(dev
, RTL_PORT_REG(port
->id
, PVID
), val
->port_vlan
);
715 rtl_set(dev
, RTL_PORT_REG(port
->id
, NON_PVID_DISCARD
), (tagged
? 0 : 1));
716 rtl_set(dev
, RTL_PORT_REG(port
->id
, VID_INSERT
), (tagged
? 0 : 1));
717 rtl_set(dev
, RTL_PORT_REG(port
->id
, TAG_INSERT
), (tagged
? 2 : 1));
720 oldmask
= rtl_get(dev
, RTL_VLAN_REG(val
->port_vlan
, PORTMASK
));
721 rtl_set(dev
, RTL_VLAN_REG(val
->port_vlan
, PORTMASK
), mask
);
723 /* fix up PVIDs for removed ports, default to last vlan */
725 for (i
= 0; i
< RTL8306_NUM_PORTS
; i
++) {
726 if (!(oldmask
& (1 << i
)))
729 if (i
== dev
->cpu_port
)
732 if (rtl_get(dev
, RTL_PORT_REG(i
, PVID
)) == val
->port_vlan
)
733 rtl_set(dev
, RTL_PORT_REG(i
, PVID
), dev
->vlans
- 1);
739 static struct switch_attr rtl_globals
[] = {
741 .type
= SWITCH_TYPE_INT
,
742 .name
= "enable_vlan",
743 .description
= "Enable VLAN mode",
749 RTL_GLOBAL_REGATTR(EN_TRUNK
),
751 .description
= "Enable port trunking",
755 RTL_GLOBAL_REGATTR(TRUNK_PORTSEL
),
757 .description
= "Select ports for trunking (0: 0,1 - 1: 3,4)",
762 RTL_GLOBAL_REGATTR(VLAN_FILTER
),
763 .name
= "vlan_filter",
764 .description
= "Filter incoming packets for allowed VLANS",
768 .type
= SWITCH_TYPE_INT
,
770 .description
= "CPU Port",
771 .set
= rtl_set_cpuport
,
772 .get
= rtl_get_cpuport
,
773 .max
= RTL8306_NUM_PORTS
,
776 .type
= SWITCH_TYPE_INT
,
777 .name
= "use_cpuport",
778 .description
= "CPU Port handling flag",
779 .set
= rtl_set_use_cpuport
,
780 .get
= rtl_get_use_cpuport
,
781 .max
= RTL8306_NUM_PORTS
,
784 RTL_GLOBAL_REGATTR(TRAP_CPU
),
786 .description
= "VLAN trap to CPU",
790 RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE
),
791 .name
= "vlan_tag_aware",
792 .description
= "Enable VLAN tag awareness",
796 RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY
),
798 .description
= "Only accept tagged packets",
803 static struct switch_attr rtl_port
[] = {
805 RTL_PORT_REGATTR(PVID
),
807 .description
= "Port VLAN ID",
808 .max
= RTL8306_NUM_VLANS
- 1,
812 RTL_PORT_REGATTR(NULL_VID_REPLACE
),
814 .description
= "NULL VID gets replaced by port default vid",
818 RTL_PORT_REGATTR(NON_PVID_DISCARD
),
819 .name
= "non_pvid_discard",
820 .description
= "discard packets with VID != PVID",
824 RTL_PORT_REGATTR(VID_INSERT
),
825 .name
= "vid_insert_remove",
826 .description
= "how should the switch insert and remove vids ?",
830 RTL_PORT_REGATTR(TAG_INSERT
),
831 .name
= "tag_insert",
832 .description
= "tag insertion handling",
838 static struct switch_attr rtl_vlan
[] = {
840 RTL_VLAN_REGATTR(VID
),
842 .description
= "VLAN ID (1-4095)",
847 static const struct switch_dev_ops rtl8306_ops
= {
850 .n_attr
= ARRAY_SIZE(rtl_globals
),
854 .n_attr
= ARRAY_SIZE(rtl_port
),
858 .n_attr
= ARRAY_SIZE(rtl_vlan
),
861 .get_vlan_ports
= rtl_get_ports
,
862 .set_vlan_ports
= rtl_set_ports
,
863 .apply_config
= rtl_hw_apply
,
864 .reset_switch
= rtl_reset
,
865 .get_port_link
= rtl_get_port_link
,
869 rtl8306_config_init(struct phy_device
*pdev
)
871 struct net_device
*netdev
= pdev
->attached_dev
;
872 struct rtl_priv
*priv
= pdev
->priv
;
873 struct switch_dev
*dev
= &priv
->dev
;
874 struct switch_val val
;
875 unsigned int chipid
, chipver
, chiptype
;
878 /* Only init the switch for the primary PHY */
879 if (pdev
->mdio
.addr
!= 0)
883 priv
->dev
.cpu_port
= RTL8306_PORT_CPU
;
884 priv
->dev
.ports
= RTL8306_NUM_PORTS
;
885 priv
->dev
.vlans
= RTL8306_NUM_VLANS
;
886 priv
->dev
.ops
= &rtl8306_ops
;
889 priv
->bus
= pdev
->mdio
.bus
;
891 chipid
= rtl_get(dev
, RTL_REG_CHIPID
);
892 chipver
= rtl_get(dev
, RTL_REG_CHIPVER
);
893 chiptype
= rtl_get(dev
, RTL_REG_CHIPTYPE
);
897 strncpy(priv
->hwname
, RTL_NAME_S
, sizeof(priv
->hwname
));
898 priv
->type
= RTL_TYPE_S
;
901 strncpy(priv
->hwname
, RTL_NAME_SD
, sizeof(priv
->hwname
));
902 priv
->type
= RTL_TYPE_SD
;
905 strncpy(priv
->hwname
, RTL_NAME_SDM
, sizeof(priv
->hwname
));
906 priv
->type
= RTL_TYPE_SDM
;
909 strncpy(priv
->hwname
, RTL_NAME_UNKNOWN
, sizeof(priv
->hwname
));
913 dev
->name
= priv
->hwname
;
916 printk(KERN_INFO
"Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv
->hwname
, chipid
, chipver
);
918 err
= register_switch(dev
, netdev
);
929 rtl8306_fixup(struct phy_device
*pdev
)
931 struct rtl_priv priv
;
934 /* Attach to primary LAN port and WAN port */
935 if (pdev
->mdio
.addr
!= 0 && pdev
->mdio
.addr
!= 4)
938 memset(&priv
, 0, sizeof(priv
));
941 priv
.bus
= pdev
->mdio
.bus
;
942 chipid
= rtl_get(&priv
.dev
, RTL_REG_CHIPID
);
943 if (chipid
== 0x5988)
944 pdev
->phy_id
= RTL8306_MAGIC
;
950 rtl8306_probe(struct phy_device
*pdev
)
952 struct rtl_priv
*priv
;
954 list_for_each_entry(priv
, &phydevs
, list
) {
956 * share one rtl_priv instance between virtual phy
957 * devices on the same bus
959 if (priv
->bus
== pdev
->mdio
.bus
)
962 priv
= kzalloc(sizeof(struct rtl_priv
), GFP_KERNEL
);
966 priv
->bus
= pdev
->mdio
.bus
;
974 rtl8306_remove(struct phy_device
*pdev
)
976 struct rtl_priv
*priv
= pdev
->priv
;
977 unregister_switch(&priv
->dev
);
982 rtl8306_config_aneg(struct phy_device
*pdev
)
984 struct rtl_priv
*priv
= pdev
->priv
;
987 if (pdev
->mdio
.addr
== 0)
990 /* Restart autonegotiation */
991 rtl_set(&priv
->dev
, RTL_PORT_REG(4, NWAY
), 1);
992 rtl_set(&priv
->dev
, RTL_PORT_REG(4, NRESTART
), 1);
998 rtl8306_read_status(struct phy_device
*pdev
)
1000 struct rtl_priv
*priv
= pdev
->priv
;
1001 struct switch_dev
*dev
= &priv
->dev
;
1003 if (pdev
->mdio
.addr
== 4) {
1005 pdev
->speed
= rtl_get(dev
, RTL_PORT_REG(4, SPEED
)) ? SPEED_100
: SPEED_10
;
1006 pdev
->duplex
= rtl_get(dev
, RTL_PORT_REG(4, DUPLEX
)) ? DUPLEX_FULL
: DUPLEX_HALF
;
1007 pdev
->link
= !!rtl_get(dev
, RTL_PORT_REG(4, LINK
));
1010 pdev
->speed
= SPEED_100
;
1011 pdev
->duplex
= DUPLEX_FULL
;
1016 * Bypass generic PHY status read,
1017 * it doesn't work with this switch
1020 pdev
->state
= PHY_RUNNING
;
1021 netif_carrier_on(pdev
->attached_dev
);
1022 pdev
->adjust_link(pdev
->attached_dev
);
1024 pdev
->state
= PHY_NOLINK
;
1025 netif_carrier_off(pdev
->attached_dev
);
1026 pdev
->adjust_link(pdev
->attached_dev
);
1033 static struct phy_driver rtl8306_driver
= {
1034 .name
= "Realtek RTL8306S",
1035 .flags
= PHY_HAS_MAGICANEG
,
1036 .phy_id
= RTL8306_MAGIC
,
1037 .phy_id_mask
= 0xffffffff,
1038 .features
= PHY_BASIC_FEATURES
,
1039 .probe
= &rtl8306_probe
,
1040 .remove
= &rtl8306_remove
,
1041 .config_init
= &rtl8306_config_init
,
1042 .config_aneg
= &rtl8306_config_aneg
,
1043 .read_status
= &rtl8306_read_status
,
1050 phy_register_fixup_for_id(PHY_ANY_ID
, rtl8306_fixup
);
1051 return phy_driver_register(&rtl8306_driver
, THIS_MODULE
);
1057 phy_driver_unregister(&rtl8306_driver
);
1060 module_init(rtl_init
);
1061 module_exit(rtl_exit
);
1062 MODULE_LICENSE("GPL");