generic: copy backport, hack, pending patch and config from 6.1 to 6.6
[openwrt/openwrt.git] / target / linux / generic / hack-6.6 / 750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
1 From 880d1311335120f64447ca9d11933872d734e19a Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Mon, 27 Mar 2023 18:41:54 +0100
4 Subject: [PATCH] generic: pcs-mtk-lynxi: add hack to use 2500Base-X without AN
5
6 Using 2500Base-T SFP modules e.g. on the BananaPi R3 requires manually
7 disabling auto-negotiation, e.g. using ethtool. While a proper fix
8 using SFP quirks is being discussed upstream, bring a work-around to
9 restore user experience to what it was before the switch to the
10 dedicated SGMII PCS driver.
11
12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
13
14 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
15 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
16 @@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
17 struct phylink_link_state *state)
18 {
19 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
20 - unsigned int bm, adv;
21 + unsigned int bm, bmsr, adv;
22
23 /* Read the BMSR and LPA */
24 regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
25 - regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
26 + bmsr = FIELD_GET(SGMII_BMSR, bm);
27 +
28 + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
29 + state->link = !!(bmsr & BMSR_LSTATUS);
30 + state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
31 + state->speed = SPEED_2500;
32 + state->duplex = DUPLEX_FULL;
33
34 - phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
35 - FIELD_GET(SGMII_LPA, adv));
36 + return;
37 + }
38 +
39 + regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
40 + phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
41 }
42
43 static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
44 @@ -163,7 +172,8 @@ static int mtk_pcs_lynxi_config(struct p
45 if (neg_mode & PHYLINK_PCS_NEG_INBAND)
46 sgm_mode |= SGMII_REMOTE_FAULT_DIS;
47
48 - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
49 + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED &&
50 + interface != PHY_INTERFACE_MODE_2500BASEX) {
51 if (interface == PHY_INTERFACE_MODE_SGMII)
52 sgm_mode |= SGMII_SPEED_DUPLEX_AN;
53 bmcr = BMCR_ANENABLE;