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2791ce1bb6d22860ad7ebe2865cb8af2570f2078
[openwrt/openwrt.git] / target / linux / generic / patches-3.14 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -1,8 +1,10 @@
4 bcma-y += main.o scan.o core.o sprom.o
5 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
6 +bcma-y += driver_chipcommon_b.o
7 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
8 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
9 bcma-y += driver_pci.o
10 +bcma-y += driver_pcie2.o
11 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
12 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
13 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
14 --- a/drivers/bcma/driver_chipcommon.c
15 +++ b/drivers/bcma/driver_chipcommon.c
16 @@ -339,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
17 return;
18 }
19
20 - irq = bcma_core_irq(cc->core);
21 + irq = bcma_core_irq(cc->core, 0);
22
23 /* Determine the registers of the UARTs */
24 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
25 --- a/drivers/bcma/driver_chipcommon_pmu.c
26 +++ b/drivers/bcma/driver_chipcommon_pmu.c
27 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
28 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
29 break;
30
31 + case BCMA_CHIP_ID_BCM43131:
32 + case BCMA_CHIP_ID_BCM43217:
33 case BCMA_CHIP_ID_BCM43227:
34 case BCMA_CHIP_ID_BCM43228:
35 case BCMA_CHIP_ID_BCM43428:
36 --- a/drivers/bcma/driver_gpio.c
37 +++ b/drivers/bcma/driver_gpio.c
38 @@ -76,7 +76,7 @@ static void bcma_gpio_free(struct gpio_c
39 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
40 }
41
42 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
43 +#if IS_BUILTIN(CONFIG_BCM47XX)
44 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
45 {
46 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
47 @@ -152,7 +152,7 @@ static int bcma_gpio_irq_domain_init(str
48 handle_simple_irq);
49 }
50
51 - hwirq = bcma_core_irq(cc->core);
52 + hwirq = bcma_core_irq(cc->core, 0);
53 err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
54 cc);
55 if (err)
56 @@ -183,7 +183,7 @@ static void bcma_gpio_irq_domain_exit(st
57 return;
58
59 bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
60 - free_irq(bcma_core_irq(cc->core), cc);
61 + free_irq(bcma_core_irq(cc->core, 0), cc);
62 for (gpio = 0; gpio < chip->ngpio; gpio++) {
63 int irq = irq_find_mapping(cc->irq_domain, gpio);
64
65 @@ -215,10 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
66 chip->set = bcma_gpio_set_value;
67 chip->direction_input = bcma_gpio_direction_input;
68 chip->direction_output = bcma_gpio_direction_output;
69 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
70 +#if IS_BUILTIN(CONFIG_BCM47XX)
71 chip->to_irq = bcma_gpio_to_irq;
72 #endif
73 - chip->ngpio = 16;
74 +#if IS_BUILTIN(CONFIG_OF)
75 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
76 + chip->of_node = cc->core->dev.of_node;
77 +#endif
78 + switch (cc->core->bus->chipinfo.id) {
79 + case BCMA_CHIP_ID_BCM5357:
80 + case BCMA_CHIP_ID_BCM53572:
81 + chip->ngpio = 32;
82 + break;
83 + default:
84 + chip->ngpio = 16;
85 + }
86 +
87 /* There is just one SoC in one device and its GPIO addresses should be
88 * deterministic to address them more easily. The other buses could get
89 * a random base number. */
90 @@ -243,5 +255,6 @@ int bcma_gpio_init(struct bcma_drv_cc *c
91 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
92 {
93 bcma_gpio_irq_domain_exit(cc);
94 - return gpiochip_remove(&cc->gpio);
95 + gpiochip_remove(&cc->gpio);
96 + return 0;
97 }
98 --- a/drivers/bcma/driver_pci_host.c
99 +++ b/drivers/bcma/driver_pci_host.c
100 @@ -593,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p
101 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
102
103 /* Fix up interrupt lines */
104 - dev->irq = bcma_core_irq(pc_host->pdev->core);
105 + dev->irq = bcma_core_irq(pc_host->pdev->core, 0);
106 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
107
108 readrq = pcie_get_readrq(dev);
109 @@ -617,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const
110
111 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
112 pci_ops);
113 - return bcma_core_irq(pc_host->pdev->core);
114 + return bcma_core_irq(pc_host->pdev->core, 0);
115 }
116 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
117 --- /dev/null
118 +++ b/drivers/bcma/driver_pcie2.c
119 @@ -0,0 +1,175 @@
120 +/*
121 + * Broadcom specific AMBA
122 + * PCIe Gen 2 Core
123 + *
124 + * Copyright 2014, Broadcom Corporation
125 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
126 + *
127 + * Licensed under the GNU/GPL. See COPYING for details.
128 + */
129 +
130 +#include "bcma_private.h"
131 +#include <linux/bcma/bcma.h>
132 +
133 +/**************************************************
134 + * R/W ops.
135 + **************************************************/
136 +
137 +#if 0
138 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
139 +{
140 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
141 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
142 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
143 +}
144 +#endif
145 +
146 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
147 + u32 val)
148 +{
149 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
150 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
151 +}
152 +
153 +/**************************************************
154 + * Init.
155 + **************************************************/
156 +
157 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
158 + bool enable)
159 +{
160 + u32 val;
161 +
162 + /* restore back to default */
163 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
164 + val |= PCIE2_CLKC_DLYPERST;
165 + val &= ~PCIE2_CLKC_DISSPROMLD;
166 + if (enable) {
167 + val &= ~PCIE2_CLKC_DLYPERST;
168 + val |= PCIE2_CLKC_DISSPROMLD;
169 + }
170 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
171 + /* flush */
172 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
173 +}
174 +
175 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
176 +{
177 + /* LTR0 */
178 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
179 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
180 + /* LTR1 */
181 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
182 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
183 + /* LTR2 */
184 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
185 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
186 +}
187 +
188 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
189 +{
190 + u8 core_rev = pcie2->core->id.rev;
191 + u32 devstsctr2;
192 +
193 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
194 + return;
195 +
196 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
197 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
198 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
199 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
200 + /* force the right LTR values */
201 + bcma_core_pcie2_set_ltr_vals(pcie2);
202 +
203 + /* TODO:
204 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
205 +
206 + /* enable the LTR */
207 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
208 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
209 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
210 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
211 +
212 + /* set the LTR state to be active */
213 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
214 + PCIE2_LTR_ACTIVE);
215 + usleep_range(1000, 2000);
216 +
217 + /* set the LTR state to be sleep */
218 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
219 + PCIE2_LTR_SLEEP);
220 + usleep_range(1000, 2000);
221 + }
222 +}
223 +
224 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
225 +{
226 + u8 core_rev = pcie2->core->id.rev;
227 + bool pciewar160, pciewar162;
228 +
229 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
230 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
231 + core_rev == 9 || core_rev == 11;
232 +
233 + if (!pciewar160 && !pciewar162)
234 + return;
235 +
236 +/* TODO */
237 +#if 0
238 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
239 + PCIE_DISABLE_L1CLK_GATING);
240 +#if 0
241 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
242 + PCIEGEN2_COE_PVT_TL_CTRL_0);
243 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
244 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
245 +#endif
246 +#endif
247 +}
248 +
249 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
250 +{
251 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
252 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
253 +}
254 +
255 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
256 +{
257 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
258 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
259 +}
260 +
261 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
262 +{
263 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
264 + u8 core_rev = pcie2->core->id.rev;
265 + u32 alp_khz, pm_value;
266 +
267 + if (core_rev <= 13) {
268 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
269 + pm_value = (1000000 * 2) / alp_khz;
270 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
271 + PCIE2_PVT_REG_PM_CLK_PERIOD);
272 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
273 + }
274 +}
275 +
276 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
277 +{
278 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
279 + u32 tmp;
280 +
281 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
282 + if ((tmp & 0xe) >> 1 == 2)
283 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
284 +
285 + /* TODO: Do we need pcie_reqsize? */
286 +
287 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
288 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
289 + bcma_core_pcie2_hw_ltr_war(pcie2);
290 + pciedev_crwlpciegen2(pcie2);
291 + pciedev_reg_pm_clk_period(pcie2);
292 + pciedev_crwlpciegen2_180(pcie2);
293 + pciedev_crwlpciegen2_182(pcie2);
294 +}
295 --- a/drivers/bcma/host_pci.c
296 +++ b/drivers/bcma/host_pci.c
297 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
298 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
299 bus->boardinfo.type = bus->host_pci->subsystem_device;
300
301 + /* Initialize struct, detect chip */
302 + bcma_init_bus(bus);
303 +
304 /* Register */
305 err = bcma_bus_register(bus);
306 if (err)
307 @@ -272,14 +275,18 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
308 static const struct pci_device_id bcma_pci_bridge_tbl[] = {
309 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
310 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
311 - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
312 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
313 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
314 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
315 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
316 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
317 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
318 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
319 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
320 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
321 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
322 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
323 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
324 { 0, },
325 };
326 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
327 --- a/drivers/bcma/main.c
328 +++ b/drivers/bcma/main.c
329 @@ -10,6 +10,8 @@
330 #include <linux/platform_device.h>
331 #include <linux/bcma/bcma.h>
332 #include <linux/slab.h>
333 +#include <linux/of_address.h>
334 +#include <linux/of_irq.h>
335
336 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
337 MODULE_LICENSE("GPL");
338 @@ -120,56 +122,195 @@ static void bcma_release_core_dev(struct
339 kfree(core);
340 }
341
342 -static int bcma_register_cores(struct bcma_bus *bus)
343 +static bool bcma_is_core_needed_early(u16 core_id)
344 +{
345 + switch (core_id) {
346 + case BCMA_CORE_NS_NAND:
347 + case BCMA_CORE_NS_QSPI:
348 + return true;
349 + }
350 +
351 + return false;
352 +}
353 +
354 +#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS)
355 +static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
356 + struct bcma_device *core)
357 +{
358 + struct device_node *node;
359 + u64 size;
360 + const __be32 *reg;
361 +
362 + if (!parent || !parent->dev.of_node)
363 + return NULL;
364 +
365 + for_each_child_of_node(parent->dev.of_node, node) {
366 + reg = of_get_address(node, 0, &size, NULL);
367 + if (!reg)
368 + continue;
369 + if (of_translate_address(node, reg) == core->addr)
370 + return node;
371 + }
372 + return NULL;
373 +}
374 +
375 +static int bcma_of_irq_parse(struct platform_device *parent,
376 + struct bcma_device *core,
377 + struct of_phandle_args *out_irq, int num)
378 +{
379 + __be32 laddr[1];
380 + int rc;
381 +
382 + if (core->dev.of_node) {
383 + rc = of_irq_parse_one(core->dev.of_node, num, out_irq);
384 + if (!rc)
385 + return rc;
386 + }
387 +
388 + out_irq->np = parent->dev.of_node;
389 + out_irq->args_count = 1;
390 + out_irq->args[0] = num;
391 +
392 + laddr[0] = cpu_to_be32(core->addr);
393 + return of_irq_parse_raw(laddr, out_irq);
394 +}
395 +
396 +static unsigned int bcma_of_get_irq(struct platform_device *parent,
397 + struct bcma_device *core, int num)
398 +{
399 + struct of_phandle_args out_irq;
400 + int ret;
401 +
402 + if (!parent || !parent->dev.of_node)
403 + return 0;
404 +
405 + ret = bcma_of_irq_parse(parent, core, &out_irq, num);
406 + if (ret) {
407 + bcma_debug(core->bus, "bcma_of_get_irq() failed with rc=%d\n",
408 + ret);
409 + return 0;
410 + }
411 +
412 + return irq_create_of_mapping(&out_irq);
413 +}
414 +
415 +static void bcma_of_fill_device(struct platform_device *parent,
416 + struct bcma_device *core)
417 +{
418 + struct device_node *node;
419 +
420 + node = bcma_of_find_child_device(parent, core);
421 + if (node)
422 + core->dev.of_node = node;
423 +
424 + core->irq = bcma_of_get_irq(parent, core, 0);
425 +}
426 +#else
427 +static void bcma_of_fill_device(struct platform_device *parent,
428 + struct bcma_device *core)
429 +{
430 +}
431 +static inline unsigned int bcma_of_get_irq(struct platform_device *parent,
432 + struct bcma_device *core, int num)
433 +{
434 + return 0;
435 +}
436 +#endif /* CONFIG_OF */
437 +
438 +unsigned int bcma_core_irq(struct bcma_device *core, int num)
439 +{
440 + struct bcma_bus *bus = core->bus;
441 + unsigned int mips_irq;
442 +
443 + switch (bus->hosttype) {
444 + case BCMA_HOSTTYPE_PCI:
445 + return bus->host_pci->irq;
446 + case BCMA_HOSTTYPE_SOC:
447 + if (bus->drv_mips.core && num == 0) {
448 + mips_irq = bcma_core_mips_irq(core);
449 + return mips_irq <= 4 ? mips_irq + 2 : 0;
450 + }
451 + if (bus->host_pdev)
452 + return bcma_of_get_irq(bus->host_pdev, core, num);
453 + return 0;
454 + case BCMA_HOSTTYPE_SDIO:
455 + return 0;
456 + }
457 +
458 + return 0;
459 +}
460 +EXPORT_SYMBOL(bcma_core_irq);
461 +
462 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)
463 +{
464 + core->dev.release = bcma_release_core_dev;
465 + core->dev.bus = &bcma_bus_type;
466 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
467 +
468 + switch (bus->hosttype) {
469 + case BCMA_HOSTTYPE_PCI:
470 + core->dev.parent = &bus->host_pci->dev;
471 + core->dma_dev = &bus->host_pci->dev;
472 + core->irq = bus->host_pci->irq;
473 + break;
474 + case BCMA_HOSTTYPE_SOC:
475 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
476 + if (bus->host_pdev) {
477 + core->dma_dev = &bus->host_pdev->dev;
478 + core->dev.parent = &bus->host_pdev->dev;
479 + bcma_of_fill_device(bus->host_pdev, core);
480 + } else {
481 + core->dma_dev = &core->dev;
482 + }
483 + break;
484 + case BCMA_HOSTTYPE_SDIO:
485 + break;
486 + }
487 +}
488 +
489 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
490 +{
491 + int err;
492 +
493 + err = device_register(&core->dev);
494 + if (err) {
495 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
496 + core->id.id);
497 + put_device(&core->dev);
498 + return;
499 + }
500 + core->dev_registered = true;
501 +}
502 +
503 +static int bcma_register_devices(struct bcma_bus *bus)
504 {
505 struct bcma_device *core;
506 - int err, dev_id = 0;
507 + int err;
508
509 list_for_each_entry(core, &bus->cores, list) {
510 /* We support that cores ourself */
511 switch (core->id.id) {
512 case BCMA_CORE_4706_CHIPCOMMON:
513 case BCMA_CORE_CHIPCOMMON:
514 + case BCMA_CORE_NS_CHIPCOMMON_B:
515 case BCMA_CORE_PCI:
516 case BCMA_CORE_PCIE:
517 + case BCMA_CORE_PCIE2:
518 case BCMA_CORE_MIPS_74K:
519 case BCMA_CORE_4706_MAC_GBIT_COMMON:
520 continue;
521 }
522
523 + /* Early cores were already registered */
524 + if (bcma_is_core_needed_early(core->id.id))
525 + continue;
526 +
527 /* Only first GMAC core on BCM4706 is connected and working */
528 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
529 core->core_unit > 0)
530 continue;
531
532 - core->dev.release = bcma_release_core_dev;
533 - core->dev.bus = &bcma_bus_type;
534 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
535 -
536 - switch (bus->hosttype) {
537 - case BCMA_HOSTTYPE_PCI:
538 - core->dev.parent = &bus->host_pci->dev;
539 - core->dma_dev = &bus->host_pci->dev;
540 - core->irq = bus->host_pci->irq;
541 - break;
542 - case BCMA_HOSTTYPE_SOC:
543 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
544 - core->dma_dev = &core->dev;
545 - break;
546 - case BCMA_HOSTTYPE_SDIO:
547 - break;
548 - }
549 -
550 - err = device_register(&core->dev);
551 - if (err) {
552 - bcma_err(bus,
553 - "Could not register dev for core 0x%03X\n",
554 - core->id.id);
555 - put_device(&core->dev);
556 - continue;
557 - }
558 - core->dev_registered = true;
559 - dev_id++;
560 + bcma_register_core(bus, core);
561 }
562
563 #ifdef CONFIG_BCMA_DRIVER_MIPS
564 @@ -246,6 +387,12 @@ int bcma_bus_register(struct bcma_bus *b
565 bcma_core_chipcommon_early_init(&bus->drv_cc);
566 }
567
568 + /* Cores providing flash access go before SPROM init */
569 + list_for_each_entry(core, &bus->cores, list) {
570 + if (bcma_is_core_needed_early(core->id.id))
571 + bcma_register_core(bus, core);
572 + }
573 +
574 /* Try to get SPROM */
575 err = bcma_sprom_get(bus);
576 if (err == -ENOENT) {
577 @@ -260,6 +407,13 @@ int bcma_bus_register(struct bcma_bus *b
578 bcma_core_chipcommon_init(&bus->drv_cc);
579 }
580
581 + /* Init CC core */
582 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
583 + if (core) {
584 + bus->drv_cc_b.core = core;
585 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
586 + }
587 +
588 /* Init MIPS core */
589 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
590 if (core) {
591 @@ -281,6 +435,13 @@ int bcma_bus_register(struct bcma_bus *b
592 bcma_core_pci_init(&bus->drv_pci[1]);
593 }
594
595 + /* Init PCIe Gen 2 core */
596 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
597 + if (core) {
598 + bus->drv_pcie2.core = core;
599 + bcma_core_pcie2_init(&bus->drv_pcie2);
600 + }
601 +
602 /* Init GBIT MAC COMMON core */
603 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
604 if (core) {
605 @@ -289,7 +450,7 @@ int bcma_bus_register(struct bcma_bus *b
606 }
607
608 /* Register found cores */
609 - bcma_register_cores(bus);
610 + bcma_register_devices(bus);
611
612 bcma_info(bus, "Bus registered\n");
613
614 @@ -307,6 +468,8 @@ void bcma_bus_unregister(struct bcma_bus
615 else if (err)
616 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
617
618 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
619 +
620 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
621 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
622 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
623 @@ -326,8 +489,6 @@ int __init bcma_bus_early_register(struc
624 struct bcma_device *core;
625 struct bcma_device_id match;
626
627 - bcma_init_bus(bus);
628 -
629 match.manuf = BCMA_MANUF_BCM;
630 match.id = bcma_cc_core_id(bus);
631 match.class = BCMA_CL_SIM;
632 @@ -486,6 +647,11 @@ static int __init bcma_modinit(void)
633 if (err)
634 return err;
635
636 + err = bcma_host_soc_register_driver();
637 + if (err) {
638 + pr_err("SoC host initialization failed\n");
639 + err = 0;
640 + }
641 #ifdef CONFIG_BCMA_HOST_PCI
642 err = bcma_host_pci_init();
643 if (err) {
644 @@ -503,6 +669,7 @@ static void __exit bcma_modexit(void)
645 #ifdef CONFIG_BCMA_HOST_PCI
646 bcma_host_pci_exit();
647 #endif
648 + bcma_host_soc_unregister_driver();
649 bus_unregister(&bcma_bus_type);
650 }
651 module_exit(bcma_modexit)
652 --- a/drivers/bcma/sprom.c
653 +++ b/drivers/bcma/sprom.c
654 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
655 SPEX(_field[7], _offset + 14, _mask, _shift); \
656 } while (0)
657
658 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
659 +{
660 + u16 v;
661 + u8 gain;
662 +
663 + v = in[SPOFF(offset)];
664 + gain = (v & mask) >> shift;
665 + if (gain == 0xFF) {
666 + gain = 8; /* If unset use 2dBm */
667 + } else {
668 + /* Q5.2 Fractional part is stored in 0xC0 */
669 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
670 + }
671 +
672 + return (s8)gain;
673 +}
674 +
675 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
676 {
677 u16 v, o;
678 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
679 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
680
681 /* Extract the antenna gain values. */
682 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
683 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
684 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
685 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
686 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
687 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
688 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
689 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
690 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
691 + SSB_SPROM8_AGAIN01,
692 + SSB_SPROM8_AGAIN0,
693 + SSB_SPROM8_AGAIN0_SHIFT);
694 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
695 + SSB_SPROM8_AGAIN01,
696 + SSB_SPROM8_AGAIN1,
697 + SSB_SPROM8_AGAIN1_SHIFT);
698 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
699 + SSB_SPROM8_AGAIN23,
700 + SSB_SPROM8_AGAIN2,
701 + SSB_SPROM8_AGAIN2_SHIFT);
702 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
703 + SSB_SPROM8_AGAIN23,
704 + SSB_SPROM8_AGAIN3,
705 + SSB_SPROM8_AGAIN3_SHIFT);
706
707 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
708 SSB_SPROM8_LEDDC_ON_SHIFT);
709 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
710 /* for these chips OTP is always available */
711 present = true;
712 break;
713 + case BCMA_CHIP_ID_BCM43131:
714 + case BCMA_CHIP_ID_BCM43217:
715 case BCMA_CHIP_ID_BCM43227:
716 case BCMA_CHIP_ID_BCM43228:
717 case BCMA_CHIP_ID_BCM43428:
718 --- a/include/linux/bcma/bcma.h
719 +++ b/include/linux/bcma/bcma.h
720 @@ -6,6 +6,7 @@
721
722 #include <linux/bcma/bcma_driver_chipcommon.h>
723 #include <linux/bcma/bcma_driver_pci.h>
724 +#include <linux/bcma/bcma_driver_pcie2.h>
725 #include <linux/bcma/bcma_driver_mips.h>
726 #include <linux/bcma/bcma_driver_gmac_cmn.h>
727 #include <linux/ssb/ssb.h> /* SPROM sharing */
728 @@ -72,17 +73,17 @@ struct bcma_host_ops {
729 /* Core-ID values. */
730 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
731 #define BCMA_CORE_4706_CHIPCOMMON 0x500
732 -#define BCMA_CORE_PCIEG2 0x501
733 -#define BCMA_CORE_DMA 0x502
734 -#define BCMA_CORE_SDIO3 0x503
735 -#define BCMA_CORE_USB20 0x504
736 -#define BCMA_CORE_USB30 0x505
737 -#define BCMA_CORE_A9JTAG 0x506
738 -#define BCMA_CORE_DDR23 0x507
739 -#define BCMA_CORE_ROM 0x508
740 -#define BCMA_CORE_NAND 0x509
741 -#define BCMA_CORE_QSPI 0x50A
742 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
743 +#define BCMA_CORE_NS_PCIEG2 0x501
744 +#define BCMA_CORE_NS_DMA 0x502
745 +#define BCMA_CORE_NS_SDIO3 0x503
746 +#define BCMA_CORE_NS_USB20 0x504
747 +#define BCMA_CORE_NS_USB30 0x505
748 +#define BCMA_CORE_NS_A9JTAG 0x506
749 +#define BCMA_CORE_NS_DDR23 0x507
750 +#define BCMA_CORE_NS_ROM 0x508
751 +#define BCMA_CORE_NS_NAND 0x509
752 +#define BCMA_CORE_NS_QSPI 0x50A
753 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
754 #define BCMA_CORE_4706_SOC_RAM 0x50E
755 #define BCMA_CORE_ARMCA9 0x510
756 #define BCMA_CORE_4706_MAC_GBIT 0x52D
757 @@ -157,6 +158,9 @@ struct bcma_host_ops {
758 /* Chip IDs of PCIe devices */
759 #define BCMA_CHIP_ID_BCM4313 0x4313
760 #define BCMA_CHIP_ID_BCM43142 43142
761 +#define BCMA_CHIP_ID_BCM43131 43131
762 +#define BCMA_CHIP_ID_BCM43217 43217
763 +#define BCMA_CHIP_ID_BCM43222 43222
764 #define BCMA_CHIP_ID_BCM43224 43224
765 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
766 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
767 @@ -263,7 +267,7 @@ struct bcma_device {
768 u8 core_unit;
769
770 u32 addr;
771 - u32 addr1;
772 + u32 addr_s[8];
773 u32 wrap;
774
775 void __iomem *io_addr;
776 @@ -319,6 +323,8 @@ struct bcma_bus {
777 struct pci_dev *host_pci;
778 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
779 struct sdio_func *host_sdio;
780 + /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
781 + struct platform_device *host_pdev;
782 };
783
784 struct bcma_chipinfo chipinfo;
785 @@ -328,11 +334,12 @@ struct bcma_bus {
786 struct bcma_device *mapped_core;
787 struct list_head cores;
788 u8 nr_cores;
789 - u8 init_done:1;
790 u8 num;
791
792 struct bcma_drv_cc drv_cc;
793 + struct bcma_drv_cc_b drv_cc_b;
794 struct bcma_drv_pci drv_pci[2];
795 + struct bcma_drv_pcie2 drv_pcie2;
796 struct bcma_drv_mips drv_mips;
797 struct bcma_drv_gmac_cmn drv_gmac_cmn;
798
799 @@ -440,4 +447,6 @@ extern u32 bcma_chipco_pll_read(struct b
800 #define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
801 extern u32 bcma_core_dma_translation(struct bcma_device *core);
802
803 +extern unsigned int bcma_core_irq(struct bcma_device *core, int num);
804 +
805 #endif /* LINUX_BCMA_H_ */
806 --- a/include/linux/bcma/bcma_driver_mips.h
807 +++ b/include/linux/bcma/bcma_driver_mips.h
808 @@ -43,12 +43,12 @@ struct bcma_drv_mips {
809 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
810 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
811
812 -extern unsigned int bcma_core_irq(struct bcma_device *core);
813 +extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
814 #else
815 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
816 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
817
818 -static inline unsigned int bcma_core_irq(struct bcma_device *core)
819 +static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev)
820 {
821 return 0;
822 }
823 --- /dev/null
824 +++ b/include/linux/bcma/bcma_driver_pcie2.h
825 @@ -0,0 +1,158 @@
826 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
827 +#define LINUX_BCMA_DRIVER_PCIE2_H_
828 +
829 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
830 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
831 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
832 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
833 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
834 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
835 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
836 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
837 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
838 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
839 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
840 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
841 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
842 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
843 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
844 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
845 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
846 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
847 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
848 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
849 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
850 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
851 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
852 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
853 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
854 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
855 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
856 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
857 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
858 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
859 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
860 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
861 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
862 +#define PCIE2_LTR_ACTIVE 2
863 +#define PCIE2_LTR_ACTIVE_IDLE 1
864 +#define PCIE2_LTR_SLEEP 0
865 +#define PCIE2_LTR_FINAL_MASK 0x300
866 +#define PCIE2_LTR_FINAL_SHIFT 8
867 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
868 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
869 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
870 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
871 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
872 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
873 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
874 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
875 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
876 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
877 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
878 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
879 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
880 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
881 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
882 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
883 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
884 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
885 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
886 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
887 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
888 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
889 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
890 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
891 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
892 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
893 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
894 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
895 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
896 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
897 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
898 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
899 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
900 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
901 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
902 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
903 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
904 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
905 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
906 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
907 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
908 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
909 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
910 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
911 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
912 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
913 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
914 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
915 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
916 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
917 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
918 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
919 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
920 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
921 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
922 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
923 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
924 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
925 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
926 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
927 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
928 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
929 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
930 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
931 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
932 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
933 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
934 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
935 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
936 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
937 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
938 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
939 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
940 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
941 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
942 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
943 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
944 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
945 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
946 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
947 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
948 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
949 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
950 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
951 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
952 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
953 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
954 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
955 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
956 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
957 +
958 +/* PCIE gen2 config regs */
959 +#define PCIE2_INTSTATUS 0x090
960 +#define PCIE2_INTMASK 0x094
961 +#define PCIE2_SBMBX 0x098
962 +
963 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
964 +
965 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
966 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
967 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
968 +
969 +struct bcma_drv_pcie2 {
970 + struct bcma_device *core;
971 +};
972 +
973 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
974 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
975 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
976 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
977 +
978 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
979 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
980 +
981 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
982 +
983 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
984 --- a/drivers/bcma/scan.c
985 +++ b/drivers/bcma/scan.c
986 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
987 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
988 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
989 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
990 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
991 - { BCMA_CORE_DMA, "DMA" },
992 - { BCMA_CORE_SDIO3, "SDIO3" },
993 - { BCMA_CORE_USB20, "USB 2.0" },
994 - { BCMA_CORE_USB30, "USB 3.0" },
995 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
996 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
997 - { BCMA_CORE_ROM, "ROM" },
998 - { BCMA_CORE_NAND, "NAND flash controller" },
999 - { BCMA_CORE_QSPI, "SPI flash controller" },
1000 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
1001 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
1002 + { BCMA_CORE_NS_DMA, "DMA" },
1003 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
1004 + { BCMA_CORE_NS_USB20, "USB 2.0" },
1005 + { BCMA_CORE_NS_USB30, "USB 3.0" },
1006 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
1007 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
1008 + { BCMA_CORE_NS_ROM, "ROM" },
1009 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
1010 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
1011 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
1012 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1013 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1014 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1015 @@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
1016 struct bcma_device *core)
1017 {
1018 u32 tmp;
1019 - u8 i, j;
1020 + u8 i, j, k;
1021 s32 cia, cib;
1022 u8 ports[2], wrappers[2];
1023
1024 @@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
1025 /* Some specific cores don't need wrappers */
1026 switch (core->id.id) {
1027 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1028 + case BCMA_CORE_NS_CHIPCOMMON_B:
1029 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
1030 break;
1031 default:
1032 @@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm
1033 core->addr = tmp;
1034
1035 /* get & parse slave ports */
1036 + k = 0;
1037 for (i = 0; i < ports[1]; i++) {
1038 for (j = 0; ; j++) {
1039 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1040 @@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm
1041 /* pr_debug("erom: slave port %d "
1042 * "has %d descriptors\n", i, j); */
1043 break;
1044 - } else {
1045 - if (i == 0 && j == 0)
1046 - core->addr1 = tmp;
1047 + } else if (k < ARRAY_SIZE(core->addr_s)) {
1048 + core->addr_s[k] = tmp;
1049 + k++;
1050 }
1051 }
1052 }
1053 @@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm
1054 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
1055 if (!core->io_addr)
1056 return -ENOMEM;
1057 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
1058 - if (!core->io_wrap) {
1059 - iounmap(core->io_addr);
1060 - return -ENOMEM;
1061 + if (core->wrap) {
1062 + core->io_wrap = ioremap_nocache(core->wrap,
1063 + BCMA_CORE_SIZE);
1064 + if (!core->io_wrap) {
1065 + iounmap(core->io_addr);
1066 + return -ENOMEM;
1067 + }
1068 }
1069 }
1070 return 0;
1071 @@ -434,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
1072 {
1073 s32 tmp;
1074 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1075 -
1076 - if (bus->init_done)
1077 - return;
1078 + char chip_id[8];
1079
1080 INIT_LIST_HEAD(&bus->cores);
1081 bus->nr_cores = 0;
1082 @@ -447,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
1083 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1084 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1085 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1086 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1087 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
1088
1089 - bus->init_done = true;
1090 + snprintf(chip_id, ARRAY_SIZE(chip_id),
1091 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
1092 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
1093 + chip_id, chipinfo->rev, chipinfo->pkg);
1094 }
1095
1096 int bcma_bus_scan(struct bcma_bus *bus)
1097 @@ -460,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
1098
1099 int err, core_num = 0;
1100
1101 - bcma_init_bus(bus);
1102 -
1103 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
1104 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1105 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
1106 @@ -503,6 +505,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
1107 bus->nr_cores++;
1108 other_core = bcma_find_core_reverse(bus, core->id.id);
1109 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
1110 + bcma_prepare_core(bus, core);
1111
1112 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
1113 core->core_index, bcma_device_name(&core->id),
1114 --- a/drivers/bcma/host_soc.c
1115 +++ b/drivers/bcma/host_soc.c
1116 @@ -7,6 +7,9 @@
1117
1118 #include "bcma_private.h"
1119 #include "scan.h"
1120 +#include <linux/slab.h>
1121 +#include <linux/module.h>
1122 +#include <linux/of_address.h>
1123 #include <linux/bcma/bcma.h>
1124 #include <linux/bcma/bcma_soc.h>
1125
1126 @@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st
1127
1128 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
1129 {
1130 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
1131 + return ~0;
1132 return readl(core->io_wrap + offset);
1133 }
1134
1135 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
1136 u32 value)
1137 {
1138 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
1139 + return;
1140 writel(value, core->io_wrap + offset);
1141 }
1142
1143 @@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h
1144 int __init bcma_host_soc_register(struct bcma_soc *soc)
1145 {
1146 struct bcma_bus *bus = &soc->bus;
1147 - int err;
1148
1149 /* iomap only first core. We have to read some register on this core
1150 * to scan the bus.
1151 @@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct
1152 /* Host specific */
1153 bus->hosttype = BCMA_HOSTTYPE_SOC;
1154 bus->ops = &bcma_host_soc_ops;
1155 + bus->host_pdev = NULL;
1156
1157 - /* Register */
1158 + /* Initialize struct, detect chip */
1159 + bcma_init_bus(bus);
1160 +
1161 + return 0;
1162 +}
1163 +
1164 +int __init bcma_host_soc_init(struct bcma_soc *soc)
1165 +{
1166 + struct bcma_bus *bus = &soc->bus;
1167 + int err;
1168 +
1169 + /* Scan bus and initialize it */
1170 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
1171 if (err)
1172 iounmap(bus->mmio);
1173
1174 return err;
1175 }
1176 +
1177 +#ifdef CONFIG_OF
1178 +static int bcma_host_soc_probe(struct platform_device *pdev)
1179 +{
1180 + struct device *dev = &pdev->dev;
1181 + struct device_node *np = dev->of_node;
1182 + struct bcma_bus *bus;
1183 + int err;
1184 +
1185 + /* Alloc */
1186 + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
1187 + if (!bus)
1188 + return -ENOMEM;
1189 +
1190 + /* Map MMIO */
1191 + bus->mmio = of_iomap(np, 0);
1192 + if (!bus->mmio)
1193 + return -ENOMEM;
1194 +
1195 + /* Host specific */
1196 + bus->hosttype = BCMA_HOSTTYPE_SOC;
1197 + bus->ops = &bcma_host_soc_ops;
1198 + bus->host_pdev = pdev;
1199 +
1200 + /* Initialize struct, detect chip */
1201 + bcma_init_bus(bus);
1202 +
1203 + /* Register */
1204 + err = bcma_bus_register(bus);
1205 + if (err)
1206 + goto err_unmap_mmio;
1207 +
1208 + platform_set_drvdata(pdev, bus);
1209 +
1210 + return err;
1211 +
1212 +err_unmap_mmio:
1213 + iounmap(bus->mmio);
1214 + return err;
1215 +}
1216 +
1217 +static int bcma_host_soc_remove(struct platform_device *pdev)
1218 +{
1219 + struct bcma_bus *bus = platform_get_drvdata(pdev);
1220 +
1221 + bcma_bus_unregister(bus);
1222 + iounmap(bus->mmio);
1223 + platform_set_drvdata(pdev, NULL);
1224 +
1225 + return 0;
1226 +}
1227 +
1228 +static const struct of_device_id bcma_host_soc_of_match[] = {
1229 + { .compatible = "brcm,bus-axi", },
1230 + {},
1231 +};
1232 +MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
1233 +
1234 +static struct platform_driver bcma_host_soc_driver = {
1235 + .driver = {
1236 + .name = "bcma-host-soc",
1237 + .of_match_table = bcma_host_soc_of_match,
1238 + },
1239 + .probe = bcma_host_soc_probe,
1240 + .remove = bcma_host_soc_remove,
1241 +};
1242 +
1243 +int __init bcma_host_soc_register_driver(void)
1244 +{
1245 + return platform_driver_register(&bcma_host_soc_driver);
1246 +}
1247 +
1248 +void __exit bcma_host_soc_unregister_driver(void)
1249 +{
1250 + platform_driver_unregister(&bcma_host_soc_driver);
1251 +}
1252 +#endif /* CONFIG_OF */
1253 --- a/drivers/bcma/driver_mips.c
1254 +++ b/drivers/bcma/driver_mips.c
1255 @@ -21,6 +21,14 @@
1256 #include <linux/serial_reg.h>
1257 #include <linux/time.h>
1258
1259 +enum bcma_boot_dev {
1260 + BCMA_BOOT_DEV_UNK = 0,
1261 + BCMA_BOOT_DEV_ROM,
1262 + BCMA_BOOT_DEV_PARALLEL,
1263 + BCMA_BOOT_DEV_SERIAL,
1264 + BCMA_BOOT_DEV_NAND,
1265 +};
1266 +
1267 static const char * const part_probes[] = { "bcm47xxpart", NULL };
1268
1269 static struct physmap_flash_data bcma_pflash_data = {
1270 @@ -107,7 +115,7 @@ static u32 bcma_core_mips_irqflag(struct
1271 * If disabled, 5 is returned.
1272 * If not supported, 6 is returned.
1273 */
1274 -static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1275 +unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1276 {
1277 struct bcma_device *mdev = dev->bus->drv_mips.core;
1278 u32 irqflag;
1279 @@ -125,13 +133,6 @@ static unsigned int bcma_core_mips_irq(s
1280 return 5;
1281 }
1282
1283 -unsigned int bcma_core_irq(struct bcma_device *dev)
1284 -{
1285 - unsigned int mips_irq = bcma_core_mips_irq(dev);
1286 - return mips_irq <= 4 ? mips_irq + 2 : 0;
1287 -}
1288 -EXPORT_SYMBOL(bcma_core_irq);
1289 -
1290 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1291 {
1292 unsigned int oldirq = bcma_core_mips_irq(dev);
1293 @@ -229,11 +230,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1294 }
1295 EXPORT_SYMBOL(bcma_cpu_clock);
1296
1297 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
1298 +{
1299 + struct bcma_drv_cc *cc = &bus->drv_cc;
1300 + u8 cc_rev = cc->core->id.rev;
1301 +
1302 + if (cc_rev == 42) {
1303 + struct bcma_device *core;
1304 +
1305 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
1306 + if (core) {
1307 + switch (bcma_aread32(core, BCMA_IOST) &
1308 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
1309 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
1310 + return BCMA_BOOT_DEV_SERIAL;
1311 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
1312 + return BCMA_BOOT_DEV_NAND;
1313 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
1314 + default:
1315 + return BCMA_BOOT_DEV_ROM;
1316 + }
1317 + }
1318 + } else {
1319 + if (cc_rev == 38) {
1320 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
1321 + return BCMA_BOOT_DEV_NAND;
1322 + else if (cc->status & BIT(5))
1323 + return BCMA_BOOT_DEV_ROM;
1324 + }
1325 +
1326 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
1327 + BCMA_CC_FLASHT_PARA)
1328 + return BCMA_BOOT_DEV_PARALLEL;
1329 + else
1330 + return BCMA_BOOT_DEV_SERIAL;
1331 + }
1332 +
1333 + return BCMA_BOOT_DEV_SERIAL;
1334 +}
1335 +
1336 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1337 {
1338 struct bcma_bus *bus = mcore->core->bus;
1339 struct bcma_drv_cc *cc = &bus->drv_cc;
1340 struct bcma_pflash *pflash = &cc->pflash;
1341 + enum bcma_boot_dev boot_dev;
1342
1343 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1344 case BCMA_CC_FLASHT_STSER:
1345 @@ -269,6 +310,20 @@ static void bcma_core_mips_flash_detect(
1346 bcma_nflash_init(cc);
1347 }
1348 }
1349 +
1350 + /* Determine flash type this SoC boots from */
1351 + boot_dev = bcma_boot_dev(bus);
1352 + switch (boot_dev) {
1353 + case BCMA_BOOT_DEV_PARALLEL:
1354 + case BCMA_BOOT_DEV_SERIAL:
1355 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
1356 + break;
1357 + case BCMA_BOOT_DEV_NAND:
1358 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
1359 + break;
1360 + default:
1361 + break;
1362 + }
1363 }
1364
1365 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1366 @@ -361,7 +416,7 @@ void bcma_core_mips_init(struct bcma_drv
1367 break;
1368 default:
1369 list_for_each_entry(core, &bus->cores, list) {
1370 - core->irq = bcma_core_irq(core);
1371 + core->irq = bcma_core_irq(core, 0);
1372 }
1373 bcma_err(bus,
1374 "Unknown device (0x%x) found, can not configure IRQs\n",
1375 --- a/include/linux/bcma/bcma_regs.h
1376 +++ b/include/linux/bcma/bcma_regs.h
1377 @@ -39,6 +39,11 @@
1378 #define BCMA_RESET_CTL_RESET 0x0001
1379 #define BCMA_RESET_ST 0x0804
1380
1381 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
1382 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
1383 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
1384 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
1385 +
1386 /* BCMA PCI config space registers. */
1387 #define BCMA_PCI_PMCSR 0x44
1388 #define BCMA_PCI_PE 0x100
1389 --- a/drivers/usb/host/bcma-hcd.c
1390 +++ b/drivers/usb/host/bcma-hcd.c
1391 @@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
1392 bcma_hcd_init_chip(dev);
1393
1394 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
1395 - ohci_addr = dev->addr1;
1396 + ohci_addr = dev->addr_s[0];
1397 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
1398 && chipinfo->rev == 0)
1399 ohci_addr = 0x18009000;
1400 --- a/drivers/bcma/bcma_private.h
1401 +++ b/drivers/bcma/bcma_private.h
1402 @@ -24,6 +24,7 @@ struct bcma_bus;
1403 /* main.c */
1404 bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1405 int timeout);
1406 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core);
1407 int bcma_bus_register(struct bcma_bus *bus);
1408 void bcma_bus_unregister(struct bcma_bus *bus);
1409 int __init bcma_bus_early_register(struct bcma_bus *bus,
1410 @@ -50,6 +51,10 @@ void bcma_chipco_serial_init(struct bcma
1411 extern struct platform_device bcma_pflash_dev;
1412 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1413
1414 +/* driver_chipcommon_b.c */
1415 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
1416 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
1417 +
1418 /* driver_chipcommon_pmu.c */
1419 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
1420 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
1421 @@ -84,6 +89,20 @@ extern int __init bcma_host_pci_init(voi
1422 extern void __exit bcma_host_pci_exit(void);
1423 #endif /* CONFIG_BCMA_HOST_PCI */
1424
1425 +/* host_soc.c */
1426 +#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF)
1427 +extern int __init bcma_host_soc_register_driver(void);
1428 +extern void __exit bcma_host_soc_unregister_driver(void);
1429 +#else
1430 +static inline int __init bcma_host_soc_register_driver(void)
1431 +{
1432 + return 0;
1433 +}
1434 +static inline void __exit bcma_host_soc_unregister_driver(void)
1435 +{
1436 +}
1437 +#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
1438 +
1439 /* driver_pci.c */
1440 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
1441
1442 --- /dev/null
1443 +++ b/drivers/bcma/driver_chipcommon_b.c
1444 @@ -0,0 +1,61 @@
1445 +/*
1446 + * Broadcom specific AMBA
1447 + * ChipCommon B Unit driver
1448 + *
1449 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
1450 + *
1451 + * Licensed under the GNU/GPL. See COPYING for details.
1452 + */
1453 +
1454 +#include "bcma_private.h"
1455 +#include <linux/export.h>
1456 +#include <linux/bcma/bcma.h>
1457 +
1458 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
1459 + u32 value, int timeout)
1460 +{
1461 + unsigned long deadline = jiffies + timeout;
1462 + u32 val;
1463 +
1464 + do {
1465 + val = readl(addr);
1466 + if ((val & mask) == value)
1467 + return true;
1468 + cpu_relax();
1469 + udelay(10);
1470 + } while (!time_after_eq(jiffies, deadline));
1471 +
1472 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
1473 +
1474 + return false;
1475 +}
1476 +
1477 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
1478 +{
1479 + struct bcma_bus *bus = ccb->core->bus;
1480 +
1481 + writel(offset, ccb->mii + 0x00);
1482 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1483 + writel(value, ccb->mii + 0x04);
1484 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1485 +}
1486 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
1487 +
1488 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
1489 +{
1490 + if (ccb->setup_done)
1491 + return 0;
1492 +
1493 + ccb->setup_done = 1;
1494 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
1495 + if (!ccb->mii)
1496 + return -ENOMEM;
1497 +
1498 + return 0;
1499 +}
1500 +
1501 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
1502 +{
1503 + if (ccb->mii)
1504 + iounmap(ccb->mii);
1505 +}
1506 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1507 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1508 @@ -644,6 +644,12 @@ struct bcma_drv_cc {
1509 #endif
1510 };
1511
1512 +struct bcma_drv_cc_b {
1513 + struct bcma_device *core;
1514 + u8 setup_done:1;
1515 + void __iomem *mii;
1516 +};
1517 +
1518 /* Register access */
1519 #define bcma_cc_read32(cc, offset) \
1520 bcma_read32((cc)->core, offset)
1521 @@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1522
1523 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1524
1525 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1526 +
1527 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1528 --- a/arch/mips/bcm47xx/setup.c
1529 +++ b/arch/mips/bcm47xx/setup.c
1530 @@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma
1531
1532 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
1533 if (err)
1534 + panic("Failed to register BCMA bus (err %d)", err);
1535 +
1536 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
1537 + if (err)
1538 panic("Failed to initialize BCMA bus (err %d)", err);
1539
1540 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
1541 --- a/include/linux/bcma/bcma_soc.h
1542 +++ b/include/linux/bcma/bcma_soc.h
1543 @@ -10,6 +10,7 @@ struct bcma_soc {
1544 };
1545
1546 int __init bcma_host_soc_register(struct bcma_soc *soc);
1547 +int __init bcma_host_soc_init(struct bcma_soc *soc);
1548
1549 int bcma_bus_register(struct bcma_bus *bus);
1550
1551 --- /dev/null
1552 +++ b/Documentation/devicetree/bindings/bus/bcma.txt
1553 @@ -0,0 +1,53 @@
1554 +Driver for ARM AXI Bus with Broadcom Plugins (bcma)
1555 +
1556 +Required properties:
1557 +
1558 +- compatible : brcm,bus-axi
1559 +
1560 +- reg : iomem address range of chipcommon core
1561 +
1562 +The cores on the AXI bus are automatically detected by bcma with the
1563 +memory ranges they are using and they get registered afterwards.
1564 +Automatic detection of the IRQ number is not working on
1565 +BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
1566 +them manually through device tree. Use an interrupt-map to specify the
1567 +IRQ used by the devices on the bus. The first address is just an index,
1568 +because we do not have any special register.
1569 +
1570 +The top-level axi bus may contain children representing attached cores
1571 +(devices). This is needed since some hardware details can't be auto
1572 +detected (e.g. IRQ numbers). Also some of the cores may be responsible
1573 +for extra things, e.g. ChipCommon providing access to the GPIO chip.
1574 +
1575 +Example:
1576 +
1577 + axi@18000000 {
1578 + compatible = "brcm,bus-axi";
1579 + reg = <0x18000000 0x1000>;
1580 + ranges = <0x00000000 0x18000000 0x00100000>;
1581 + #address-cells = <1>;
1582 + #size-cells = <1>;
1583 + #interrupt-cells = <1>;
1584 + interrupt-map-mask = <0x000fffff 0xffff>;
1585 + interrupt-map =
1586 + /* Ethernet Controller 0 */
1587 + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1588 +
1589 + /* Ethernet Controller 1 */
1590 + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1591 +
1592 + /* PCIe Controller 0 */
1593 + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1594 + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1595 + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1596 + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1597 + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1598 + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1599 +
1600 + chipcommon {
1601 + reg = <0x00000000 0x1000>;
1602 +
1603 + gpio-controller;
1604 + #gpio-cells = <2>;
1605 + };
1606 + };
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