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kernel: add missing bcma defines and header file for bcrmfmac
[openwrt/openwrt.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
46
47 If unsure, say N
48
49 +config SSB_DRIVER_GPIO
50 + bool "SSB GPIO driver"
51 + depends on SSB && GPIOLIB
52 + help
53 + Driver to provide access to the GPIO pins on the bus.
54 +
55 + If unsure, say N
56 +
57 endmenu
58 --- a/drivers/ssb/Makefile
59 +++ b/drivers/ssb/Makefile
60 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
61 # built-in drivers
62 ssb-y += driver_chipcommon.o
63 ssb-y += driver_chipcommon_pmu.o
64 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
65 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
66 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
67 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
68 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
69 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
70
71 # b43 pci-ssb-bridge driver
72 # Not strictly a part of SSB, but kept here for convenience
73 --- a/drivers/ssb/b43_pci_bridge.c
74 +++ b/drivers/ssb/b43_pci_bridge.c
75 @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
76 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
77 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
78 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
79 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
80 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
81 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
82 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
83 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
84 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
85 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
86 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
87 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
88 { 0, },
89 };
90 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
91 --- a/drivers/ssb/driver_chipcommon.c
92 +++ b/drivers/ssb/driver_chipcommon.c
93 @@ -4,6 +4,7 @@
94 *
95 * Copyright 2005, Broadcom Corporation
96 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
97 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
98 *
99 * Licensed under the GNU/GPL. See COPYING for details.
100 */
101 @@ -12,6 +13,7 @@
102 #include <linux/ssb/ssb_regs.h>
103 #include <linux/export.h>
104 #include <linux/pci.h>
105 +#include <linux/bcm47xx_wdt.h>
106
107 #include "ssb_private.h"
108
109 @@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
110 cc->fast_pwrup_delay = tmp;
111 }
112
113 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
114 +{
115 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
116 + return ssb_pmu_get_alp_clock(cc);
117 +
118 + return 20000000;
119 +}
120 +
121 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
122 +{
123 + u32 nb;
124 +
125 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
126 + if (cc->dev->id.revision < 26)
127 + nb = 16;
128 + else
129 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
130 + } else {
131 + nb = 28;
132 + }
133 + if (nb == 32)
134 + return 0xffffffff;
135 + else
136 + return (1 << nb) - 1;
137 +}
138 +
139 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
140 +{
141 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
142 +
143 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
144 + return 0;
145 +
146 + return ssb_chipco_watchdog_timer_set(cc, ticks);
147 +}
148 +
149 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
150 +{
151 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
152 + u32 ticks;
153 +
154 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
155 + return 0;
156 +
157 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
158 + return ticks / cc->ticks_per_ms;
159 +}
160 +
161 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
162 +{
163 + struct ssb_bus *bus = cc->dev->bus;
164 +
165 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
166 + /* based on 32KHz ILP clock */
167 + return 32;
168 + } else {
169 + if (cc->dev->id.revision < 18)
170 + return ssb_clockspeed(bus) / 1000;
171 + else
172 + return ssb_chipco_alp_clock(cc) / 1000;
173 + }
174 +}
175 +
176 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
177 {
178 if (!cc->dev)
179 return; /* We don't have a ChipCommon */
180 +
181 + spin_lock_init(&cc->gpio_lock);
182 +
183 if (cc->dev->id.revision >= 11)
184 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
185 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
186 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
187 chipco_powercontrol_init(cc);
188 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
189 calc_fast_powerup_delay(cc);
190 +
191 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
192 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
193 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
194 + }
195 }
196
197 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
198 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
199 }
200
201 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
202 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
203 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
204 {
205 - /* instant NMI */
206 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
207 + u32 maxt;
208 + enum ssb_clkmode clkmode;
209 +
210 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
211 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
212 + if (ticks == 1)
213 + ticks = 2;
214 + else if (ticks > maxt)
215 + ticks = maxt;
216 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
217 + } else {
218 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
219 + ssb_chipco_set_clockmode(cc, clkmode);
220 + if (ticks > maxt)
221 + ticks = maxt;
222 + /* instant NMI */
223 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
224 + }
225 + return ticks;
226 }
227
228 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
229 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
230
231 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
232 {
233 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
234 + unsigned long flags;
235 + u32 res = 0;
236 +
237 + spin_lock_irqsave(&cc->gpio_lock, flags);
238 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
239 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
240 +
241 + return res;
242 }
243
244 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
245 {
246 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
247 + unsigned long flags;
248 + u32 res = 0;
249 +
250 + spin_lock_irqsave(&cc->gpio_lock, flags);
251 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
252 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
253 +
254 + return res;
255 }
256
257 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
258 {
259 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
260 + unsigned long flags;
261 + u32 res = 0;
262 +
263 + spin_lock_irqsave(&cc->gpio_lock, flags);
264 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
265 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
266 +
267 + return res;
268 }
269 EXPORT_SYMBOL(ssb_chipco_gpio_control);
270
271 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
272 {
273 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
274 + unsigned long flags;
275 + u32 res = 0;
276 +
277 + spin_lock_irqsave(&cc->gpio_lock, flags);
278 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
279 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
280 +
281 + return res;
282 }
283
284 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
285 {
286 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
287 + unsigned long flags;
288 + u32 res = 0;
289 +
290 + spin_lock_irqsave(&cc->gpio_lock, flags);
291 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
292 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
293 +
294 + return res;
295 +}
296 +
297 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
298 +{
299 + unsigned long flags;
300 + u32 res = 0;
301 +
302 + if (cc->dev->id.revision < 20)
303 + return 0xffffffff;
304 +
305 + spin_lock_irqsave(&cc->gpio_lock, flags);
306 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
307 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
308 +
309 + return res;
310 +}
311 +
312 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
313 +{
314 + unsigned long flags;
315 + u32 res = 0;
316 +
317 + if (cc->dev->id.revision < 20)
318 + return 0xffffffff;
319 +
320 + spin_lock_irqsave(&cc->gpio_lock, flags);
321 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
322 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
323 +
324 + return res;
325 }
326
327 #ifdef CONFIG_SSB_SERIAL
328 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
329 chipco_read32(cc, SSB_CHIPCO_CORECTL)
330 | SSB_CHIPCO_CORECTL_UARTCLK0);
331 } else if ((ccrev >= 11) && (ccrev != 15)) {
332 - /* Fixed ALP clock */
333 - baud_base = 20000000;
334 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
335 - /* FIXME: baud_base is different for devices with a PMU */
336 - SSB_WARN_ON(1);
337 - }
338 + baud_base = ssb_chipco_alp_clock(cc);
339 div = 1;
340 if (ccrev >= 21) {
341 /* Turn off UART clock before switching clocksource. */
342 --- a/drivers/ssb/driver_chipcommon_pmu.c
343 +++ b/drivers/ssb/driver_chipcommon_pmu.c
344 @@ -13,6 +13,9 @@
345 #include <linux/ssb/ssb_driver_chipcommon.h>
346 #include <linux/delay.h>
347 #include <linux/export.h>
348 +#ifdef CONFIG_BCM47XX
349 +#include <asm/mach-bcm47xx/nvram.h>
350 +#endif
351
352 #include "ssb_private.h"
353
354 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
355 u32 pmuctl, tmp, pllctl;
356 unsigned int i;
357
358 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
359 - /* The 5354 crystal freq is 25MHz */
360 - crystalfreq = 25000;
361 - }
362 if (crystalfreq)
363 e = pmu0_plltab_find_entry(crystalfreq);
364 if (!e)
365 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
366 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
367
368 if (bus->bustype == SSB_BUSTYPE_SSB) {
369 - /* TODO: The user may override the crystal frequency. */
370 +#ifdef CONFIG_BCM47XX
371 + char buf[20];
372 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
373 + crystalfreq = simple_strtoul(buf, NULL, 0);
374 +#endif
375 }
376
377 switch (bus->chip_id) {
378 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
379 ssb_pmu1_pllinit_r0(cc, crystalfreq);
380 break;
381 case 0x4328:
382 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
383 + break;
384 case 0x5354:
385 + if (crystalfreq == 0)
386 + crystalfreq = 25000;
387 ssb_pmu0_pllinit_r0(cc, crystalfreq);
388 break;
389 case 0x4322:
390 @@ -339,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
391 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
392 }
393 break;
394 + case 43222:
395 + break;
396 default:
397 ssb_printk(KERN_ERR PFX
398 "ERROR: PLL init unknown for device %04X\n",
399 @@ -427,6 +436,7 @@ static void ssb_pmu_resources_init(struc
400 min_msk = 0xCBB;
401 break;
402 case 0x4322:
403 + case 43222:
404 /* We keep the default settings:
405 * min_msk = 0xCBB
406 * max_msk = 0x7FFFF
407 @@ -607,3 +617,90 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
408
409 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
410 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
411 +
412 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
413 +{
414 + u32 crystalfreq;
415 + const struct pmu0_plltab_entry *e = NULL;
416 +
417 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
418 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
419 + e = pmu0_plltab_find_entry(crystalfreq);
420 + BUG_ON(!e);
421 + return e->freq * 1000;
422 +}
423 +
424 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
425 +{
426 + struct ssb_bus *bus = cc->dev->bus;
427 +
428 + switch (bus->chip_id) {
429 + case 0x5354:
430 + ssb_pmu_get_alp_clock_clk0(cc);
431 + default:
432 + ssb_printk(KERN_ERR PFX
433 + "ERROR: PMU alp clock unknown for device %04X\n",
434 + bus->chip_id);
435 + return 0;
436 + }
437 +}
438 +
439 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
440 +{
441 + struct ssb_bus *bus = cc->dev->bus;
442 +
443 + switch (bus->chip_id) {
444 + case 0x5354:
445 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
446 + return 240000000;
447 + default:
448 + ssb_printk(KERN_ERR PFX
449 + "ERROR: PMU cpu clock unknown for device %04X\n",
450 + bus->chip_id);
451 + return 0;
452 + }
453 +}
454 +
455 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
456 +{
457 + struct ssb_bus *bus = cc->dev->bus;
458 +
459 + switch (bus->chip_id) {
460 + case 0x5354:
461 + return 120000000;
462 + default:
463 + ssb_printk(KERN_ERR PFX
464 + "ERROR: PMU controlclock unknown for device %04X\n",
465 + bus->chip_id);
466 + return 0;
467 + }
468 +}
469 +
470 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
471 +{
472 + u32 pmu_ctl = 0;
473 +
474 + switch (cc->dev->bus->chip_id) {
475 + case 0x4322:
476 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
477 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
478 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
479 + if (spuravoid == 1)
480 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
481 + else
482 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
483 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
484 + break;
485 + case 43222:
486 + /* TODO: BCM43222 requires updating PLLs too */
487 + return;
488 + default:
489 + ssb_printk(KERN_ERR PFX
490 + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
491 + cc->dev->bus->chip_id);
492 + return;
493 + }
494 +
495 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
496 +}
497 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
498 --- /dev/null
499 +++ b/drivers/ssb/driver_chipcommon_sflash.c
500 @@ -0,0 +1,18 @@
501 +/*
502 + * Sonics Silicon Backplane
503 + * ChipCommon serial flash interface
504 + *
505 + * Licensed under the GNU/GPL. See COPYING for details.
506 + */
507 +
508 +#include <linux/ssb/ssb.h>
509 +
510 +#include "ssb_private.h"
511 +
512 +/* Initialize serial flash access */
513 +int ssb_sflash_init(struct ssb_chipcommon *cc)
514 +{
515 + pr_err("Serial flash support is not implemented yet!\n");
516 +
517 + return -ENOTSUPP;
518 +}
519 --- a/drivers/ssb/driver_extif.c
520 +++ b/drivers/ssb/driver_extif.c
521 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
522 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
523 }
524
525 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
526 - u32 ticks)
527 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
528 {
529 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
530 +
531 + return ssb_extif_watchdog_timer_set(extif, ticks);
532 +}
533 +
534 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
535 +{
536 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
537 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
538 +
539 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
540 +
541 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
542 +}
543 +
544 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
545 +{
546 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
547 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
548 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
549 +
550 + return ticks;
551 +}
552 +
553 +void ssb_extif_init(struct ssb_extif *extif)
554 +{
555 + if (!extif->dev)
556 + return; /* We don't have a Extif core */
557 + spin_lock_init(&extif->gpio_lock);
558 }
559
560 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
561 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
562
563 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
564 {
565 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
566 + unsigned long flags;
567 + u32 res = 0;
568 +
569 + spin_lock_irqsave(&extif->gpio_lock, flags);
570 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
571 mask, value);
572 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
573 +
574 + return res;
575 }
576
577 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
578 {
579 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
580 + unsigned long flags;
581 + u32 res = 0;
582 +
583 + spin_lock_irqsave(&extif->gpio_lock, flags);
584 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
585 mask, value);
586 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
587 +
588 + return res;
589 }
590
591 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
592 {
593 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
594 + unsigned long flags;
595 + u32 res = 0;
596 +
597 + spin_lock_irqsave(&extif->gpio_lock, flags);
598 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
599 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
600 +
601 + return res;
602 }
603
604 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
605 {
606 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
607 + unsigned long flags;
608 + u32 res = 0;
609 +
610 + spin_lock_irqsave(&extif->gpio_lock, flags);
611 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
612 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
613 +
614 + return res;
615 }
616 --- /dev/null
617 +++ b/drivers/ssb/driver_gpio.c
618 @@ -0,0 +1,176 @@
619 +/*
620 + * Sonics Silicon Backplane
621 + * GPIO driver
622 + *
623 + * Copyright 2011, Broadcom Corporation
624 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
625 + *
626 + * Licensed under the GNU/GPL. See COPYING for details.
627 + */
628 +
629 +#include <linux/gpio.h>
630 +#include <linux/export.h>
631 +#include <linux/ssb/ssb.h>
632 +
633 +#include "ssb_private.h"
634 +
635 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
636 +{
637 + return container_of(chip, struct ssb_bus, gpio);
638 +}
639 +
640 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
641 +{
642 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
643 +
644 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
645 +}
646 +
647 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
648 + int value)
649 +{
650 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
651 +
652 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
653 +}
654 +
655 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
656 + unsigned gpio)
657 +{
658 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
659 +
660 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
661 + return 0;
662 +}
663 +
664 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
665 + unsigned gpio, int value)
666 +{
667 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
668 +
669 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
670 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
671 + return 0;
672 +}
673 +
674 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
675 +{
676 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
677 +
678 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
679 + /* clear pulldown */
680 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
681 + /* Set pullup */
682 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
683 +
684 + return 0;
685 +}
686 +
687 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
688 +{
689 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
690 +
691 + /* clear pullup */
692 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
693 +}
694 +
695 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
696 +{
697 + struct gpio_chip *chip = &bus->gpio;
698 +
699 + chip->label = "ssb_chipco_gpio";
700 + chip->owner = THIS_MODULE;
701 + chip->request = ssb_gpio_chipco_request;
702 + chip->free = ssb_gpio_chipco_free;
703 + chip->get = ssb_gpio_chipco_get_value;
704 + chip->set = ssb_gpio_chipco_set_value;
705 + chip->direction_input = ssb_gpio_chipco_direction_input;
706 + chip->direction_output = ssb_gpio_chipco_direction_output;
707 + chip->ngpio = 16;
708 + /* There is just one SoC in one device and its GPIO addresses should be
709 + * deterministic to address them more easily. The other buses could get
710 + * a random base number. */
711 + if (bus->bustype == SSB_BUSTYPE_SSB)
712 + chip->base = 0;
713 + else
714 + chip->base = -1;
715 +
716 + return gpiochip_add(chip);
717 +}
718 +
719 +#ifdef CONFIG_SSB_DRIVER_EXTIF
720 +
721 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
722 +{
723 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
724 +
725 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
726 +}
727 +
728 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
729 + int value)
730 +{
731 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
732 +
733 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
734 +}
735 +
736 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
737 + unsigned gpio)
738 +{
739 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
740 +
741 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
742 + return 0;
743 +}
744 +
745 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
746 + unsigned gpio, int value)
747 +{
748 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
749 +
750 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
751 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
752 + return 0;
753 +}
754 +
755 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
756 +{
757 + struct gpio_chip *chip = &bus->gpio;
758 +
759 + chip->label = "ssb_extif_gpio";
760 + chip->owner = THIS_MODULE;
761 + chip->get = ssb_gpio_extif_get_value;
762 + chip->set = ssb_gpio_extif_set_value;
763 + chip->direction_input = ssb_gpio_extif_direction_input;
764 + chip->direction_output = ssb_gpio_extif_direction_output;
765 + chip->ngpio = 5;
766 + /* There is just one SoC in one device and its GPIO addresses should be
767 + * deterministic to address them more easily. The other buses could get
768 + * a random base number. */
769 + if (bus->bustype == SSB_BUSTYPE_SSB)
770 + chip->base = 0;
771 + else
772 + chip->base = -1;
773 +
774 + return gpiochip_add(chip);
775 +}
776 +
777 +#else
778 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
779 +{
780 + return -ENOTSUPP;
781 +}
782 +#endif
783 +
784 +int ssb_gpio_init(struct ssb_bus *bus)
785 +{
786 + if (ssb_chipco_available(&bus->chipco))
787 + return ssb_gpio_chipco_init(bus);
788 + else if (ssb_extif_available(&bus->extif))
789 + return ssb_gpio_extif_init(bus);
790 + else
791 + SSB_WARN_ON(1);
792 +
793 + return -1;
794 +}
795 --- a/drivers/ssb/driver_mipscore.c
796 +++ b/drivers/ssb/driver_mipscore.c
797 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
798 {
799 struct ssb_bus *bus = mcore->dev->bus;
800
801 - if (bus->extif.dev)
802 + if (ssb_extif_available(&bus->extif))
803 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
804 - else if (bus->chipco.dev)
805 + else if (ssb_chipco_available(&bus->chipco))
806 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
807 else
808 mcore->nr_serial_ports = 0;
809 @@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct
810 {
811 struct ssb_bus *bus = mcore->dev->bus;
812
813 - mcore->flash_buswidth = 2;
814 - if (bus->chipco.dev) {
815 - mcore->flash_window = 0x1c000000;
816 - mcore->flash_window_size = 0x02000000;
817 + /* When there is no chipcommon on the bus there is 4MB flash */
818 + if (!ssb_chipco_available(&bus->chipco)) {
819 + mcore->pflash.present = true;
820 + mcore->pflash.buswidth = 2;
821 + mcore->pflash.window = SSB_FLASH1;
822 + mcore->pflash.window_size = SSB_FLASH1_SZ;
823 + return;
824 + }
825 +
826 + /* There is ChipCommon, so use it to read info about flash */
827 + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
828 + case SSB_CHIPCO_FLASHT_STSER:
829 + case SSB_CHIPCO_FLASHT_ATSER:
830 + pr_debug("Found serial flash\n");
831 + ssb_sflash_init(&bus->chipco);
832 + break;
833 + case SSB_CHIPCO_FLASHT_PARA:
834 + pr_debug("Found parallel flash\n");
835 + mcore->pflash.present = true;
836 + mcore->pflash.window = SSB_FLASH2;
837 + mcore->pflash.window_size = SSB_FLASH2_SZ;
838 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
839 & SSB_CHIPCO_CFG_DS16) == 0)
840 - mcore->flash_buswidth = 1;
841 - } else {
842 - mcore->flash_window = 0x1fc00000;
843 - mcore->flash_window_size = 0x00400000;
844 + mcore->pflash.buswidth = 1;
845 + else
846 + mcore->pflash.buswidth = 2;
847 + break;
848 }
849 }
850
851 @@ -208,9 +225,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
852 struct ssb_bus *bus = mcore->dev->bus;
853 u32 pll_type, n, m, rate = 0;
854
855 - if (bus->extif.dev) {
856 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
857 + return ssb_pmu_get_cpu_clock(&bus->chipco);
858 +
859 + if (ssb_extif_available(&bus->extif)) {
860 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
861 - } else if (bus->chipco.dev) {
862 + } else if (ssb_chipco_available(&bus->chipco)) {
863 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
864 } else
865 return 0;
866 @@ -246,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
867 hz = 100000000;
868 ns = 1000000000 / hz;
869
870 - if (bus->extif.dev)
871 + if (ssb_extif_available(&bus->extif))
872 ssb_extif_timing_init(&bus->extif, ns);
873 - else if (bus->chipco.dev)
874 + else if (ssb_chipco_available(&bus->chipco))
875 ssb_chipco_timing_init(&bus->chipco, ns);
876
877 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
878 --- a/drivers/ssb/embedded.c
879 +++ b/drivers/ssb/embedded.c
880 @@ -4,11 +4,13 @@
881 *
882 * Copyright 2005-2008, Broadcom Corporation
883 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
884 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
885 *
886 * Licensed under the GNU/GPL. See COPYING for details.
887 */
888
889 #include <linux/export.h>
890 +#include <linux/platform_device.h>
891 #include <linux/ssb/ssb.h>
892 #include <linux/ssb/ssb_embedded.h>
893 #include <linux/ssb/ssb_driver_pci.h>
894 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
895 }
896 EXPORT_SYMBOL(ssb_watchdog_timer_set);
897
898 +int ssb_watchdog_register(struct ssb_bus *bus)
899 +{
900 + struct bcm47xx_wdt wdt = {};
901 + struct platform_device *pdev;
902 +
903 + if (ssb_chipco_available(&bus->chipco)) {
904 + wdt.driver_data = &bus->chipco;
905 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
906 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
907 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
908 + } else if (ssb_extif_available(&bus->extif)) {
909 + wdt.driver_data = &bus->extif;
910 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
911 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
912 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
913 + } else {
914 + return -ENODEV;
915 + }
916 +
917 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
918 + bus->busnumber, &wdt,
919 + sizeof(wdt));
920 + if (IS_ERR(pdev)) {
921 + ssb_dprintk(KERN_INFO PFX
922 + "can not register watchdog device, err: %li\n",
923 + PTR_ERR(pdev));
924 + return PTR_ERR(pdev);
925 + }
926 +
927 + bus->watchdog = pdev;
928 + return 0;
929 +}
930 +
931 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
932 {
933 unsigned long flags;
934 --- a/drivers/ssb/main.c
935 +++ b/drivers/ssb/main.c
936 @@ -13,6 +13,7 @@
937 #include <linux/delay.h>
938 #include <linux/io.h>
939 #include <linux/module.h>
940 +#include <linux/platform_device.h>
941 #include <linux/ssb/ssb.h>
942 #include <linux/ssb/ssb_regs.h>
943 #include <linux/ssb/ssb_driver_gige.h>
944 @@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
945 put_device(dev->dev);
946 }
947
948 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
949 -{
950 - if (drv)
951 - get_driver(&drv->drv);
952 - return drv;
953 -}
954 -
955 -static inline void ssb_driver_put(struct ssb_driver *drv)
956 -{
957 - if (drv)
958 - put_driver(&drv->drv);
959 -}
960 -
961 static int ssb_device_resume(struct device *dev)
962 {
963 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
964 @@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
965 ssb_device_put(sdev);
966 continue;
967 }
968 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
969 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
970 - ssb_device_put(sdev);
971 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
972 + if (SSB_WARN_ON(!sdrv->remove))
973 continue;
974 - }
975 sdrv->remove(sdev);
976 ctx->device_frozen[i] = 1;
977 }
978 @@ -293,7 +279,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
979 dev_name(sdev->dev));
980 result = err;
981 }
982 - ssb_driver_put(sdrv);
983 ssb_device_put(sdev);
984 }
985
986 @@ -449,6 +434,11 @@ static void ssb_devices_unregister(struc
987 if (sdev->dev)
988 device_unregister(sdev->dev);
989 }
990 +
991 +#ifdef CONFIG_SSB_EMBEDDED
992 + if (bus->bustype == SSB_BUSTYPE_SSB)
993 + platform_device_unregister(bus->watchdog);
994 +#endif
995 }
996
997 void ssb_bus_unregister(struct ssb_bus *bus)
998 @@ -577,6 +567,8 @@ static int __devinit ssb_attach_queued_b
999 if (err)
1000 goto error;
1001 ssb_pcicore_init(&bus->pcicore);
1002 + if (bus->bustype == SSB_BUSTYPE_SSB)
1003 + ssb_watchdog_register(bus);
1004 ssb_bus_may_powerdown(bus);
1005
1006 err = ssb_devices_register(bus);
1007 @@ -812,7 +804,14 @@ static int __devinit ssb_bus_register(st
1008 if (err)
1009 goto err_pcmcia_exit;
1010 ssb_chipcommon_init(&bus->chipco);
1011 + ssb_extif_init(&bus->extif);
1012 ssb_mipscore_init(&bus->mipscore);
1013 + err = ssb_gpio_init(bus);
1014 + if (err == -ENOTSUPP)
1015 + ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
1016 + else if (err)
1017 + ssb_dprintk(KERN_ERR PFX
1018 + "Error registering GPIO driver: %i\n", err);
1019 err = ssb_fetch_invariants(bus, get_invariants);
1020 if (err) {
1021 ssb_bus_may_powerdown(bus);
1022 @@ -1094,6 +1093,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1023 u32 plltype;
1024 u32 clkctl_n, clkctl_m;
1025
1026 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1027 + return ssb_pmu_get_controlclock(&bus->chipco);
1028 +
1029 if (ssb_extif_available(&bus->extif))
1030 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1031 &clkctl_n, &clkctl_m);
1032 @@ -1131,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1033 case SSB_IDLOW_SSBREV_27: /* same here */
1034 return SSB_TMSLOW_REJECT; /* this is a guess */
1035 default:
1036 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1037 - WARN_ON(1);
1038 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1039 }
1040 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1041 }
1042 --- a/drivers/ssb/pci.c
1043 +++ b/drivers/ssb/pci.c
1044 @@ -178,6 +178,18 @@ err_pci:
1045 #define SPEX(_outvar, _offset, _mask, _shift) \
1046 SPEX16(_outvar, _offset, _mask, _shift)
1047
1048 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
1049 + do { \
1050 + SPEX(_field[0], _offset + 0, _mask, _shift); \
1051 + SPEX(_field[1], _offset + 2, _mask, _shift); \
1052 + SPEX(_field[2], _offset + 4, _mask, _shift); \
1053 + SPEX(_field[3], _offset + 6, _mask, _shift); \
1054 + SPEX(_field[4], _offset + 8, _mask, _shift); \
1055 + SPEX(_field[5], _offset + 10, _mask, _shift); \
1056 + SPEX(_field[6], _offset + 12, _mask, _shift); \
1057 + SPEX(_field[7], _offset + 14, _mask, _shift); \
1058 + } while (0)
1059 +
1060
1061 static inline u8 ssb_crc8(u8 crc, u8 data)
1062 {
1063 @@ -327,11 +339,25 @@ static s8 r123_extract_antgain(u8 sprom_
1064 return (s8)gain;
1065 }
1066
1067 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1068 +{
1069 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1070 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1071 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1072 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1073 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1074 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1075 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1076 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1077 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1078 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1079 + SSB_SPROM2_MAXP_A_LO_SHIFT);
1080 +}
1081 +
1082 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1083 {
1084 int i;
1085 u16 v;
1086 - s8 gain;
1087 u16 loc[3];
1088
1089 if (out->revision == 3) /* rev 3 moved MAC */
1090 @@ -361,8 +387,9 @@ static void sprom_extract_r123(struct ss
1091 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1092 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1093 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1094 - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1095 - SSB_SPROM1_BINF_CCODE_SHIFT);
1096 + if (out->revision == 1)
1097 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1098 + SSB_SPROM1_BINF_CCODE_SHIFT);
1099 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
1100 SSB_SPROM1_BINF_ANTA_SHIFT);
1101 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
1102 @@ -386,24 +413,19 @@ static void sprom_extract_r123(struct ss
1103 SSB_SPROM1_ITSSI_A_SHIFT);
1104 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1105 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1106 - if (out->revision >= 2)
1107 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1108 +
1109 + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1110 + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1111
1112 /* Extract the antenna gain values. */
1113 - gain = r123_extract_antgain(out->revision, in,
1114 - SSB_SPROM1_AGAIN_BG,
1115 - SSB_SPROM1_AGAIN_BG_SHIFT);
1116 - out->antenna_gain.ghz24.a0 = gain;
1117 - out->antenna_gain.ghz24.a1 = gain;
1118 - out->antenna_gain.ghz24.a2 = gain;
1119 - out->antenna_gain.ghz24.a3 = gain;
1120 - gain = r123_extract_antgain(out->revision, in,
1121 - SSB_SPROM1_AGAIN_A,
1122 - SSB_SPROM1_AGAIN_A_SHIFT);
1123 - out->antenna_gain.ghz5.a0 = gain;
1124 - out->antenna_gain.ghz5.a1 = gain;
1125 - out->antenna_gain.ghz5.a2 = gain;
1126 - out->antenna_gain.ghz5.a3 = gain;
1127 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1128 + SSB_SPROM1_AGAIN_BG,
1129 + SSB_SPROM1_AGAIN_BG_SHIFT);
1130 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1131 + SSB_SPROM1_AGAIN_A,
1132 + SSB_SPROM1_AGAIN_A_SHIFT);
1133 + if (out->revision >= 2)
1134 + sprom_extract_r23(out, in);
1135 }
1136
1137 /* Revs 4 5 and 8 have partially shared layout */
1138 @@ -464,14 +486,17 @@ static void sprom_extract_r45(struct ssb
1139 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1140 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1141 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1142 + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1143 if (out->revision == 4) {
1144 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1145 + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1146 + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1147 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1148 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1149 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1150 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1151 } else {
1152 - SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1153 + SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
1154 + SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
1155 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1156 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1157 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1158 @@ -504,16 +529,14 @@ static void sprom_extract_r45(struct ssb
1159 }
1160
1161 /* Extract the antenna gain values. */
1162 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1163 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1164 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1165 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1166 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1167 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1168 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1169 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1170 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1171 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1172 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1173 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1174 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1175 - sizeof(out->antenna_gain.ghz5));
1176
1177 sprom_extract_r458(out, in);
1178
1179 @@ -523,14 +546,22 @@ static void sprom_extract_r45(struct ssb
1180 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1181 {
1182 int i;
1183 - u16 v;
1184 + u16 v, o;
1185 + u16 pwr_info_offset[] = {
1186 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1187 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1188 + };
1189 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1190 + ARRAY_SIZE(out->core_pwr_info));
1191
1192 /* extract the MAC address */
1193 for (i = 0; i < 3; i++) {
1194 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1195 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1196 }
1197 - SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1198 + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1199 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1200 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1201 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1202 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1203 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1204 @@ -596,16 +627,46 @@ static void sprom_extract_r8(struct ssb_
1205 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1206
1207 /* Extract the antenna gain values. */
1208 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1209 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1210 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1211 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1212 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1213 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1214 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1215 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1216 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1217 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1218 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1219 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1220 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1221 - sizeof(out->antenna_gain.ghz5));
1222 +
1223 + /* Extract cores power info info */
1224 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1225 + o = pwr_info_offset[i];
1226 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1227 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1228 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1229 + SSB_SPROM8_2G_MAXP, 0);
1230 +
1231 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1232 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1233 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1234 +
1235 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1236 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1237 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1238 + SSB_SPROM8_5G_MAXP, 0);
1239 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1240 + SSB_SPROM8_5GH_MAXP, 0);
1241 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1242 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1243 +
1244 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1245 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1246 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1247 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1248 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1249 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1250 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1251 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1252 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1253 + }
1254
1255 /* Extract FEM info */
1256 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1257 @@ -630,6 +691,63 @@ static void sprom_extract_r8(struct ssb_
1258 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1259 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1260
1261 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1262 + SSB_SPROM8_LEDDC_ON_SHIFT);
1263 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
1264 + SSB_SPROM8_LEDDC_OFF_SHIFT);
1265 +
1266 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
1267 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
1268 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
1269 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
1270 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
1271 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
1272 +
1273 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
1274 +
1275 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
1276 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
1277 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
1278 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
1279 +
1280 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
1281 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
1282 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
1283 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
1284 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
1285 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
1286 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
1287 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
1288 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
1289 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
1290 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
1291 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
1292 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
1293 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
1294 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
1295 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
1296 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
1297 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
1298 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
1299 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
1300 +
1301 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
1302 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
1303 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
1304 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
1305 +
1306 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
1307 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
1308 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
1309 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
1310 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
1311 + SSB_SPROM8_TEMPDELTA_PHYCAL,
1312 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
1313 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
1314 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
1315 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
1316 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
1317 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
1318 sprom_extract_r458(out, in);
1319
1320 /* TODO - get remaining rev 8 stuff needed */
1321 @@ -759,7 +877,6 @@ static void ssb_pci_get_boardinfo(struct
1322 {
1323 bi->vendor = bus->host_pci->subsystem_vendor;
1324 bi->type = bus->host_pci->subsystem_device;
1325 - bi->rev = bus->host_pci->revision;
1326 }
1327
1328 int ssb_pci_get_invariants(struct ssb_bus *bus,
1329 --- a/drivers/ssb/pcmcia.c
1330 +++ b/drivers/ssb/pcmcia.c
1331 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
1332 case SSB_PCMCIA_CIS_ANTGAIN:
1333 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1334 "antg tpl size");
1335 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
1336 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
1337 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
1338 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
1339 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
1340 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
1341 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
1342 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
1343 + sprom->antenna_gain.a0 = tuple->TupleData[1];
1344 + sprom->antenna_gain.a1 = tuple->TupleData[1];
1345 + sprom->antenna_gain.a2 = tuple->TupleData[1];
1346 + sprom->antenna_gain.a3 = tuple->TupleData[1];
1347 break;
1348 case SSB_PCMCIA_CIS_BFLAGS:
1349 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1350 --- a/drivers/ssb/scan.c
1351 +++ b/drivers/ssb/scan.c
1352 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
1353 return "ARM 1176";
1354 case SSB_DEV_ARM_7TDMI:
1355 return "ARM 7TDMI";
1356 + case SSB_DEV_ARM_CM3:
1357 + return "ARM Cortex M3";
1358 }
1359 return "UNKNOWN";
1360 }
1361 @@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
1362 bus->chip_package = 0;
1363 }
1364 }
1365 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1366 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1367 + bus->chip_package);
1368 if (!bus->nr_devices)
1369 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1370 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1371 --- a/drivers/ssb/sdio.c
1372 +++ b/drivers/ssb/sdio.c
1373 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
1374 case SSB_SDIO_CIS_ANTGAIN:
1375 GOTO_ERROR_ON(tuple->size != 2,
1376 "antg tpl size");
1377 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
1378 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
1379 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
1380 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
1381 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
1382 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
1383 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
1384 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
1385 + sprom->antenna_gain.a0 = tuple->data[1];
1386 + sprom->antenna_gain.a1 = tuple->data[1];
1387 + sprom->antenna_gain.a2 = tuple->data[1];
1388 + sprom->antenna_gain.a3 = tuple->data[1];
1389 break;
1390 case SSB_SDIO_CIS_BFLAGS:
1391 GOTO_ERROR_ON((tuple->size != 3) &&
1392 --- a/drivers/ssb/ssb_private.h
1393 +++ b/drivers/ssb/ssb_private.h
1394 @@ -3,6 +3,7 @@
1395
1396 #include <linux/ssb/ssb.h>
1397 #include <linux/types.h>
1398 +#include <linux/bcm47xx_wdt.h>
1399
1400
1401 #define PFX "ssb: "
1402 @@ -207,4 +208,66 @@ static inline void b43_pci_ssb_bridge_ex
1403 }
1404 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1405
1406 +/* driver_chipcommon_pmu.c */
1407 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
1408 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
1409 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
1410 +
1411 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
1412 + u32 ticks);
1413 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
1414 +
1415 +/* driver_chipcommon_sflash.c */
1416 +#ifdef CONFIG_SSB_SFLASH
1417 +int ssb_sflash_init(struct ssb_chipcommon *cc);
1418 +#else
1419 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
1420 +{
1421 + pr_err("Serial flash not supported\n");
1422 + return 0;
1423 +}
1424 +#endif /* CONFIG_SSB_SFLASH */
1425 +
1426 +#ifdef CONFIG_SSB_DRIVER_EXTIF
1427 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
1428 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
1429 +#else
1430 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
1431 + u32 ticks)
1432 +{
1433 + return 0;
1434 +}
1435 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
1436 + u32 ms)
1437 +{
1438 + return 0;
1439 +}
1440 +#endif
1441 +
1442 +#ifdef CONFIG_SSB_EMBEDDED
1443 +extern int ssb_watchdog_register(struct ssb_bus *bus);
1444 +#else /* CONFIG_SSB_EMBEDDED */
1445 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
1446 +{
1447 + return 0;
1448 +}
1449 +#endif /* CONFIG_SSB_EMBEDDED */
1450 +
1451 +#ifdef CONFIG_SSB_DRIVER_EXTIF
1452 +extern void ssb_extif_init(struct ssb_extif *extif);
1453 +#else
1454 +static inline void ssb_extif_init(struct ssb_extif *extif)
1455 +{
1456 +}
1457 +#endif
1458 +
1459 +#ifdef CONFIG_SSB_DRIVER_GPIO
1460 +extern int ssb_gpio_init(struct ssb_bus *bus);
1461 +#else /* CONFIG_SSB_DRIVER_GPIO */
1462 +static inline int ssb_gpio_init(struct ssb_bus *bus)
1463 +{
1464 + return -ENOTSUPP;
1465 +}
1466 +#endif /* CONFIG_SSB_DRIVER_GPIO */
1467 +
1468 #endif /* LINUX_SSB_PRIVATE_H_ */
1469 --- a/include/linux/ssb/ssb.h
1470 +++ b/include/linux/ssb/ssb.h
1471 @@ -6,8 +6,10 @@
1472 #include <linux/types.h>
1473 #include <linux/spinlock.h>
1474 #include <linux/pci.h>
1475 +#include <linux/gpio.h>
1476 #include <linux/mod_devicetable.h>
1477 #include <linux/dma-mapping.h>
1478 +#include <linux/platform_device.h>
1479
1480 #include <linux/ssb/ssb_regs.h>
1481
1482 @@ -16,6 +18,12 @@ struct pcmcia_device;
1483 struct ssb_bus;
1484 struct ssb_driver;
1485
1486 +struct ssb_sprom_core_pwr_info {
1487 + u8 itssi_2g, itssi_5g;
1488 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
1489 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
1490 +};
1491 +
1492 struct ssb_sprom {
1493 u8 revision;
1494 u8 il0mac[6]; /* MAC address for 802.11b/g */
1495 @@ -26,9 +34,12 @@ struct ssb_sprom {
1496 u8 et0mdcport; /* MDIO for enet0 */
1497 u8 et1mdcport; /* MDIO for enet1 */
1498 u16 board_rev; /* Board revision number from SPROM. */
1499 + u16 board_num; /* Board number from SPROM. */
1500 + u16 board_type; /* Board type from SPROM. */
1501 u8 country_code; /* Country Code */
1502 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1503 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1504 + char alpha2[2]; /* Country Code as two chars like EU or US */
1505 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1506 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1507 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1508 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1509 u16 pa0b0;
1510 @@ -47,10 +58,10 @@ struct ssb_sprom {
1511 u8 gpio1; /* GPIO pin 1 */
1512 u8 gpio2; /* GPIO pin 2 */
1513 u8 gpio3; /* GPIO pin 3 */
1514 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1515 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1516 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1517 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1518 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1519 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1520 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1521 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1522 u8 itssi_a; /* Idle TSSI Target for A-PHY */
1523 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
1524 u8 tri2g; /* 2.4GHz TX isolation */
1525 @@ -61,8 +72,8 @@ struct ssb_sprom {
1526 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
1527 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
1528 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
1529 - u8 rxpo2g; /* 2GHz RX power offset */
1530 - u8 rxpo5g; /* 5GHz RX power offset */
1531 + s8 rxpo2g; /* 2GHz RX power offset */
1532 + s8 rxpo5g; /* 5GHz RX power offset */
1533 u8 rssisav2g; /* 2GHz RSSI params */
1534 u8 rssismc2g;
1535 u8 rssismf2g;
1536 @@ -82,16 +93,13 @@ struct ssb_sprom {
1537 u16 boardflags2_hi; /* Board flags (bits 48-63) */
1538 /* TODO store board flags in a single u64 */
1539
1540 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
1541 +
1542 /* Antenna gain values for up to 4 antennas
1543 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
1544 * loss in the connectors is bigger than the gain. */
1545 struct {
1546 - struct {
1547 - s8 a0, a1, a2, a3;
1548 - } ghz24; /* 2.4GHz band */
1549 - struct {
1550 - s8 a0, a1, a2, a3;
1551 - } ghz5; /* 5GHz band */
1552 + s8 a0, a1, a2, a3;
1553 } antenna_gain;
1554
1555 struct {
1556 @@ -103,14 +111,85 @@ struct ssb_sprom {
1557 } ghz5;
1558 } fem;
1559
1560 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1561 + u16 mcs2gpo[8];
1562 + u16 mcs5gpo[8];
1563 + u16 mcs5glpo[8];
1564 + u16 mcs5ghpo[8];
1565 + u8 opo;
1566 +
1567 + u8 rxgainerr2ga[3];
1568 + u8 rxgainerr5gla[3];
1569 + u8 rxgainerr5gma[3];
1570 + u8 rxgainerr5gha[3];
1571 + u8 rxgainerr5gua[3];
1572 +
1573 + u8 noiselvl2ga[3];
1574 + u8 noiselvl5gla[3];
1575 + u8 noiselvl5gma[3];
1576 + u8 noiselvl5gha[3];
1577 + u8 noiselvl5gua[3];
1578 +
1579 + u8 regrev;
1580 + u8 txchain;
1581 + u8 rxchain;
1582 + u8 antswitch;
1583 + u16 cddpo;
1584 + u16 stbcpo;
1585 + u16 bw40po;
1586 + u16 bwduppo;
1587 +
1588 + u8 tempthresh;
1589 + u8 tempoffset;
1590 + u16 rawtempsense;
1591 + u8 measpower;
1592 + u8 tempsense_slope;
1593 + u8 tempcorrx;
1594 + u8 tempsense_option;
1595 + u8 freqoffset_corr;
1596 + u8 iqcal_swp_dis;
1597 + u8 hw_iqcal_en;
1598 + u8 elna2g;
1599 + u8 elna5g;
1600 + u8 phycal_tempdelta;
1601 + u8 temps_period;
1602 + u8 temps_hysteresis;
1603 + u8 measpower1;
1604 + u8 measpower2;
1605 + u8 pcieingress_war;
1606 +
1607 + /* power per rate from sromrev 9 */
1608 + u16 cckbw202gpo;
1609 + u16 cckbw20ul2gpo;
1610 + u32 legofdmbw202gpo;
1611 + u32 legofdmbw20ul2gpo;
1612 + u32 legofdmbw205glpo;
1613 + u32 legofdmbw20ul5glpo;
1614 + u32 legofdmbw205gmpo;
1615 + u32 legofdmbw20ul5gmpo;
1616 + u32 legofdmbw205ghpo;
1617 + u32 legofdmbw20ul5ghpo;
1618 + u32 mcsbw202gpo;
1619 + u32 mcsbw20ul2gpo;
1620 + u32 mcsbw402gpo;
1621 + u32 mcsbw205glpo;
1622 + u32 mcsbw20ul5glpo;
1623 + u32 mcsbw405glpo;
1624 + u32 mcsbw205gmpo;
1625 + u32 mcsbw20ul5gmpo;
1626 + u32 mcsbw405gmpo;
1627 + u32 mcsbw205ghpo;
1628 + u32 mcsbw20ul5ghpo;
1629 + u32 mcsbw405ghpo;
1630 + u16 mcs32po;
1631 + u16 legofdm40duppo;
1632 + u8 sar2g;
1633 + u8 sar5g;
1634 };
1635
1636 /* Information about the PCB the circuitry is soldered on. */
1637 struct ssb_boardinfo {
1638 u16 vendor;
1639 u16 type;
1640 - u8 rev;
1641 };
1642
1643
1644 @@ -166,6 +245,7 @@ struct ssb_bus_ops {
1645 #define SSB_DEV_MINI_MACPHY 0x823
1646 #define SSB_DEV_ARM_1176 0x824
1647 #define SSB_DEV_ARM_7TDMI 0x825
1648 +#define SSB_DEV_ARM_CM3 0x82A
1649
1650 /* Vendor-ID values */
1651 #define SSB_VENDOR_BROADCOM 0x4243
1652 @@ -354,7 +434,11 @@ struct ssb_bus {
1653 #ifdef CONFIG_SSB_EMBEDDED
1654 /* Lock for GPIO register access. */
1655 spinlock_t gpio_lock;
1656 + struct platform_device *watchdog;
1657 #endif /* EMBEDDED */
1658 +#ifdef CONFIG_SSB_DRIVER_GPIO
1659 + struct gpio_chip gpio;
1660 +#endif /* DRIVER_GPIO */
1661
1662 /* Internal-only stuff follows. Do not touch. */
1663 struct list_head list;
1664 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1665 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1666 @@ -219,6 +219,7 @@
1667 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
1668 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1669 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
1670 +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
1671 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1672 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1673 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
1674 @@ -504,7 +505,9 @@
1675 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
1676 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
1677 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
1678 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
1679 +#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
1680 +#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
1681 +#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
1682
1683 /* Status register bits for ST flashes */
1684 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
1685 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
1686 u32 status;
1687 /* Fast Powerup Delay constant */
1688 u16 fast_pwrup_delay;
1689 + spinlock_t gpio_lock;
1690 struct ssb_chipcommon_pmu pmu;
1691 + u32 ticks_per_ms;
1692 + u32 max_timer_ms;
1693 };
1694
1695 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
1696 @@ -628,8 +634,7 @@ enum ssb_clkmode {
1697 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
1698 enum ssb_clkmode mode);
1699
1700 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
1701 - u32 ticks);
1702 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
1703
1704 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1705
1706 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
1707 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
1708 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1709 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
1710 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
1711 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
1712
1713 #ifdef CONFIG_SSB_SERIAL
1714 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
1715 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
1716 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
1717 enum ssb_pmu_ldo_volt_id id, u32 voltage);
1718 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
1719 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
1720
1721 #endif /* LINUX_SSB_CHIPCO_H_ */
1722 --- a/include/linux/ssb/ssb_driver_extif.h
1723 +++ b/include/linux/ssb/ssb_driver_extif.h
1724 @@ -152,12 +152,16 @@
1725 /* watchdog */
1726 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
1727
1728 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
1729 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
1730 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
1731
1732
1733 #ifdef CONFIG_SSB_DRIVER_EXTIF
1734
1735 struct ssb_extif {
1736 struct ssb_device *dev;
1737 + spinlock_t gpio_lock;
1738 };
1739
1740 static inline bool ssb_extif_available(struct ssb_extif *extif)
1741 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
1742 extern void ssb_extif_timing_init(struct ssb_extif *extif,
1743 unsigned long ns);
1744
1745 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1746 - u32 ticks);
1747 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
1748
1749 /* Extif GPIO pin access */
1750 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
1751 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
1752 }
1753
1754 static inline
1755 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1756 - u32 ticks)
1757 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
1758 {
1759 }
1760
1761 +static inline
1762 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
1763 +{
1764 + return 0;
1765 +}
1766 +
1767 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
1768 +{
1769 + return 0;
1770 +}
1771 +
1772 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
1773 + u32 value)
1774 +{
1775 + return 0;
1776 +}
1777 +
1778 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
1779 + u32 value)
1780 +{
1781 + return 0;
1782 +}
1783 +
1784 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
1785 + u32 value)
1786 +{
1787 + return 0;
1788 +}
1789 +
1790 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
1791 + u32 value)
1792 +{
1793 + return 0;
1794 +}
1795 +
1796 +#ifdef CONFIG_SSB_SERIAL
1797 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
1798 + struct ssb_serial_port *ports)
1799 +{
1800 + return 0;
1801 +}
1802 +#endif /* CONFIG_SSB_SERIAL */
1803 +
1804 #endif /* CONFIG_SSB_DRIVER_EXTIF */
1805 #endif /* LINUX_SSB_EXTIFCORE_H_ */
1806 --- a/include/linux/ssb/ssb_driver_gige.h
1807 +++ b/include/linux/ssb/ssb_driver_gige.h
1808 @@ -2,6 +2,7 @@
1809 #define LINUX_SSB_DRIVER_GIGE_H_
1810
1811 #include <linux/ssb/ssb.h>
1812 +#include <linux/bug.h>
1813 #include <linux/pci.h>
1814 #include <linux/spinlock.h>
1815
1816 --- a/include/linux/ssb/ssb_driver_mips.h
1817 +++ b/include/linux/ssb/ssb_driver_mips.h
1818 @@ -13,6 +13,12 @@ struct ssb_serial_port {
1819 unsigned int reg_shift;
1820 };
1821
1822 +struct ssb_pflash {
1823 + bool present;
1824 + u8 buswidth;
1825 + u32 window;
1826 + u32 window_size;
1827 +};
1828
1829 struct ssb_mipscore {
1830 struct ssb_device *dev;
1831 @@ -20,9 +26,7 @@ struct ssb_mipscore {
1832 int nr_serial_ports;
1833 struct ssb_serial_port serial_ports[4];
1834
1835 - u8 flash_buswidth;
1836 - u32 flash_window;
1837 - u32 flash_window_size;
1838 + struct ssb_pflash pflash;
1839 };
1840
1841 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1842 --- a/include/linux/ssb/ssb_regs.h
1843 +++ b/include/linux/ssb/ssb_regs.h
1844 @@ -228,6 +228,7 @@
1845 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
1846 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
1847 #define SSB_SPROM1_AGAIN_A_SHIFT 8
1848 +#define SSB_SPROM1_CCODE 0x0076
1849
1850 /* SPROM Revision 2 (inherits from rev 1) */
1851 #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
1852 @@ -267,6 +268,7 @@
1853 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
1854
1855 /* SPROM Revision 4 */
1856 +#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
1857 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
1858 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
1859 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
1860 @@ -287,11 +289,11 @@
1861 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1862 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1863 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1864 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1865 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1866 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1867 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1868 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1869 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
1870 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1871 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
1872 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1873 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
1874 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1875 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1876 #define SSB_SPROM4_AGAIN0_SHIFT 0
1877 @@ -389,6 +391,11 @@
1878 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1879 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1880 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
1881 +#define SSB_SPROM8_LEDDC 0x009A
1882 +#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
1883 +#define SSB_SPROM8_LEDDC_ON_SHIFT 8
1884 +#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
1885 +#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
1886 #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1887 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1888 #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1889 @@ -404,6 +411,13 @@
1890 #define SSB_SPROM8_AGAIN2_SHIFT 0
1891 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1892 #define SSB_SPROM8_AGAIN3_SHIFT 8
1893 +#define SSB_SPROM8_TXRXC 0x00A2
1894 +#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
1895 +#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
1896 +#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
1897 +#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
1898 +#define SSB_SPROM8_TXRXC_SWITCH 0xff00
1899 +#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
1900 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1901 #define SSB_SPROM8_RSSISMF2G 0x000F
1902 #define SSB_SPROM8_RSSISMC2G 0x00F0
1903 @@ -430,6 +444,7 @@
1904 #define SSB_SPROM8_TRI5GH_SHIFT 8
1905 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1906 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1907 +#define SSB_SPROM8_RXPO2G_SHIFT 0
1908 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1909 #define SSB_SPROM8_RXPO5G_SHIFT 8
1910 #define SSB_SPROM8_FEM2G 0x00AE
1911 @@ -445,10 +460,71 @@
1912 #define SSB_SROM8_FEM_ANTSWLUT 0xF800
1913 #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
1914 #define SSB_SPROM8_THERMAL 0x00B2
1915 -#define SSB_SPROM8_MPWR_RAWTS 0x00B4
1916 -#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
1917 -#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
1918 -#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
1919 +#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
1920 +#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
1921 +#define SSB_SPROM8_THERMAL_TRESH 0xff00
1922 +#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
1923 +/* Temp sense related entries */
1924 +#define SSB_SPROM8_RAWTS 0x00B4
1925 +#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
1926 +#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
1927 +#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
1928 +#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
1929 +#define SSB_SPROM8_OPT_CORRX 0x00B6
1930 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
1931 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
1932 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
1933 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
1934 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
1935 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
1936 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
1937 +#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
1938 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
1939 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
1940 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
1941 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
1942 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
1943 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
1944 +#define SSB_SPROM8_TEMPDELTA 0x00BC
1945 +#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
1946 +#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
1947 +#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
1948 +#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
1949 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
1950 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
1951 +
1952 +/* There are 4 blocks with power info sharing the same layout */
1953 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
1954 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
1955 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
1956 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
1957 +
1958 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
1959 +#define SSB_SPROM8_2G_MAXP 0x00FF
1960 +#define SSB_SPROM8_2G_ITSSI 0xFF00
1961 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
1962 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
1963 +#define SSB_SROM8_2G_PA_1 0x04
1964 +#define SSB_SROM8_2G_PA_2 0x06
1965 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
1966 +#define SSB_SPROM8_5G_MAXP 0x00FF
1967 +#define SSB_SPROM8_5G_ITSSI 0xFF00
1968 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
1969 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
1970 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1971 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1972 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1973 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1974 +#define SSB_SROM8_5G_PA_1 0x0E
1975 +#define SSB_SROM8_5G_PA_2 0x10
1976 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1977 +#define SSB_SROM8_5GL_PA_1 0x14
1978 +#define SSB_SROM8_5GL_PA_2 0x16
1979 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1980 +#define SSB_SROM8_5GH_PA_1 0x1A
1981 +#define SSB_SROM8_5GH_PA_2 0x1C
1982 +
1983 +/* TODO: Make it deprecated */
1984 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1985 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1986 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1987 @@ -473,12 +549,23 @@
1988 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1989 #define SSB_SPROM8_PA1HIB1 0x00DA
1990 #define SSB_SPROM8_PA1HIB2 0x00DC
1991 +
1992 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1993 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1994 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1995 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1996 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1997
1998 +#define SSB_SPROM8_2G_MCSPO 0x0152
1999 +#define SSB_SPROM8_5G_MCSPO 0x0162
2000 +#define SSB_SPROM8_5GL_MCSPO 0x0172
2001 +#define SSB_SPROM8_5GH_MCSPO 0x0182
2002 +
2003 +#define SSB_SPROM8_CDDPO 0x0192
2004 +#define SSB_SPROM8_STBCPO 0x0194
2005 +#define SSB_SPROM8_BW40PO 0x0196
2006 +#define SSB_SPROM8_BWDUPPO 0x0198
2007 +
2008 /* Values for boardflags_lo read from SPROM */
2009 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
2010 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
2011 --- /dev/null
2012 +++ b/include/linux/bcm47xx_wdt.h
2013 @@ -0,0 +1,19 @@
2014 +#ifndef LINUX_BCM47XX_WDT_H_
2015 +#define LINUX_BCM47XX_WDT_H_
2016 +
2017 +#include <linux/types.h>
2018 +
2019 +
2020 +struct bcm47xx_wdt {
2021 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
2022 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
2023 + u32 max_timer_ms;
2024 +
2025 + void *driver_data;
2026 +};
2027 +
2028 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
2029 +{
2030 + return wdt->driver_data;
2031 +}
2032 +#endif /* LINUX_BCM47XX_WDT_H_ */
2033 --- a/drivers/net/wireless/b43/phy_n.c
2034 +++ b/drivers/net/wireless/b43/phy_n.c
2035 @@ -4259,7 +4259,8 @@ static void b43_nphy_pmu_spur_avoid(stru
2036 #endif
2037 #ifdef CONFIG_B43_SSB
2038 case B43_BUS_SSB:
2039 - /* FIXME */
2040 + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
2041 + avoid);
2042 break;
2043 #endif
2044 }
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