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kernel: update linux 3.7 to 3.7.2
[openwrt/openwrt.git] / target / linux / generic / patches-3.7 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
4
5 If unsure, say N
6
7 +config BCMA_DRIVER_GPIO
8 + bool "BCMA GPIO driver"
9 + depends on BCMA && GPIOLIB
10 + help
11 + Driver to provide access to the GPIO pins of the bcma bus.
12 +
13 + If unsure, say N
14 +
15 config BCMA_DEBUG
16 bool "BCMA debugging"
17 depends on BCMA
18 --- a/drivers/bcma/Makefile
19 +++ b/drivers/bcma/Makefile
20 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
21 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
22 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
23 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
24 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
25 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
26 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
27 obj-$(CONFIG_BCMA) += bcma.o
28 --- a/drivers/bcma/bcma_private.h
29 +++ b/drivers/bcma/bcma_private.h
30 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
31 int bcma_bus_suspend(struct bcma_bus *bus);
32 int bcma_bus_resume(struct bcma_bus *bus);
33 #endif
34 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
35 + u8 unit);
36
37 /* scan.c */
38 int bcma_bus_scan(struct bcma_bus *bus);
39 @@ -48,8 +50,8 @@ void bcma_chipco_serial_init(struct bcma
40 #endif /* CONFIG_BCMA_DRIVER_MIPS */
41
42 /* driver_chipcommon_pmu.c */
43 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
44 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
45 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
46 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
47
48 #ifdef CONFIG_BCMA_SFLASH
49 /* driver_chipcommon_sflash.c */
50 @@ -84,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
51 /* driver_pci.c */
52 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
53
54 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
55 +
56 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
57 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
58 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
59 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
60
61 +#ifdef CONFIG_BCMA_DRIVER_GPIO
62 +/* driver_gpio.c */
63 +int bcma_gpio_init(struct bcma_drv_cc *cc);
64 +#else
65 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
66 +{
67 + return -ENOTSUPP;
68 +}
69 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
70 +
71 #endif
72 --- a/drivers/bcma/driver_chipcommon.c
73 +++ b/drivers/bcma/driver_chipcommon.c
74 @@ -4,12 +4,15 @@
75 *
76 * Copyright 2005, Broadcom Corporation
77 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
78 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
79 *
80 * Licensed under the GNU/GPL. See COPYING for details.
81 */
82
83 #include "bcma_private.h"
84 +#include <linux/bcm47xx_wdt.h>
85 #include <linux/export.h>
86 +#include <linux/platform_device.h>
87 #include <linux/bcma/bcma.h>
88
89 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
90 @@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked
91 return value;
92 }
93
94 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
95 +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
96 {
97 - u32 leddc_on = 10;
98 - u32 leddc_off = 90;
99 + if (cc->capabilities & BCMA_CC_CAP_PMU)
100 + return bcma_pmu_get_alp_clock(cc);
101
102 - if (cc->setup_done)
103 + return 20000000;
104 +}
105 +
106 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
107 +{
108 + struct bcma_bus *bus = cc->core->bus;
109 + u32 nb;
110 +
111 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
112 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
113 + nb = 32;
114 + else if (cc->core->id.rev < 26)
115 + nb = 16;
116 + else
117 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
118 + } else {
119 + nb = 28;
120 + }
121 + if (nb == 32)
122 + return 0xffffffff;
123 + else
124 + return (1 << nb) - 1;
125 +}
126 +
127 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
128 + u32 ticks)
129 +{
130 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
131 +
132 + return bcma_chipco_watchdog_timer_set(cc, ticks);
133 +}
134 +
135 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
136 + u32 ms)
137 +{
138 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
139 + u32 ticks;
140 +
141 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
142 + return ticks / cc->ticks_per_ms;
143 +}
144 +
145 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
146 +{
147 + struct bcma_bus *bus = cc->core->bus;
148 +
149 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
150 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
151 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
152 + return bcma_chipco_get_alp_clock(cc) / 4000;
153 + else
154 + /* based on 32KHz ILP clock */
155 + return 32;
156 + } else {
157 + return bcma_chipco_get_alp_clock(cc) / 1000;
158 + }
159 +}
160 +
161 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
162 +{
163 + struct bcm47xx_wdt wdt = {};
164 + struct platform_device *pdev;
165 +
166 + wdt.driver_data = cc;
167 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
168 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
169 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
170 +
171 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
172 + cc->core->bus->num, &wdt,
173 + sizeof(wdt));
174 + if (IS_ERR(pdev))
175 + return PTR_ERR(pdev);
176 +
177 + cc->watchdog = pdev;
178 +
179 + return 0;
180 +}
181 +
182 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
183 +{
184 + if (cc->early_setup_done)
185 return;
186
187 + spin_lock_init(&cc->gpio_lock);
188 +
189 if (cc->core->id.rev >= 11)
190 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
191 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
192 if (cc->core->id.rev >= 35)
193 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
194
195 + if (cc->capabilities & BCMA_CC_CAP_PMU)
196 + bcma_pmu_early_init(cc);
197 +
198 + cc->early_setup_done = true;
199 +}
200 +
201 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
202 +{
203 + u32 leddc_on = 10;
204 + u32 leddc_off = 90;
205 +
206 + if (cc->setup_done)
207 + return;
208 +
209 + bcma_core_chipcommon_early_init(cc);
210 +
211 if (cc->core->id.rev >= 20) {
212 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
213 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
214 @@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc
215 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
216 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
217 }
218 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
219
220 cc->setup_done = true;
221 }
222
223 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
224 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
225 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
226 {
227 - /* instant NMI */
228 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
229 + u32 maxt;
230 + enum bcma_clkmode clkmode;
231 +
232 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
233 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
234 + if (ticks == 1)
235 + ticks = 2;
236 + else if (ticks > maxt)
237 + ticks = maxt;
238 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
239 + } else {
240 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
241 + bcma_core_set_clockmode(cc->core, clkmode);
242 + if (ticks > maxt)
243 + ticks = maxt;
244 + /* instant NMI */
245 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
246 + }
247 + return ticks;
248 }
249
250 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
251 @@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
252
253 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
254 {
255 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
256 + unsigned long flags;
257 + u32 res;
258 +
259 + spin_lock_irqsave(&cc->gpio_lock, flags);
260 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
261 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
262 +
263 + return res;
264 }
265
266 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
267 {
268 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
269 + unsigned long flags;
270 + u32 res;
271 +
272 + spin_lock_irqsave(&cc->gpio_lock, flags);
273 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
274 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
275 +
276 + return res;
277 }
278
279 +/*
280 + * If the bit is set to 0, chipcommon controlls this GPIO,
281 + * if the bit is set to 1, it is used by some part of the chip and not our code.
282 + */
283 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
284 {
285 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
286 + unsigned long flags;
287 + u32 res;
288 +
289 + spin_lock_irqsave(&cc->gpio_lock, flags);
290 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
291 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
292 +
293 + return res;
294 }
295 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
296
297 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
298 {
299 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
300 + unsigned long flags;
301 + u32 res;
302 +
303 + spin_lock_irqsave(&cc->gpio_lock, flags);
304 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
305 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
306 +
307 + return res;
308 }
309
310 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
311 {
312 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
313 + unsigned long flags;
314 + u32 res;
315 +
316 + spin_lock_irqsave(&cc->gpio_lock, flags);
317 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
318 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
319 +
320 + return res;
321 +}
322 +
323 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
324 +{
325 + unsigned long flags;
326 + u32 res;
327 +
328 + if (cc->core->id.rev < 20)
329 + return 0;
330 +
331 + spin_lock_irqsave(&cc->gpio_lock, flags);
332 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
333 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
334 +
335 + return res;
336 +}
337 +
338 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
339 +{
340 + unsigned long flags;
341 + u32 res;
342 +
343 + if (cc->core->id.rev < 20)
344 + return 0;
345 +
346 + spin_lock_irqsave(&cc->gpio_lock, flags);
347 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
348 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
349 +
350 + return res;
351 }
352
353 #ifdef CONFIG_BCMA_DRIVER_MIPS
354 @@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma
355 struct bcma_serial_port *ports = cc->serial_ports;
356
357 if (ccrev >= 11 && ccrev != 15) {
358 - /* Fixed ALP clock */
359 - baud_base = bcma_pmu_alp_clock(cc);
360 + baud_base = bcma_chipco_get_alp_clock(cc);
361 if (ccrev >= 21) {
362 /* Turn off UART clock before switching clocksource. */
363 bcma_cc_write32(cc, BCMA_CC_CORECTL,
364 --- a/drivers/bcma/driver_chipcommon_nflash.c
365 +++ b/drivers/bcma/driver_chipcommon_nflash.c
366 @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
367 }
368
369 cc->nflash.present = true;
370 + if (cc->core->id.rev == 38 &&
371 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
372 + cc->nflash.boot = true;
373
374 /* Prepare platform device, but don't register it yet. It's too early,
375 * malloc (required by device_private_init) is not available yet. */
376 --- a/drivers/bcma/driver_chipcommon_pmu.c
377 +++ b/drivers/bcma/driver_chipcommon_pmu.c
378 @@ -13,12 +13,13 @@
379 #include <linux/export.h>
380 #include <linux/bcma/bcma.h>
381
382 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
383 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
384 {
385 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
386 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
387 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
388 }
389 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
390
391 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
392 {
393 @@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct
394 }
395 }
396
397 -void bcma_pmu_init(struct bcma_drv_cc *cc)
398 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
399 {
400 u32 pmucap;
401
402 @@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
403
404 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
405 cc->pmu.rev, pmucap);
406 +}
407
408 +void bcma_pmu_init(struct bcma_drv_cc *cc)
409 +{
410 if (cc->pmu.rev == 1)
411 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
412 ~BCMA_CC_PMU_CTL_NOILPONW);
413 @@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
414 bcma_pmu_workarounds(cc);
415 }
416
417 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
418 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
419 {
420 struct bcma_bus *bus = cc->core->bus;
421
422 @@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
423 /* Find the output of the "m" pll divider given pll controls that start with
424 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
425 */
426 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
427 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
428 {
429 u32 tmp, div, ndiv, p1, p2, fc;
430 struct bcma_bus *bus = cc->core->bus;
431 @@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
432 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
433
434 /* Do calculation in Mhz */
435 - fc = bcma_pmu_alp_clock(cc) / 1000000;
436 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
437 fc = (p1 * ndiv * fc) / p2;
438
439 /* Return clock in Hertz */
440 return (fc / div) * 1000000;
441 }
442
443 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
444 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
445 {
446 u32 tmp, ndiv, p1div, p2div;
447 u32 clock;
448 @@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
449 }
450
451 /* query bus clock frequency for PMU-enabled chipcommon */
452 -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
453 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
454 {
455 struct bcma_bus *bus = cc->core->bus;
456
457 @@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(str
458 case BCMA_CHIP_ID_BCM4716:
459 case BCMA_CHIP_ID_BCM4748:
460 case BCMA_CHIP_ID_BCM47162:
461 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
462 - BCMA_CC_PMU5_MAINPLL_SSB);
463 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
464 + BCMA_CC_PMU5_MAINPLL_SSB);
465 case BCMA_CHIP_ID_BCM5356:
466 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
467 - BCMA_CC_PMU5_MAINPLL_SSB);
468 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
469 + BCMA_CC_PMU5_MAINPLL_SSB);
470 case BCMA_CHIP_ID_BCM5357:
471 case BCMA_CHIP_ID_BCM4749:
472 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
473 - BCMA_CC_PMU5_MAINPLL_SSB);
474 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
475 + BCMA_CC_PMU5_MAINPLL_SSB);
476 case BCMA_CHIP_ID_BCM4706:
477 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
478 - BCMA_CC_PMU5_MAINPLL_SSB);
479 + return bcma_pmu_pll_clock_bcm4706(cc,
480 + BCMA_CC_PMU4706_MAINPLL_PLL0,
481 + BCMA_CC_PMU5_MAINPLL_SSB);
482 case BCMA_CHIP_ID_BCM53572:
483 return 75000000;
484 default:
485 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
486 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
487 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
488 }
489 return BCMA_CC_PMU_HT_CLOCK;
490 }
491
492 /* query cpu clock frequency for PMU-enabled chipcommon */
493 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
494 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
495 {
496 struct bcma_bus *bus = cc->core->bus;
497
498 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
499 return 300000000;
500
501 + /* New PMUs can have different clock for bus and CPU */
502 if (cc->pmu.rev >= 5) {
503 u32 pll;
504 switch (bus->chipinfo.id) {
505 case BCMA_CHIP_ID_BCM4706:
506 - return bcma_pmu_clock_bcm4706(cc,
507 + return bcma_pmu_pll_clock_bcm4706(cc,
508 BCMA_CC_PMU4706_MAINPLL_PLL0,
509 BCMA_CC_PMU5_MAINPLL_CPU);
510 case BCMA_CHIP_ID_BCM5356:
511 @@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
512 break;
513 }
514
515 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
516 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
517 }
518
519 - return bcma_pmu_get_clockcontrol(cc);
520 + /* On old PMUs CPU has the same clock as the bus */
521 + return bcma_pmu_get_bus_clock(cc);
522 }
523
524 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
525 --- a/drivers/bcma/driver_chipcommon_sflash.c
526 +++ b/drivers/bcma/driver_chipcommon_sflash.c
527 @@ -12,7 +12,7 @@
528
529 static struct resource bcma_sflash_resource = {
530 .name = "bcma_sflash",
531 - .start = BCMA_SFLASH,
532 + .start = BCMA_SOC_FLASH2,
533 .end = 0,
534 .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
535 };
536 @@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
537 };
538
539 static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
540 - { "", 0x14, 0x10000, 32, },
541 + { "M25P20", 0x11, 0x10000, 4, },
542 + { "M25P40", 0x12, 0x10000, 8, },
543 +
544 + { "M25P16", 0x14, 0x10000, 32, },
545 + { "M25P32", 0x15, 0x10000, 64, },
546 + { "M25P64", 0x16, 0x10000, 128, },
547 + { "M25FL128", 0x17, 0x10000, 256, },
548 { 0 },
549 };
550
551 static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
552 + { "SST25WF512", 1, 0x1000, 16, },
553 + { "SST25VF512", 0x48, 0x1000, 16, },
554 + { "SST25WF010", 2, 0x1000, 32, },
555 + { "SST25VF010", 0x49, 0x1000, 32, },
556 + { "SST25WF020", 3, 0x1000, 64, },
557 + { "SST25VF020", 0x43, 0x1000, 64, },
558 + { "SST25WF040", 4, 0x1000, 128, },
559 + { "SST25VF040", 0x44, 0x1000, 128, },
560 + { "SST25VF040B", 0x8d, 0x1000, 128, },
561 + { "SST25WF080", 5, 0x1000, 256, },
562 + { "SST25VF080B", 0x8e, 0x1000, 256, },
563 + { "SST25VF016", 0x41, 0x1000, 512, },
564 + { "SST25VF032", 0x4a, 0x1000, 1024, },
565 + { "SST25VF064", 0x4b, 0x1000, 2048, },
566 { 0 },
567 };
568
569 static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
570 + { "AT45DB011", 0xc, 256, 512, },
571 + { "AT45DB021", 0x14, 256, 1024, },
572 + { "AT45DB041", 0x1c, 256, 2048, },
573 + { "AT45DB081", 0x24, 256, 4096, },
574 + { "AT45DB161", 0x2c, 512, 4096, },
575 + { "AT45DB321", 0x34, 512, 8192, },
576 + { "AT45DB642", 0x3c, 1024, 8192, },
577 { 0 },
578 };
579
580 @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
581 break;
582 }
583 break;
584 + case 0x13:
585 + return -ENOTSUPP;
586 default:
587 for (e = bcma_sflash_st_tbl; e->name; e++) {
588 if (e->id == id)
589 @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
590 return -ENOTSUPP;
591 }
592
593 - sflash->window = BCMA_SFLASH;
594 + sflash->window = BCMA_SOC_FLASH2;
595 sflash->blocksize = e->blocksize;
596 sflash->numblocks = e->numblocks;
597 sflash->size = sflash->blocksize * sflash->numblocks;
598 --- /dev/null
599 +++ b/drivers/bcma/driver_gpio.c
600 @@ -0,0 +1,98 @@
601 +/*
602 + * Broadcom specific AMBA
603 + * GPIO driver
604 + *
605 + * Copyright 2011, Broadcom Corporation
606 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
607 + *
608 + * Licensed under the GNU/GPL. See COPYING for details.
609 + */
610 +
611 +#include <linux/gpio.h>
612 +#include <linux/export.h>
613 +#include <linux/bcma/bcma.h>
614 +
615 +#include "bcma_private.h"
616 +
617 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
618 +{
619 + return container_of(chip, struct bcma_drv_cc, gpio);
620 +}
621 +
622 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
623 +{
624 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
625 +
626 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
627 +}
628 +
629 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
630 + int value)
631 +{
632 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
633 +
634 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
635 +}
636 +
637 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
638 +{
639 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
640 +
641 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
642 + return 0;
643 +}
644 +
645 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
646 + int value)
647 +{
648 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
649 +
650 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
651 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
652 + return 0;
653 +}
654 +
655 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
656 +{
657 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
658 +
659 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
660 + /* clear pulldown */
661 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
662 + /* Set pullup */
663 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
664 +
665 + return 0;
666 +}
667 +
668 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
669 +{
670 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
671 +
672 + /* clear pullup */
673 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
674 +}
675 +
676 +int bcma_gpio_init(struct bcma_drv_cc *cc)
677 +{
678 + struct gpio_chip *chip = &cc->gpio;
679 +
680 + chip->label = "bcma_gpio";
681 + chip->owner = THIS_MODULE;
682 + chip->request = bcma_gpio_request;
683 + chip->free = bcma_gpio_free;
684 + chip->get = bcma_gpio_get_value;
685 + chip->set = bcma_gpio_set_value;
686 + chip->direction_input = bcma_gpio_direction_input;
687 + chip->direction_output = bcma_gpio_direction_output;
688 + chip->ngpio = 16;
689 + /* There is just one SoC in one device and its GPIO addresses should be
690 + * deterministic to address them more easily. The other buses could get
691 + * a random base number. */
692 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
693 + chip->base = 0;
694 + else
695 + chip->base = -1;
696 +
697 + return gpiochip_add(chip);
698 +}
699 --- a/drivers/bcma/driver_mips.c
700 +++ b/drivers/bcma/driver_mips.c
701 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
702 return dev->core_index;
703 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
704
705 - return flag & 0x1F;
706 + if (flag)
707 + return flag & 0x1F;
708 + else
709 + return 0x3f;
710 }
711
712 /* Get the MIPS IRQ assignment for a specified device.
713 * If unassigned, 0 is returned.
714 + * If disabled, 5 is returned.
715 + * If not supported, 6 is returned.
716 */
717 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
718 {
719 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
720 unsigned int irq;
721
722 irqflag = bcma_core_mips_irqflag(dev);
723 + if (irqflag == 0x3f)
724 + return 6;
725
726 - for (irq = 1; irq <= 4; irq++)
727 + for (irq = 0; irq <= 4; irq++)
728 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
729 (1 << irqflag))
730 return irq;
731
732 - return 0;
733 + return 5;
734 }
735 EXPORT_SYMBOL(bcma_core_mips_irq);
736
737 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
738 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
739 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
740 ~(1 << irqflag));
741 - else
742 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
743 + else if (oldirq != 5)
744 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
745
746 /* assign the new one */
747 if (irq == 0) {
748 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
749 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
750 (1 << irqflag));
751 } else {
752 - u32 oldirqflag = bcma_read32(mdev,
753 - BCMA_MIPS_MIPS74K_INTMASK(irq));
754 - if (oldirqflag) {
755 + u32 irqinitmask = bcma_read32(mdev,
756 + BCMA_MIPS_MIPS74K_INTMASK(irq));
757 + if (irqinitmask) {
758 struct bcma_device *core;
759
760 /* backplane irq line is in use, find out who uses
761 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
762 */
763 list_for_each_entry(core, &bus->cores, list) {
764 if ((1 << bcma_core_mips_irqflag(core)) ==
765 - oldirqflag) {
766 + irqinitmask) {
767 bcma_core_mips_set_irq(core, 0);
768 break;
769 }
770 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
771 1 << irqflag);
772 }
773
774 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
775 - dev->id.id, oldirq + 2, irq + 2);
776 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
777 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
778 +}
779 +
780 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
781 + u16 coreid, u8 unit)
782 +{
783 + struct bcma_device *core;
784 +
785 + core = bcma_find_core_unit(bus, coreid, unit);
786 + if (!core) {
787 + bcma_warn(bus,
788 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
789 + coreid, unit);
790 + return;
791 + }
792 +
793 + bcma_core_mips_set_irq(core, irq);
794 }
795
796 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
797 {
798 int i;
799 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
800 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
801 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
802 for (i = 0; i <= 6; i++)
803 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
804 printk("\n");
805 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
806 struct bcma_bus *bus = mcore->core->bus;
807
808 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
809 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
810 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
811
812 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
813 return 0;
814 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
815 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
816 {
817 struct bcma_bus *bus = mcore->core->bus;
818 + struct bcma_drv_cc *cc = &bus->drv_cc;
819
820 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
821 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
822 case BCMA_CC_FLASHT_STSER:
823 case BCMA_CC_FLASHT_ATSER:
824 bcma_debug(bus, "Found serial flash\n");
825 - bcma_sflash_init(&bus->drv_cc);
826 + bcma_sflash_init(cc);
827 break;
828 case BCMA_CC_FLASHT_PARA:
829 bcma_debug(bus, "Found parallel flash\n");
830 - bus->drv_cc.pflash.window = 0x1c000000;
831 - bus->drv_cc.pflash.window_size = 0x02000000;
832 + cc->pflash.present = true;
833 + cc->pflash.window = BCMA_SOC_FLASH2;
834 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
835
836 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
837 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
838 BCMA_CC_FLASH_CFG_DS) == 0)
839 - bus->drv_cc.pflash.buswidth = 1;
840 + cc->pflash.buswidth = 1;
841 else
842 - bus->drv_cc.pflash.buswidth = 2;
843 + cc->pflash.buswidth = 2;
844 break;
845 default:
846 bcma_err(bus, "Flash type not supported\n");
847 }
848
849 - if (bus->drv_cc.core->id.rev == 38 ||
850 + if (cc->core->id.rev == 38 ||
851 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
852 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
853 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
854 bcma_debug(bus, "Found NAND flash\n");
855 - bcma_nflash_init(&bus->drv_cc);
856 + bcma_nflash_init(cc);
857 }
858 }
859 }
860
861 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
862 +{
863 + struct bcma_bus *bus = mcore->core->bus;
864 +
865 + if (mcore->early_setup_done)
866 + return;
867 +
868 + bcma_chipco_serial_init(&bus->drv_cc);
869 + bcma_core_mips_flash_detect(mcore);
870 +
871 + mcore->early_setup_done = true;
872 +}
873 +
874 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
875 {
876 struct bcma_bus *bus;
877 struct bcma_device *core;
878 bus = mcore->core->bus;
879
880 - bcma_info(bus, "Initializing MIPS core...\n");
881 + if (mcore->setup_done)
882 + return;
883
884 - if (!mcore->setup_done)
885 - mcore->assigned_irqs = 1;
886 + bcma_debug(bus, "Initializing MIPS core...\n");
887
888 - /* Assign IRQs to all cores on the bus */
889 - list_for_each_entry(core, &bus->cores, list) {
890 - int mips_irq;
891 - if (core->irq)
892 - continue;
893 -
894 - mips_irq = bcma_core_mips_irq(core);
895 - if (mips_irq > 4)
896 - core->irq = 0;
897 - else
898 - core->irq = mips_irq + 2;
899 - if (core->irq > 5)
900 - continue;
901 - switch (core->id.id) {
902 - case BCMA_CORE_PCI:
903 - case BCMA_CORE_PCIE:
904 - case BCMA_CORE_ETHERNET:
905 - case BCMA_CORE_ETHERNET_GBIT:
906 - case BCMA_CORE_MAC_GBIT:
907 - case BCMA_CORE_80211:
908 - case BCMA_CORE_USB20_HOST:
909 - /* These devices get their own IRQ line if available,
910 - * the rest goes on IRQ0
911 - */
912 - if (mcore->assigned_irqs <= 4)
913 - bcma_core_mips_set_irq(core,
914 - mcore->assigned_irqs++);
915 - break;
916 + bcma_core_mips_early_init(mcore);
917 +
918 + switch (bus->chipinfo.id) {
919 + case BCMA_CHIP_ID_BCM4716:
920 + case BCMA_CHIP_ID_BCM4748:
921 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
922 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
923 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
924 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
925 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
926 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
927 + break;
928 + case BCMA_CHIP_ID_BCM5356:
929 + case BCMA_CHIP_ID_BCM47162:
930 + case BCMA_CHIP_ID_BCM53572:
931 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
932 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
933 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
934 + break;
935 + case BCMA_CHIP_ID_BCM5357:
936 + case BCMA_CHIP_ID_BCM4749:
937 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
938 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
939 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
940 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
941 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
942 + break;
943 + case BCMA_CHIP_ID_BCM4706:
944 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
945 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
946 + 0);
947 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
948 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
949 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
950 + 0);
951 + break;
952 + default:
953 + list_for_each_entry(core, &bus->cores, list) {
954 + core->irq = bcma_core_mips_irq(core) + 2;
955 }
956 + bcma_err(bus,
957 + "Unknown device (0x%x) found, can not configure IRQs\n",
958 + bus->chipinfo.id);
959 }
960 - bcma_info(bus, "IRQ reconfiguration done\n");
961 + bcma_debug(bus, "IRQ reconfiguration done\n");
962 bcma_core_mips_dump_irq(bus);
963
964 - if (mcore->setup_done)
965 - return;
966 -
967 - bcma_chipco_serial_init(&bus->drv_cc);
968 - bcma_core_mips_flash_detect(mcore);
969 mcore->setup_done = true;
970 }
971 --- a/drivers/bcma/driver_pci_host.c
972 +++ b/drivers/bcma/driver_pci_host.c
973 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
974 chipid_top != 0x5300)
975 return false;
976
977 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
978 - bcma_info(bus, "This PCI core is disabled and not working\n");
979 - return false;
980 - }
981 -
982 bcma_core_enable(pc->core, 0);
983
984 return !mips_busprobe32(tmp, pc->core->io_addr);
985 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
986
987 bcma_info(bus, "PCIEcore in host mode found\n");
988
989 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
990 + bcma_info(bus, "This PCIE core is disabled and not working\n");
991 + return;
992 + }
993 +
994 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
995 if (!pc_host) {
996 bcma_err(bus, "can not allocate memory");
997 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
998 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
999 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1000 BCMA_SOC_PCI_MEM_SZ - 1;
1001 + pc_host->io_resource.start = 0x100;
1002 + pc_host->io_resource.end = 0x47F;
1003 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1004 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1005 tmp | BCMA_SOC_PCI_MEM);
1006 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1007 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1008 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1009 BCMA_SOC_PCI_MEM_SZ - 1;
1010 + pc_host->io_resource.start = 0x480;
1011 + pc_host->io_resource.end = 0x7FF;
1012 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1013 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1014 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1015 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1016 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1017 {
1018 struct resource *res;
1019 - int pos;
1020 + int pos, err;
1021
1022 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1023 /* This is not a device on the PCI-core bridge. */
1024 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1025
1026 for (pos = 0; pos < 6; pos++) {
1027 res = &dev->resource[pos];
1028 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1029 - pci_assign_resource(dev, pos);
1030 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1031 + err = pci_assign_resource(dev, pos);
1032 + if (err)
1033 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1034 + pci_name(dev));
1035 + }
1036 }
1037 }
1038 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1039 --- a/drivers/bcma/host_pci.c
1040 +++ b/drivers/bcma/host_pci.c
1041 @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1042 pci_set_drvdata(dev, NULL);
1043 }
1044
1045 -#ifdef CONFIG_PM
1046 +#ifdef CONFIG_PM_SLEEP
1047 static int bcma_host_pci_suspend(struct device *dev)
1048 {
1049 struct pci_dev *pdev = to_pci_dev(dev);
1050 @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1051 bcma_host_pci_resume);
1052 #define BCMA_PM_OPS (&bcma_pm_ops)
1053
1054 -#else /* CONFIG_PM */
1055 +#else /* CONFIG_PM_SLEEP */
1056
1057 #define BCMA_PM_OPS NULL
1058
1059 -#endif /* CONFIG_PM */
1060 +#endif /* CONFIG_PM_SLEEP */
1061
1062 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1063 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1064 --- a/drivers/bcma/main.c
1065 +++ b/drivers/bcma/main.c
1066 @@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1067 }
1068 EXPORT_SYMBOL_GPL(bcma_find_core);
1069
1070 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1071 + u8 unit)
1072 +{
1073 + struct bcma_device *core;
1074 +
1075 + list_for_each_entry(core, &bus->cores, list) {
1076 + if (core->id.id == coreid && core->core_unit == unit)
1077 + return core;
1078 + }
1079 + return NULL;
1080 +}
1081 +
1082 static void bcma_release_core_dev(struct device *dev)
1083 {
1084 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1085 @@ -152,6 +164,17 @@ static int bcma_register_cores(struct bc
1086 bcma_err(bus, "Error registering NAND flash\n");
1087 }
1088 #endif
1089 + err = bcma_gpio_init(&bus->drv_cc);
1090 + if (err == -ENOTSUPP)
1091 + bcma_debug(bus, "GPIO driver not activated\n");
1092 + else if (err)
1093 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1094 +
1095 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1096 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1097 + if (err)
1098 + bcma_err(bus, "Error registering watchdog driver\n");
1099 + }
1100
1101 return 0;
1102 }
1103 @@ -165,6 +188,8 @@ static void bcma_unregister_cores(struct
1104 if (core->dev_registered)
1105 device_unregister(&core->dev);
1106 }
1107 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1108 + platform_device_unregister(bus->drv_cc.watchdog);
1109 }
1110
1111 int __devinit bcma_bus_register(struct bcma_bus *bus)
1112 @@ -183,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1113 return -1;
1114 }
1115
1116 + /* Early init CC core */
1117 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1118 + if (core) {
1119 + bus->drv_cc.core = core;
1120 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1121 + }
1122 +
1123 + /* Try to get SPROM */
1124 + err = bcma_sprom_get(bus);
1125 + if (err == -ENOENT) {
1126 + bcma_err(bus, "No SPROM available\n");
1127 + } else if (err)
1128 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1129 +
1130 /* Init CC core */
1131 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1132 if (core) {
1133 @@ -198,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1134 }
1135
1136 /* Init PCIE core */
1137 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1138 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1139 if (core) {
1140 - bus->drv_pci.core = core;
1141 - bcma_core_pci_init(&bus->drv_pci);
1142 + bus->drv_pci[0].core = core;
1143 + bcma_core_pci_init(&bus->drv_pci[0]);
1144 + }
1145 +
1146 + /* Init PCIE core */
1147 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1148 + if (core) {
1149 + bus->drv_pci[1].core = core;
1150 + bcma_core_pci_init(&bus->drv_pci[1]);
1151 }
1152
1153 /* Init GBIT MAC COMMON core */
1154 @@ -211,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1155 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1156 }
1157
1158 - /* Try to get SPROM */
1159 - err = bcma_sprom_get(bus);
1160 - if (err == -ENOENT) {
1161 - bcma_err(bus, "No SPROM available\n");
1162 - } else if (err)
1163 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1164 -
1165 /* Register found cores */
1166 bcma_register_cores(bus);
1167
1168 @@ -275,18 +314,18 @@ int __init bcma_bus_early_register(struc
1169 return -1;
1170 }
1171
1172 - /* Init CC core */
1173 + /* Early init CC core */
1174 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1175 if (core) {
1176 bus->drv_cc.core = core;
1177 - bcma_core_chipcommon_init(&bus->drv_cc);
1178 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1179 }
1180
1181 - /* Init MIPS core */
1182 + /* Early init MIPS core */
1183 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1184 if (core) {
1185 bus->drv_mips.core = core;
1186 - bcma_core_mips_init(&bus->drv_mips);
1187 + bcma_core_mips_early_init(&bus->drv_mips);
1188 }
1189
1190 bcma_info(bus, "Early bus registered\n");
1191 --- a/drivers/bcma/sprom.c
1192 +++ b/drivers/bcma/sprom.c
1193 @@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1194 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1195
1196 err = bcma_sprom_valid(sprom);
1197 - if (err)
1198 + if (err) {
1199 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1200 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1201 goto out;
1202 + }
1203
1204 bcma_sprom_extract_r8(bus, sprom);
1205
1206 --- a/include/linux/bcma/bcma.h
1207 +++ b/include/linux/bcma/bcma.h
1208 @@ -157,6 +157,7 @@ struct bcma_host_ops {
1209
1210 /* Chip IDs of SoCs */
1211 #define BCMA_CHIP_ID_BCM4706 0x5300
1212 +#define BCMA_PKG_ID_BCM4706L 1
1213 #define BCMA_CHIP_ID_BCM4716 0x4716
1214 #define BCMA_PKG_ID_BCM4716 8
1215 #define BCMA_PKG_ID_BCM4717 9
1216 @@ -166,7 +167,11 @@ struct bcma_host_ops {
1217 #define BCMA_CHIP_ID_BCM4749 0x4749
1218 #define BCMA_CHIP_ID_BCM5356 0x5356
1219 #define BCMA_CHIP_ID_BCM5357 0x5357
1220 +#define BCMA_PKG_ID_BCM5358 9
1221 +#define BCMA_PKG_ID_BCM47186 10
1222 +#define BCMA_PKG_ID_BCM5357 11
1223 #define BCMA_CHIP_ID_BCM53572 53572
1224 +#define BCMA_PKG_ID_BCM47188 9
1225
1226 struct bcma_device {
1227 struct bcma_bus *bus;
1228 @@ -251,7 +256,7 @@ struct bcma_bus {
1229 u8 num;
1230
1231 struct bcma_drv_cc drv_cc;
1232 - struct bcma_drv_pci drv_pci;
1233 + struct bcma_drv_pci drv_pci[2];
1234 struct bcma_drv_mips drv_mips;
1235 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1236
1237 @@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
1238 enum bcma_clkmode clkmode);
1239 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1240 bool on);
1241 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1242 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1243 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1244 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1245 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1246 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1247 @@ -1,6 +1,9 @@
1248 #ifndef LINUX_BCMA_DRIVER_CC_H_
1249 #define LINUX_BCMA_DRIVER_CC_H_
1250
1251 +#include <linux/platform_device.h>
1252 +#include <linux/gpio.h>
1253 +
1254 /** ChipCommon core registers. **/
1255 #define BCMA_CC_ID 0x0000
1256 #define BCMA_CC_ID_ID 0x0000FFFF
1257 @@ -510,6 +513,7 @@ struct bcma_chipcommon_pmu {
1258
1259 #ifdef CONFIG_BCMA_DRIVER_MIPS
1260 struct bcma_pflash {
1261 + bool present;
1262 u8 buswidth;
1263 u32 window;
1264 u32 window_size;
1265 @@ -532,6 +536,7 @@ struct mtd_info;
1266
1267 struct bcma_nflash {
1268 bool present;
1269 + bool boot; /* This is the flash the SoC boots from */
1270
1271 struct mtd_info *mtd;
1272 };
1273 @@ -552,6 +557,7 @@ struct bcma_drv_cc {
1274 u32 capabilities;
1275 u32 capabilities_ext;
1276 u8 setup_done:1;
1277 + u8 early_setup_done:1;
1278 /* Fast Powerup Delay constant */
1279 u16 fast_pwrup_delay;
1280 struct bcma_chipcommon_pmu pmu;
1281 @@ -567,6 +573,14 @@ struct bcma_drv_cc {
1282 int nr_serial_ports;
1283 struct bcma_serial_port serial_ports[4];
1284 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1285 + u32 ticks_per_ms;
1286 + struct platform_device *watchdog;
1287 +
1288 + /* Lock for GPIO register access. */
1289 + spinlock_t gpio_lock;
1290 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1291 + struct gpio_chip gpio;
1292 +#endif
1293 };
1294
1295 /* Register access */
1296 @@ -583,14 +597,14 @@ struct bcma_drv_cc {
1297 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1298
1299 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1300 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1301
1302 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1303 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1304
1305 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1306
1307 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1308 - u32 ticks);
1309 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1310
1311 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1312
1313 @@ -603,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1314 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1315 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1316 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1317 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1318 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1319
1320 /* PMU support */
1321 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1322 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1323
1324 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1325 u32 value);
1326 --- a/include/linux/bcma/bcma_driver_mips.h
1327 +++ b/include/linux/bcma/bcma_driver_mips.h
1328 @@ -35,13 +35,15 @@ struct bcma_device;
1329 struct bcma_drv_mips {
1330 struct bcma_device *core;
1331 u8 setup_done:1;
1332 - unsigned int assigned_irqs;
1333 + u8 early_setup_done:1;
1334 };
1335
1336 #ifdef CONFIG_BCMA_DRIVER_MIPS
1337 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1338 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1339 #else
1340 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1341 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1342 #endif
1343
1344 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1345 --- a/include/linux/bcma/bcma_regs.h
1346 +++ b/include/linux/bcma/bcma_regs.h
1347 @@ -85,6 +85,9 @@
1348 * (2 ZettaBytes), high 32 bits
1349 */
1350
1351 -#define BCMA_SFLASH 0x1c000000
1352 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1353 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1354 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1355 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1356
1357 #endif /* LINUX_BCMA_REGS_H_ */
1358 --- a/drivers/net/wireless/b43/main.c
1359 +++ b/drivers/net/wireless/b43/main.c
1360 @@ -4656,7 +4656,7 @@ static int b43_wireless_core_init(struct
1361 switch (dev->dev->bus_type) {
1362 #ifdef CONFIG_B43_BCMA
1363 case B43_BUS_BCMA:
1364 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1365 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1366 dev->dev->bdev, true);
1367 break;
1368 #endif
1369 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1370 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1371 @@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
1372 sii = container_of(sih, struct si_info, pub);
1373
1374 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1375 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1376 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1377 }
1378
1379 /* Unconfigure and/or apply various WARs when going down */
1380 @@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
1381 sii = container_of(sih, struct si_info, pub);
1382
1383 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1384 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1385 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1386 }
1387
1388 /* Enable BT-COEX & Ex-PA for 4313 */
1389 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1390 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1391 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1392 * Configure pci/pcmcia here instead of in brcms_c_attach()
1393 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1394 */
1395 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1396 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
1397 true);
1398
1399 /*
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