target/linux/generic/pending-4.14/840-can-flexcan-flexcan_chip_freeze-fix-chip-freeze-for-.patch

   1 From 47c5e474bc1e1061fb037d13b5000b38967eb070 Mon Sep 17 00:00:00 2001
   2 From: Angelo Dureghello <angelo@kernel-space.org>
   3 Date: Tue, 16 Mar 2021 00:15:10 +0100
   4 Subject: can: flexcan: flexcan_chip_freeze(): fix chip freeze for missing bitrate
   5
   6 From: Angelo Dureghello <angelo@kernel-space.org>
   7
   8 commit 47c5e474bc1e1061fb037d13b5000b38967eb070 upstream.
   9
  10 For cases when flexcan is built-in, bitrate is still not set at
  11 registering. So flexcan_chip_freeze() generates:
  12
  13 [    1.860000] *** ZERO DIVIDE ***   FORMAT=4
  14 [    1.860000] Current process id is 1
  15 [    1.860000] BAD KERNEL TRAP: 00000000
  16 [    1.860000] PC: [<402e70c8>] flexcan_chip_freeze+0x1a/0xa8
  17
  18 To allow chip freeze, using an hardcoded timeout when bitrate is still
  19 not set.
  20
  21 Fixes: ec15e27cc890 ("can: flexcan: enable RX FIFO after FRZ/HALT valid")
  22 Link: https://lore.kernel.org/r/20210315231510.650593-1-angelo@kernel-space.org
  23 Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
  24 [mkl: use if instead of ? operator]
  25 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  26 Cc: Koen Vandeputte <koen.vandeputte@citymesh.com>
  27 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  28 ---
  29  drivers/net/can/flexcan.c |    8 +++++++-
  30  1 file changed, 7 insertions(+), 1 deletion(-)
  31
  32 --- a/drivers/net/can/flexcan.c
  33 +++ b/drivers/net/can/flexcan.c
  34 @@ -413,9 +413,15 @@ static int flexcan_chip_disable(struct f
  35  static int flexcan_chip_freeze(struct flexcan_priv *priv)
  36  {
  37         struct flexcan_regs __iomem *regs = priv->regs;
  38 -       unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
  39 +       unsigned int timeout;
  40 +       u32 bitrate = priv->can.bittiming.bitrate;
  41         u32 reg;
  42
  43 +       if (bitrate)
  44 +               timeout = 1000 * 1000 * 10 / bitrate;
  45 +       else
  46 +               timeout = FLEXCAN_TIMEOUT_US / 10;
  47 +
  48         reg = flexcan_read(&regs->mcr);
  49         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
  50         flexcan_write(reg, &regs->mcr);