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mediatek: sync MT7988 USXGMII with SDK driver
[openwrt/openwrt.git] / target / linux / generic / pending-5.15 / 737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
1 From 3d833ad2cfc1ab503d9aae2967b7f10811bb3c9c Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Wed, 1 Mar 2023 11:56:04 +0000
4 Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes
5 for MT7988
6
7 MT7988 comes with a built-in 2.5G PHY as well as
8 USXGMII/10GBase-KR/5GBase-KR compatible SerDes lanes for external PHYs.
9 Add support for configuring the MAC and SerDes parts for the new paths.
10
11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
12 ---
13 drivers/net/ethernet/mediatek/Kconfig | 7 +
14 drivers/net/ethernet/mediatek/Makefile | 1 +
15 drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 +++-
16 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 270 +++++-
17 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 194 ++++-
18 drivers/net/ethernet/mediatek/mtk_usxgmii.c | 835 +++++++++++++++++++
19 6 files changed, 1428 insertions(+), 33 deletions(-)
20 create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
21
22 --- a/drivers/net/ethernet/mediatek/Kconfig
23 +++ b/drivers/net/ethernet/mediatek/Kconfig
24 @@ -24,6 +24,13 @@ config NET_MEDIATEK_SOC
25 This driver supports the gigabit ethernet MACs in the
26 MediaTek SoC family.
27
28 +config NET_MEDIATEK_SOC_USXGMII
29 + bool "Support USXGMII SerDes on MT7988"
30 + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
31 + def_bool NET_MEDIATEK_SOC != n
32 + help
33 + Include support for 10G SerDes which can be found on MT7988.
34 +
35 config NET_MEDIATEK_STAR_EMAC
36 tristate "MediaTek STAR Ethernet MAC support"
37 select PHYLIB
38 --- a/drivers/net/ethernet/mediatek/Makefile
39 +++ b/drivers/net/ethernet/mediatek/Makefile
40 @@ -5,6 +5,7 @@
41
42 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
43 mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
44 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
45 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
46 ifdef CONFIG_DEBUG_FS
47 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
48 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
49 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
50 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
51 return "gmac2_rgmii";
52 case MTK_ETH_PATH_GMAC2_SGMII:
53 return "gmac2_sgmii";
54 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
55 + return "gmac2_2p5gphy";
56 case MTK_ETH_PATH_GMAC2_GEPHY:
57 return "gmac2_gephy";
58 + case MTK_ETH_PATH_GMAC3_SGMII:
59 + return "gmac3_sgmii";
60 case MTK_ETH_PATH_GDM1_ESW:
61 return "gdm1_esw";
62 + case MTK_ETH_PATH_GMAC1_USXGMII:
63 + return "gmac1_usxgmii";
64 + case MTK_ETH_PATH_GMAC2_USXGMII:
65 + return "gmac2_usxgmii";
66 + case MTK_ETH_PATH_GMAC3_USXGMII:
67 + return "gmac3_usxgmii";
68 default:
69 return "unknown path";
70 }
71 @@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64
72
73 static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
74 {
75 + u32 val, mask, set, reg;
76 bool updated = true;
77 - u32 val, mask, set;
78
79 switch (path) {
80 case MTK_ETH_PATH_GMAC1_SGMII:
81 @@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str
82 break;
83 }
84
85 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
86 + reg = MTK_MAC_MISC_V3;
87 + else
88 + reg = MTK_MAC_MISC;
89 +
90 if (updated) {
91 - val = mtk_r32(eth, MTK_MAC_MISC);
92 + val = mtk_r32(eth, reg);
93 val = (val & mask) | set;
94 - mtk_w32(eth, val, MTK_MAC_MISC);
95 + mtk_w32(eth, val, reg);
96 }
97
98 dev_dbg(eth->dev, "path %s in %s updated = %d\n",
99 @@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru
100 return 0;
101 }
102
103 +static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
104 +{
105 + unsigned int val = 0;
106 + bool updated = true;
107 + int mac_id = 0;
108 +
109 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
110 +
111 + switch (path) {
112 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
113 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
114 + mac_id = MTK_GMAC2_ID;
115 + break;
116 + default:
117 + updated = false;
118 + break;
119 + };
120 +
121 + if (updated)
122 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
123 + SYSCFG0_SGMII_MASK, val);
124 +
125 + return 0;
126 +}
127 +
128 static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
129 {
130 unsigned int val = 0;
131 @@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_
132 return 0;
133 }
134
135 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
136 +static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
137 +{
138 + unsigned int val = 0;
139 + bool updated = true;
140 + int mac_id = 0;
141 +
142 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
143 + mtk_eth_path_name(path), __func__, updated);
144 +
145 + /* Disable SYSCFG1 SGMII */
146 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
147 +
148 + switch (path) {
149 + case MTK_ETH_PATH_GMAC1_USXGMII:
150 + val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
151 + mac_id = MTK_GMAC1_ID;
152 + break;
153 + case MTK_ETH_PATH_GMAC2_USXGMII:
154 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
155 + mac_id = MTK_GMAC2_ID;
156 + break;
157 + case MTK_ETH_PATH_GMAC3_USXGMII:
158 + val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
159 + mac_id = MTK_GMAC3_ID;
160 + break;
161 + default:
162 + updated = false;
163 + };
164 +
165 + if (updated) {
166 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
167 + SYSCFG0_SGMII_MASK, val);
168 +
169 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
170 + mac_id == MTK_GMAC2_ID) {
171 + regmap_update_bits(eth->infra,
172 + TOP_MISC_NETSYS_PCS_MUX,
173 + NETSYS_PCS_MUX_MASK,
174 + MUX_G2_USXGMII_SEL);
175 + }
176 + }
177 +
178 + /* Enable XGDM Path */
179 + val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id));
180 + val |= MTK_GDMA_XGDM_SEL;
181 + mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id));
182 +
183 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
184 + mtk_eth_path_name(path), __func__, updated);
185 +
186 +
187 + return 0;
188 +}
189 +
190 +static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
191 {
192 unsigned int val = 0;
193 bool updated = true;
194 @@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii
195 case MTK_ETH_PATH_GMAC2_SGMII:
196 val |= SYSCFG0_SGMII_GMAC2_V2;
197 break;
198 + case MTK_ETH_PATH_GMAC3_SGMII:
199 + val |= SYSCFG0_SGMII_GMAC3_V2;
200 + break;
201 default:
202 updated = false;
203 }
204 @@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth
205 .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
206 .set_path = set_mux_u3_gmac2_to_qphy,
207 }, {
208 + .name = "mux_gmac2_to_2p5gphy",
209 + .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
210 + .set_path = set_mux_gmac2_to_2p5gphy,
211 + }, {
212 .name = "mux_gmac1_gmac2_to_sgmii_rgmii",
213 .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
214 .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
215 }, {
216 .name = "mux_gmac12_to_gephy_sgmii",
217 .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
218 - .set_path = set_mux_gmac12_to_gephy_sgmii,
219 + .set_path = set_mux_gmac123_to_gephy_sgmii,
220 + }, {
221 + .name = "mux_gmac123_to_gephy_sgmii",
222 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
223 + .set_path = set_mux_gmac123_to_gephy_sgmii,
224 + }, {
225 + .name = "mux_gmac123_to_usxgmii",
226 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
227 + .set_path = set_mux_gmac123_to_usxgmii,
228 },
229 };
230
231 @@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_
232 }
233 }
234
235 + dev_dbg(eth->dev, "leaving mux_setup %s\n",
236 + mtk_eth_path_name(path));
237 +
238 out:
239 return err;
240 }
241
242 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
243 +{
244 + u64 path;
245 +
246 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
247 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
248 + MTK_ETH_PATH_GMAC3_USXGMII;
249 +
250 + /* Setup proper MUXes along the path */
251 + return mtk_eth_mux_setup(eth, path);
252 +}
253 +
254 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
255 {
256 u64 path;
257
258 - path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
259 - MTK_ETH_PATH_GMAC2_SGMII;
260 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
261 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
262 + MTK_ETH_PATH_GMAC3_SGMII;
263 +
264 + /* Setup proper MUXes along the path */
265 + return mtk_eth_mux_setup(eth, path);
266 +}
267 +
268 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
269 +{
270 + u64 path = 0;
271 +
272 + if (mac_id == MTK_GMAC2_ID)
273 + path = MTK_ETH_PATH_GMAC2_2P5GPHY;
274 +
275 + if (!path)
276 + return -EINVAL;
277
278 /* Setup proper MUXes along the path */
279 return mtk_eth_mux_setup(eth, path);
280 @@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
281 /* Setup proper MUXes along the path */
282 return mtk_eth_mux_setup(eth, path);
283 }
284 -
285 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
286 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
287 @@ -437,6 +437,23 @@ static void mtk_gmac0_rgmii_adjust(struc
288 mtk_w32(eth, val, TRGMII_TCK_CTRL);
289 }
290
291 +static void mtk_setup_bridge_switch(struct mtk_eth *eth)
292 +{
293 + int val;
294 +
295 + /* Force Port1 XGMAC Link Up */
296 + val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID));
297 + mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
298 + MTK_XGMAC_STS(MTK_GMAC1_ID));
299 +
300 + /* Adjust GSW bridge IPG to 11*/
301 + val = mtk_r32(eth, MTK_GSW_CFG);
302 + val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK);
303 + val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
304 + (GSW_IPG_11 << GSWRX_IPG_SHIFT);
305 + mtk_w32(eth, val, MTK_GSW_CFG);
306 +}
307 +
308 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
309 phy_interface_t interface)
310 {
311 @@ -451,6 +468,12 @@ static struct phylink_pcs *mtk_mac_selec
312 0 : mac->id;
313
314 return eth->sgmii_pcs[sid];
315 + } else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
316 + interface == PHY_INTERFACE_MODE_10GKR ||
317 + interface == PHY_INTERFACE_MODE_5GBASER) &&
318 + MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
319 + mac->id != MTK_GMAC1_ID) {
320 + return mtk_usxgmii_select_pcs(eth, mac->id);
321 }
322
323 return NULL;
324 @@ -462,7 +485,7 @@ static void mtk_mac_config(struct phylin
325 struct mtk_mac *mac = container_of(config, struct mtk_mac,
326 phylink_config);
327 struct mtk_eth *eth = mac->hw;
328 - int val, ge_mode, err = 0;
329 + int val, ge_mode, force_link, err = 0;
330 u32 i;
331
332 /* MT76x8 has no hardware settings between for the MAC */
333 @@ -506,6 +529,23 @@ static void mtk_mac_config(struct phylin
334 goto init_err;
335 }
336 break;
337 + case PHY_INTERFACE_MODE_USXGMII:
338 + case PHY_INTERFACE_MODE_10GKR:
339 + case PHY_INTERFACE_MODE_5GBASER:
340 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
341 + err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
342 + if (err)
343 + goto init_err;
344 + }
345 + break;
346 + case PHY_INTERFACE_MODE_INTERNAL:
347 + if (mac->id == MTK_GMAC2_ID &&
348 + MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
349 + err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
350 + if (err)
351 + goto init_err;
352 + }
353 + break;
354 default:
355 goto err_phy;
356 }
357 @@ -584,14 +624,78 @@ static void mtk_mac_config(struct phylin
358 SYSCFG0_SGMII_MASK,
359 ~(u32)SYSCFG0_SGMII_MASK);
360
361 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
362 + mtk_xfi_pll_enable(eth);
363 + mtk_sgmii_reset(eth, mac->id);
364 + if (phylink_autoneg_inband(mode))
365 + mtk_sgmii_setup_phya_gen1(eth, mac->id);
366 + else
367 + mtk_sgmii_setup_phya_gen2(eth, mac->id);
368 + }
369 /* Save the syscfg0 value for mac_finish */
370 mac->syscfg0 = val;
371 - } else if (phylink_autoneg_inband(mode)) {
372 + } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
373 + state->interface != PHY_INTERFACE_MODE_10GKR &&
374 + state->interface != PHY_INTERFACE_MODE_5GBASER &&
375 + phylink_autoneg_inband(mode)) {
376 dev_err(eth->dev,
377 - "In-band mode not supported in non SGMII mode!\n");
378 + "In-band mode not supported in non-SerDes modes!\n");
379 return;
380 }
381
382 + /* Setup gmac */
383 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
384 + (mtk_interface_mode_is_xgmii(state->interface) ||
385 + mac->interface == PHY_INTERFACE_MODE_INTERNAL)) {
386 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
387 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
388 +
389 + switch (mac->id) {
390 + case MTK_GMAC1_ID:
391 + mtk_setup_bridge_switch(eth);
392 + break;
393 + case MTK_GMAC2_ID:
394 + force_link = (mac->interface ==
395 + PHY_INTERFACE_MODE_INTERNAL) ?
396 + MTK_XGMAC_FORCE_LINK(mac->id) : 0;
397 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
398 + mtk_w32(eth, val | force_link,
399 + MTK_XGMAC_STS(mac->id));
400 + break;
401 + case MTK_GMAC3_ID:
402 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
403 + mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id),
404 + MTK_XGMAC_STS(mac->id));
405 + break;
406 + }
407 + } else {
408 + val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id));
409 + mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL,
410 + MTK_GDMA_EG_CTRL(mac->id));
411 +
412 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
413 + switch (mac->id) {
414 + case MTK_GMAC2_ID:
415 + case MTK_GMAC3_ID:
416 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
417 + mtk_w32(eth,
418 + val & ~MTK_XGMAC_FORCE_LINK(mac->id),
419 + MTK_XGMAC_STS(mac->id));
420 + break;
421 + }
422 + }
423 +
424 +/*
425 + if (mac->type != mac_type) {
426 + if (atomic_read(&reset_pending) == 0) {
427 + atomic_inc(&force);
428 + schedule_work(&eth->pending_work);
429 + atomic_inc(&reset_pending);
430 + } else
431 + atomic_dec(&reset_pending);
432 + }
433 +*/
434 + }
435 return;
436
437 err_phy:
438 @@ -632,11 +736,40 @@ static int mtk_mac_finish(struct phylink
439 return 0;
440 }
441
442 -static void mtk_mac_pcs_get_state(struct phylink_config *config,
443 +static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac,
444 + struct phylink_link_state *state)
445 +{
446 + u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
447 +
448 + if (mac->id == MTK_GMAC2_ID)
449 + sts = sts >> 16;
450 +
451 + state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts);
452 + if (!state->link)
453 + return;
454 +
455 + state->duplex = DUPLEX_FULL;
456 + state->interface = mac->interface;
457 +
458 + switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) {
459 + case 0:
460 + state->speed = SPEED_10000;
461 + break;
462 + case 1:
463 + state->speed = SPEED_5000;
464 + break;
465 + case 2:
466 + state->speed = SPEED_2500;
467 + break;
468 + case 3:
469 + state->speed = SPEED_1000;
470 + break;
471 + }
472 +}
473 +
474 +static void mtk_gdm_pcs_get_state(struct mtk_mac *mac,
475 struct phylink_link_state *state)
476 {
477 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
478 - phylink_config);
479 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
480
481 state->link = (pmsr & MAC_MSR_LINK);
482 @@ -664,15 +797,35 @@ static void mtk_mac_pcs_get_state(struct
483 state->pause |= MLO_PAUSE_TX;
484 }
485
486 +static void mtk_mac_pcs_get_state(struct phylink_config *config,
487 + struct phylink_link_state *state)
488 +{
489 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
490 + phylink_config);
491 +
492 + if (mtk_interface_mode_is_xgmii(state->interface))
493 + mtk_xgdm_pcs_get_state(mac, state);
494 + else
495 + mtk_gdm_pcs_get_state(mac, state);
496 +}
497 +
498 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
499 phy_interface_t interface)
500 {
501 struct mtk_mac *mac = container_of(config, struct mtk_mac,
502 phylink_config);
503 - u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
504 + u32 mcr;
505
506 - mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
507 - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
508 + if (!mtk_interface_mode_is_xgmii(interface)) {
509 + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
510 + mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
511 + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
512 + } else if (mac->id != MTK_GMAC1_ID) {
513 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
514 + mcr &= 0xfffffff0;
515 + mcr |= XMAC_MCR_TRX_DISABLE;
516 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
517 + }
518 }
519
520 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
521 @@ -744,13 +897,11 @@ static void mtk_set_queue_speed(struct m
522 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
523 }
524
525 -static void mtk_mac_link_up(struct phylink_config *config,
526 - struct phy_device *phy,
527 - unsigned int mode, phy_interface_t interface,
528 - int speed, int duplex, bool tx_pause, bool rx_pause)
529 +static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
530 + struct phy_device *phy,
531 + unsigned int mode, phy_interface_t interface,
532 + int speed, int duplex, bool tx_pause, bool rx_pause)
533 {
534 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
535 - phylink_config);
536 u32 mcr;
537
538 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
539 @@ -784,6 +935,47 @@ static void mtk_mac_link_up(struct phyli
540 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
541 }
542
543 +static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
544 + struct phy_device *phy,
545 + unsigned int mode, phy_interface_t interface,
546 + int speed, int duplex, bool tx_pause, bool rx_pause)
547 +{
548 + u32 mcr;
549 +
550 + if (mac->id == MTK_GMAC1_ID)
551 + return;
552 +
553 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
554 +
555 + mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC);
556 + /* Configure pause modes -
557 + * phylink will avoid these for half duplex
558 + */
559 + if (tx_pause)
560 + mcr |= XMAC_MCR_FORCE_TX_FC;
561 + if (rx_pause)
562 + mcr |= XMAC_MCR_FORCE_RX_FC;
563 +
564 + mcr &= ~(XMAC_MCR_TRX_DISABLE);
565 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
566 +}
567 +
568 +static void mtk_mac_link_up(struct phylink_config *config,
569 + struct phy_device *phy,
570 + unsigned int mode, phy_interface_t interface,
571 + int speed, int duplex, bool tx_pause, bool rx_pause)
572 +{
573 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
574 + phylink_config);
575 +
576 + if (mtk_interface_mode_is_xgmii(interface))
577 + mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
578 + tx_pause, rx_pause);
579 + else
580 + mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
581 + tx_pause, rx_pause);
582 +}
583 +
584 static const struct phylink_mac_ops mtk_phylink_ops = {
585 .validate = phylink_generic_validate,
586 .mac_select_pcs = mtk_mac_select_pcs,
587 @@ -836,10 +1028,21 @@ static int mtk_mdio_init(struct mtk_eth
588 }
589 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
590
591 + /* Configure MDC Turbo Mode */
592 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
593 + val = mtk_r32(eth, MTK_MAC_MISC_V3);
594 + val |= MISC_MDC_TURBO;
595 + mtk_w32(eth, val, MTK_MAC_MISC_V3);
596 + } else {
597 + val = mtk_r32(eth, MTK_PPSC);
598 + val |= PPSC_MDC_TURBO;
599 + mtk_w32(eth, val, MTK_PPSC);
600 + }
601 +
602 /* Configure MDC Divider */
603 val = mtk_r32(eth, MTK_PPSC);
604 val &= ~PPSC_MDC_CFG;
605 - val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
606 + val |= FIELD_PREP(PPSC_MDC_CFG, divider);
607 mtk_w32(eth, val, MTK_PPSC);
608
609 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
610 @@ -4433,8 +4636,8 @@ static int mtk_add_mac(struct mtk_eth *e
611 const __be32 *_id = of_get_property(np, "reg", NULL);
612 phy_interface_t phy_mode;
613 struct phylink *phylink;
614 - struct mtk_mac *mac;
615 int id, err;
616 + struct mtk_mac *mac;
617 int txqs = 1;
618
619 if (!_id) {
620 @@ -4525,6 +4728,32 @@ static int mtk_add_mac(struct mtk_eth *e
621 mac->phylink_config.supported_interfaces);
622 }
623
624 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
625 + if (id == MTK_GMAC1_ID) {
626 + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
627 + MAC_SYM_PAUSE |
628 + MAC_10000FD;
629 + phy_interface_zero(
630 + mac->phylink_config.supported_interfaces);
631 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
632 + mac->phylink_config.supported_interfaces);
633 + } else {
634 + mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
635 + __set_bit(PHY_INTERFACE_MODE_5GBASER,
636 + mac->phylink_config.supported_interfaces);
637 + __set_bit(PHY_INTERFACE_MODE_10GKR,
638 + mac->phylink_config.supported_interfaces);
639 + __set_bit(PHY_INTERFACE_MODE_USXGMII,
640 + mac->phylink_config.supported_interfaces);
641 + }
642 + }
643 +
644 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) {
645 + if (id == MTK_GMAC2_ID)
646 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
647 + mac->phylink_config.supported_interfaces);
648 + }
649 +
650 phylink = phylink_create(&mac->phylink_config,
651 of_fwnode_handle(mac->of_node),
652 phy_mode, &mtk_phylink_ops);
653 @@ -4712,6 +4941,13 @@ static int mtk_probe(struct platform_dev
654
655 if (err)
656 return err;
657 + }
658 +
659 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
660 + err = mtk_usxgmii_init(eth);
661 +
662 + if (err)
663 + return err;
664 }
665
666 if (eth->soc->required_pctl) {
667 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
668 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
669 @@ -126,6 +126,11 @@
670 #define MTK_GDMA_TO_PDMA 0x0
671 #define MTK_GDMA_DROP_ALL 0x7777
672
673 +/* GDM Egress Control Register */
674 +#define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \
675 + 0x544 : 0x504 + (x * 0x1000))
676 +#define MTK_GDMA_XGDM_SEL BIT(31)
677 +
678 /* Unicast Filter MAC Address Register - Low */
679 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
680
681 @@ -386,7 +391,26 @@
682 #define PHY_IAC_TIMEOUT HZ
683
684 #define MTK_MAC_MISC 0x1000c
685 +#define MTK_MAC_MISC_V3 0x10010
686 #define MTK_MUX_TO_ESW BIT(0)
687 +#define MISC_MDC_TURBO BIT(4)
688 +
689 +/* XMAC status registers */
690 +#define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
691 +#define MTK_XGMAC_FORCE_LINK(x) ((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
692 +#define MTK_USXGMII_PCS_LINK BIT(8)
693 +#define MTK_XGMAC_RX_FC BIT(5)
694 +#define MTK_XGMAC_TX_FC BIT(4)
695 +#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
696 +#define MTK_XGMAC_LINK_STS BIT(0)
697 +
698 +/* GSW bridge registers */
699 +#define MTK_GSW_CFG (0x10080)
700 +#define GSWTX_IPG_MASK GENMASK(19, 16)
701 +#define GSWTX_IPG_SHIFT 16
702 +#define GSWRX_IPG_MASK GENMASK(3, 0)
703 +#define GSWRX_IPG_SHIFT 0
704 +#define GSW_IPG_11 11
705
706 /* Mac control registers */
707 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
708 @@ -411,6 +435,17 @@
709 #define MAC_MCR_FORCE_LINK BIT(0)
710 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
711
712 +/* Mac EEE control registers */
713 +#define MTK_MAC_EEE(x) (0x10104 + (x * 0x100))
714 +#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24)
715 +#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16)
716 +#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8)
717 +#define MAC_EEE_RESV0 GENMASK(7, 4)
718 +#define MAC_EEE_CKG_TXILDE BIT(3)
719 +#define MAC_EEE_CKG_RXLPI BIT(2)
720 +#define MAC_EEE_TX_DOWN_REQ BIT(1)
721 +#define MAC_EEE_LPI_MODE BIT(0)
722 +
723 /* Mac status registers */
724 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
725 #define MAC_MSR_EEE1G BIT(7)
726 @@ -455,6 +490,12 @@
727 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
728 #define INTF_MODE_RGMII_10_100 0
729
730 +/* XFI Mac control registers */
731 +#define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000))
732 +#define XMAC_MCR_TRX_DISABLE 0xf
733 +#define XMAC_MCR_FORCE_TX_FC BIT(5)
734 +#define XMAC_MCR_FORCE_RX_FC BIT(4)
735 +
736 /* GPIO port control registers for GMAC 2*/
737 #define GPIO_OD33_CTRL8 0x4c0
738 #define GPIO_BIAS_CTRL 0xed0
739 @@ -480,6 +521,7 @@
740 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
741 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
742 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
743 +#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
744
745
746 /* ethernet subsystem clock register */
747 @@ -506,16 +548,91 @@
748 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
749 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
750
751 +/* USXGMII subsystem config registers */
752 +/* Register to control speed */
753 +#define RG_PHY_TOP_SPEED_CTRL1 0x80C
754 +#define USXGMII_RATE_UPDATE_MODE BIT(31)
755 +#define USXGMII_MAC_CK_GATED BIT(29)
756 +#define USXGMII_IF_FORCE_EN BIT(28)
757 +#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
758 +#define USXGMII_RATE_ADAPT_MODE_X1 0
759 +#define USXGMII_RATE_ADAPT_MODE_X2 1
760 +#define USXGMII_RATE_ADAPT_MODE_X4 2
761 +#define USXGMII_RATE_ADAPT_MODE_X10 3
762 +#define USXGMII_RATE_ADAPT_MODE_X100 4
763 +#define USXGMII_RATE_ADAPT_MODE_X5 5
764 +#define USXGMII_RATE_ADAPT_MODE_X50 6
765 +#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
766 +#define USXGMII_XFI_RX_MODE_10G 0
767 +#define USXGMII_XFI_RX_MODE_5G 1
768 +#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
769 +#define USXGMII_XFI_TX_MODE_10G 0
770 +#define USXGMII_XFI_TX_MODE_5G 1
771 +
772 +/* Register to control PCS AN */
773 +#define RG_PCS_AN_CTRL0 0x810
774 +#define USXGMII_AN_RESTART BIT(31)
775 +#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
776 +#define USXGMII_AN_ENABLE BIT(0)
777 +
778 +#define RG_PCS_AN_CTRL2 0x818
779 +#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
780 +#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
781 +#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
782 +
783 +/* Register to read PCS AN status */
784 +#define RG_PCS_AN_STS0 0x81c
785 +#define USXGMII_LPA_SPEED_MASK GENMASK(11, 9)
786 +#define USXGMII_LPA_SPEED_10 0
787 +#define USXGMII_LPA_SPEED_100 1
788 +#define USXGMII_LPA_SPEED_1000 2
789 +#define USXGMII_LPA_SPEED_10000 3
790 +#define USXGMII_LPA_SPEED_2500 4
791 +#define USXGMII_LPA_SPEED_5000 5
792 +#define USXGMII_LPA_DUPLEX BIT(12)
793 +#define USXGMII_LPA_LINK BIT(15)
794 +#define USXGMII_LPA_LATCH BIT(31)
795 +
796 +/* Register to control USXGMII XFI PLL digital */
797 +#define XFI_PLL_DIG_GLB8 0x08
798 +#define RG_XFI_PLL_EN BIT(31)
799 +
800 +/* Register to control USXGMII XFI PLL analog */
801 +#define XFI_PLL_ANA_GLB8 0x108
802 +#define RG_XFI_PLL_ANA_SWWA 0x02283248
803 +
804 /* Infrasys subsystem config registers */
805 #define INFRA_MISC2 0x70c
806 #define CO_QPHY_SEL BIT(0)
807 #define GEPHY_MAC_SEL BIT(1)
808
809 +/* Toprgu subsystem config registers */
810 +#define TOPRGU_SWSYSRST 0x18
811 +#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24)
812 +#define SWSYSRST_XFI_PLL_GRST BIT(16)
813 +#define SWSYSRST_XFI_PEXPT1_GRST BIT(15)
814 +#define SWSYSRST_XFI_PEXPT0_GRST BIT(14)
815 +#define SWSYSRST_XFI1_GRST BIT(13)
816 +#define SWSYSRST_XFI0_GRST BIT(12)
817 +#define SWSYSRST_SGMII1_GRST BIT(2)
818 +#define SWSYSRST_SGMII0_GRST BIT(1)
819 +#define TOPRGU_SWSYSRST_EN 0xFC
820 +
821 /* Top misc registers */
822 +#define TOP_MISC_NETSYS_PCS_MUX 0x84
823 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
824 +#define MUX_G2_USXGMII_SEL BIT(1)
825 +#define MUX_HSGMII1_G1_SEL BIT(0)
826 +
827 #define USB_PHY_SWITCH_REG 0x218
828 #define QPHY_SEL_MASK GENMASK(1, 0)
829 #define SGMII_QPHY_SEL 0x2
830
831 +/* MDIO control */
832 +#define MII_MMD_ACC_CTL_REG 0x0d
833 +#define MII_MMD_ADDR_DATA_REG 0x0e
834 +#define MMD_OP_MODE_DATA BIT(14)
835 +
836 /* MT7628/88 specific stuff */
837 #define MT7628_PDMA_OFFSET 0x0800
838 #define MT7628_SDM_OFFSET 0x0c00
839 @@ -809,13 +926,6 @@ enum mtk_gmac_id {
840 MTK_GMAC_ID_MAX
841 };
842
843 -/* GDM Type */
844 -enum mtk_gdm_type {
845 - MTK_GDM_TYPE = 0,
846 - MTK_XGDM_TYPE,
847 - MTK_GDM_TYPE_MAX
848 -};
849 -
850 enum mtk_tx_buf_type {
851 MTK_TYPE_SKB,
852 MTK_TYPE_XDP_TX,
853 @@ -902,6 +1012,7 @@ enum mkt_eth_capabilities {
854 MTK_TRGMII_BIT,
855 MTK_SGMII_BIT,
856 MTK_USXGMII_BIT,
857 + MTK_2P5GPHY_BIT,
858 MTK_ESW_BIT,
859 MTK_GEPHY_BIT,
860 MTK_MUX_BIT,
861 @@ -922,6 +1033,7 @@ enum mkt_eth_capabilities {
862 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
863 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
864 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
865 + MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
866 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
867 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
868 MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
869 @@ -933,6 +1045,7 @@ enum mkt_eth_capabilities {
870 MTK_ETH_PATH_GMAC1_SGMII_BIT,
871 MTK_ETH_PATH_GMAC2_RGMII_BIT,
872 MTK_ETH_PATH_GMAC2_SGMII_BIT,
873 + MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
874 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
875 MTK_ETH_PATH_GMAC3_SGMII_BIT,
876 MTK_ETH_PATH_GDM1_ESW_BIT,
877 @@ -946,6 +1059,7 @@ enum mkt_eth_capabilities {
878 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
879 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
880 #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
881 +#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
882 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
883 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
884 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
885 @@ -968,6 +1082,8 @@ enum mkt_eth_capabilities {
886 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
887 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
888 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
889 +#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
890 + BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
891 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
892 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
893 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
894 @@ -983,6 +1099,7 @@ enum mkt_eth_capabilities {
895 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
896 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
897 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
898 +#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
899 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
900 #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
901 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
902 @@ -996,6 +1113,7 @@ enum mkt_eth_capabilities {
903 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
904 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
905 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
906 +#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
907 #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
908 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
909 #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
910 @@ -1019,6 +1137,10 @@ enum mkt_eth_capabilities {
911 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
912 MTK_SHARED_SGMII)
913
914 +/* 2: GMAC2 -> XGMII */
915 +#define MTK_MUX_GMAC2_TO_2P5GPHY \
916 + (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
917 +
918 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
919 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
920 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
921 @@ -1077,7 +1199,8 @@ enum mkt_eth_capabilities {
922 MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
923 MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \
924 MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
925 - MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
926 + MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
927 + MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY)
928
929 struct mtk_tx_dma_desc_info {
930 dma_addr_t addr;
931 @@ -1183,6 +1306,22 @@ struct mtk_soc_data {
932
933 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
934
935 +/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
936 + * associated data
937 + * @regmap: The register map pointing at the range used to setup
938 + * USXGMII modes
939 + * @interface: Currently selected interface mode
940 + * @id: The element is used to record the index of PCS
941 + * @pcs: Phylink PCS structure
942 + */
943 +struct mtk_usxgmii_pcs {
944 + struct mtk_eth *eth;
945 + struct regmap *regmap;
946 + phy_interface_t interface;
947 + u8 id;
948 + struct phylink_pcs pcs;
949 +};
950 +
951 /* struct mtk_eth - This is the main datasructure for holding the state
952 * of the driver
953 * @dev: The device pointer
954 @@ -1203,6 +1342,11 @@ struct mtk_soc_data {
955 * @infra: The register map pointing at the range used to setup
956 * SGMII and GePHY path
957 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
958 + * @usxgmii_pll: The register map pointing at the range used to control
959 + * the USXGMII SerDes PLL
960 + * @regmap_pextp: The register map pointing at the range used to setup
961 + * PHYA
962 + * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS
963 * @pctl: The register map pointing at the range used to setup
964 * GMAC port drive/slew values
965 * @dma_refcnt: track how many netdevs are using the DMA engine
966 @@ -1244,7 +1388,11 @@ struct mtk_eth {
967 unsigned long sysclk;
968 struct regmap *ethsys;
969 struct regmap *infra;
970 + struct regmap *toprgu;
971 struct phylink_pcs **sgmii_pcs;
972 + struct regmap *usxgmii_pll;
973 + struct regmap **regmap_pextp;
974 + struct mtk_usxgmii_pcs **usxgmii_pcs;
975 struct regmap *pctl;
976 bool hwlro;
977 refcount_t dma_refcnt;
978 @@ -1400,6 +1548,19 @@ static inline u32 mtk_get_ib2_multicast_
979 return MTK_FOE_IB2_MULTICAST;
980 }
981
982 +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
983 +{
984 + switch (interface) {
985 + case PHY_INTERFACE_MODE_USXGMII:
986 + case PHY_INTERFACE_MODE_10GKR:
987 + case PHY_INTERFACE_MODE_5GBASER:
988 + return true;
989 + break;
990 + default:
991 + return false;
992 + }
993 +}
994 +
995 /* read the hardware status register */
996 void mtk_stats_update_mac(struct mtk_mac *mac);
997
998 @@ -1407,8 +1568,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va
999 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1000
1001 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1002 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
1003 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1004 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1005 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
1006
1007 int mtk_eth_offload_init(struct mtk_eth *eth);
1008 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1009 @@ -1418,5 +1581,20 @@ int mtk_flow_offload_cmd(struct mtk_eth
1010 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
1011 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
1012
1013 +#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
1014 +struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
1015 +int mtk_usxgmii_init(struct mtk_eth *eth);
1016 +int mtk_xfi_pll_enable(struct mtk_eth *eth);
1017 +void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id);
1018 +void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id);
1019 +void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id);
1020 +#else
1021 +static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) { return NULL; }
1022 +static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
1023 +static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; }
1024 +static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { }
1025 +static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { }
1026 +static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { }
1027 +#endif /* NET_MEDIATEK_SOC_USXGMII */
1028
1029 #endif /* MTK_ETH_H */
1030 --- /dev/null
1031 +++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
1032 @@ -0,0 +1,835 @@
1033 +/* SPDX-License-Identifier: GPL-2.0
1034 + *
1035 + * Copyright (c) 2022 MediaTek Inc.
1036 + * Author: Henry Yen <henry.yen@mediatek.com>
1037 + * Daniel Golle <daniel@makrotopia.org>
1038 + */
1039 +
1040 +#include <linux/mfd/syscon.h>
1041 +#include <linux/of.h>
1042 +#include <linux/regmap.h>
1043 +#include "mtk_eth_soc.h"
1044 +
1045 +static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
1046 +{
1047 + return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
1048 +}
1049 +
1050 +static int mtk_xfi_pextp_init(struct mtk_eth *eth)
1051 +{
1052 + struct device *dev = eth->dev;
1053 + struct device_node *r = dev->of_node;
1054 + struct device_node *np;
1055 + int i;
1056 +
1057 + eth->regmap_pextp = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->regmap_pextp), GFP_KERNEL);
1058 + if (!eth->regmap_pextp)
1059 + return -ENOMEM;
1060 +
1061 + for (i = 0; i < eth->soc->num_devs; i++) {
1062 + np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
1063 + if (!np)
1064 + break;
1065 +
1066 + eth->regmap_pextp[i] = syscon_node_to_regmap(np);
1067 + if (IS_ERR(eth->regmap_pextp[i]))
1068 + return PTR_ERR(eth->regmap_pextp[i]);
1069 + }
1070 +
1071 + return 0;
1072 +}
1073 +
1074 +static int mtk_xfi_pll_init(struct mtk_eth *eth)
1075 +{
1076 + struct device_node *r = eth->dev->of_node;
1077 + struct device_node *np;
1078 +
1079 + np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
1080 + if (!np)
1081 + return -1;
1082 +
1083 + eth->usxgmii_pll = syscon_node_to_regmap(np);
1084 + if (IS_ERR(eth->usxgmii_pll))
1085 + return PTR_ERR(eth->usxgmii_pll);
1086 +
1087 + return 0;
1088 +}
1089 +
1090 +static int mtk_toprgu_init(struct mtk_eth *eth)
1091 +{
1092 + struct device_node *r = eth->dev->of_node;
1093 + struct device_node *np;
1094 +
1095 + np = of_parse_phandle(r, "mediatek,toprgu", 0);
1096 + if (!np)
1097 + return -1;
1098 +
1099 + eth->toprgu = syscon_node_to_regmap(np);
1100 + if (IS_ERR(eth->toprgu))
1101 + return PTR_ERR(eth->toprgu);
1102 +
1103 + return 0;
1104 +}
1105 +
1106 +int mtk_xfi_pll_enable(struct mtk_eth *eth)
1107 +{
1108 + u32 val = 0;
1109 +
1110 + if (!eth->usxgmii_pll)
1111 + return -EINVAL;
1112 +
1113 + /* Add software workaround for USXGMII PLL TCL issue */
1114 + regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
1115 +
1116 + regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
1117 + val |= RG_XFI_PLL_EN;
1118 + regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
1119 +
1120 + return 0;
1121 +}
1122 +
1123 +static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
1124 +{
1125 + int xgmii_id = mac_id;
1126 +
1127 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
1128 + switch (mac_id) {
1129 + case MTK_GMAC1_ID:
1130 + case MTK_GMAC2_ID:
1131 + xgmii_id = 1;
1132 + break;
1133 + case MTK_GMAC3_ID:
1134 + xgmii_id = 0;
1135 + break;
1136 + default:
1137 + xgmii_id = -1;
1138 + }
1139 + }
1140 +
1141 + return xgmii_id;
1142 +}
1143 +
1144 +static int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
1145 +{
1146 + int mac_id = xgmii_id;
1147 +
1148 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
1149 + switch (xgmii_id) {
1150 + case 0:
1151 + mac_id = 2;
1152 + break;
1153 + case 1:
1154 + mac_id = 1;
1155 + break;
1156 + default:
1157 + mac_id = -1;
1158 + }
1159 + }
1160 +
1161 + return mac_id;
1162 +}
1163 +
1164 +
1165 +static void mtk_usxgmii_setup_phya_usxgmii(struct mtk_usxgmii_pcs *mpcs)
1166 +{
1167 + struct regmap *pextp;
1168 +
1169 + if (!mpcs->eth)
1170 + return;
1171 +
1172 + pextp = mpcs->eth->regmap_pextp[mpcs->id];
1173 + if (!pextp)
1174 + return;
1175 +
1176 + /* Setup operation mode */
1177 + regmap_write(pextp, 0x9024, 0x00C9071C);
1178 + regmap_write(pextp, 0x2020, 0xAA8585AA);
1179 + regmap_write(pextp, 0x2030, 0x0C020707);
1180 + regmap_write(pextp, 0x2034, 0x0E050F0F);
1181 + regmap_write(pextp, 0x2040, 0x00140032);
1182 + regmap_write(pextp, 0x50F0, 0x00C014AA);
1183 + regmap_write(pextp, 0x50E0, 0x3777C12B);
1184 + regmap_write(pextp, 0x506C, 0x005F9CFF);
1185 + regmap_write(pextp, 0x5070, 0x9D9DFAFA);
1186 + regmap_write(pextp, 0x5074, 0x27273F3F);
1187 + regmap_write(pextp, 0x5078, 0xA7883C68);
1188 + regmap_write(pextp, 0x507C, 0x11661166);
1189 + regmap_write(pextp, 0x5080, 0x0E000AAF);
1190 + regmap_write(pextp, 0x5084, 0x08080D0D);
1191 + regmap_write(pextp, 0x5088, 0x02030909);
1192 + regmap_write(pextp, 0x50E4, 0x0C0C0000);
1193 + regmap_write(pextp, 0x50E8, 0x04040000);
1194 + regmap_write(pextp, 0x50EC, 0x0F0F0C06);
1195 + regmap_write(pextp, 0x50A8, 0x506E8C8C);
1196 + regmap_write(pextp, 0x6004, 0x18190000);
1197 + regmap_write(pextp, 0x00F8, 0x01423342);
1198 + /* Force SGDT_OUT off and select PCS */
1199 + regmap_write(pextp, 0x00F4, 0x80201F20);
1200 + /* Force GLB_CKDET_OUT */
1201 + regmap_write(pextp, 0x0030, 0x00050C00);
1202 + /* Force AEQ on */
1203 + regmap_write(pextp, 0x0070, 0x02002800);
1204 + ndelay(1020);
1205 + /* Setup DA default value */
1206 + regmap_write(pextp, 0x30B0, 0x00000020);
1207 + regmap_write(pextp, 0x3028, 0x00008A01);
1208 + regmap_write(pextp, 0x302C, 0x0000A884);
1209 + regmap_write(pextp, 0x3024, 0x00083002);
1210 + regmap_write(pextp, 0x3010, 0x00022220);
1211 + regmap_write(pextp, 0x5064, 0x0F020A01);
1212 + regmap_write(pextp, 0x50B4, 0x06100600);
1213 + regmap_write(pextp, 0x3048, 0x40704000);
1214 + regmap_write(pextp, 0x3050, 0xA8000000);
1215 + regmap_write(pextp, 0x3054, 0x000000AA);
1216 + regmap_write(pextp, 0x306C, 0x00000F00);
1217 + regmap_write(pextp, 0xA060, 0x00040000);
1218 + regmap_write(pextp, 0x90D0, 0x00000001);
1219 + /* Release reset */
1220 + regmap_write(pextp, 0x0070, 0x0200E800);
1221 + udelay(150);
1222 + /* Switch to P0 */
1223 + regmap_write(pextp, 0x0070, 0x0200C111);
1224 + ndelay(1020);
1225 + regmap_write(pextp, 0x0070, 0x0200C101);
1226 + udelay(15);
1227 + /* Switch to Gen3 */
1228 + regmap_write(pextp, 0x0070, 0x0202C111);
1229 + ndelay(1020);
1230 + regmap_write(pextp, 0x0070, 0x0202C101);
1231 + udelay(100);
1232 + regmap_write(pextp, 0x30B0, 0x00000030);
1233 + regmap_write(pextp, 0x00F4, 0x80201F00);
1234 + regmap_write(pextp, 0x3040, 0x30000000);
1235 + udelay(400);
1236 +}
1237 +
1238 +static void mtk_usxgmii_setup_phya_5gbaser(struct mtk_usxgmii_pcs *mpcs)
1239 +{
1240 + struct regmap *pextp;
1241 +
1242 + if (!mpcs->eth)
1243 + return;
1244 +
1245 + pextp = mpcs->eth->regmap_pextp[mpcs->id];
1246 + if (!pextp)
1247 + return;
1248 +
1249 + /* Setup operation mode */
1250 + regmap_write(pextp, 0x9024, 0x00D9071C);
1251 + regmap_write(pextp, 0x2020, 0xAAA5A5AA);
1252 + regmap_write(pextp, 0x2030, 0x0C020707);
1253 + regmap_write(pextp, 0x2034, 0x0E050F0F);
1254 + regmap_write(pextp, 0x2040, 0x00140032);
1255 + regmap_write(pextp, 0x50F0, 0x00C018AA);
1256 + regmap_write(pextp, 0x50E0, 0x3777812B);
1257 + regmap_write(pextp, 0x506C, 0x005C9CFF);
1258 + regmap_write(pextp, 0x5070, 0x9DFAFAFA);
1259 + regmap_write(pextp, 0x5074, 0x273F3F3F);
1260 + regmap_write(pextp, 0x5078, 0xA8883868);
1261 + regmap_write(pextp, 0x507C, 0x14661466);
1262 + regmap_write(pextp, 0x5080, 0x0E001ABF);
1263 + regmap_write(pextp, 0x5084, 0x080B0D0D);
1264 + regmap_write(pextp, 0x5088, 0x02050909);
1265 + regmap_write(pextp, 0x50E4, 0x0C000000);
1266 + regmap_write(pextp, 0x50E8, 0x04000000);
1267 + regmap_write(pextp, 0x50EC, 0x0F0F0C06);
1268 + regmap_write(pextp, 0x50A8, 0x50808C8C);
1269 + regmap_write(pextp, 0x6004, 0x18000000);
1270 + regmap_write(pextp, 0x00F8, 0x00A132A1);
1271 + /* Force SGDT_OUT off and select PCS */
1272 + regmap_write(pextp, 0x00F4, 0x80201F20);
1273 + /* Force GLB_CKDET_OUT */
1274 + regmap_write(pextp, 0x0030, 0x00050C00);
1275 + /* Force AEQ on */
1276 + regmap_write(pextp, 0x0070, 0x02002800);
1277 + ndelay(1020);
1278 + /* Setup DA default value */
1279 + regmap_write(pextp, 0x30B0, 0x00000020);
1280 + regmap_write(pextp, 0x3028, 0x00008A01);
1281 + regmap_write(pextp, 0x302C, 0x0000A884);
1282 + regmap_write(pextp, 0x3024, 0x00083002);
1283 + regmap_write(pextp, 0x3010, 0x00022220);
1284 + regmap_write(pextp, 0x5064, 0x0F020A01);
1285 + regmap_write(pextp, 0x50B4, 0x06100600);
1286 + regmap_write(pextp, 0x3048, 0x40704000);
1287 + regmap_write(pextp, 0x3050, 0xA8000000);
1288 + regmap_write(pextp, 0x3054, 0x000000AA);
1289 + regmap_write(pextp, 0x306C, 0x00000F00);
1290 + regmap_write(pextp, 0xA060, 0x00040000);
1291 + regmap_write(pextp, 0x90D0, 0x00000003);
1292 + /* Release reset */
1293 + regmap_write(pextp, 0x0070, 0x0200E800);
1294 + udelay(150);
1295 + /* Switch to P0 */
1296 + regmap_write(pextp, 0x0070, 0x0200C111);
1297 + ndelay(1020);
1298 + regmap_write(pextp, 0x0070, 0x0200C101);
1299 + udelay(15);
1300 + /* Switch to Gen3 */
1301 + regmap_write(pextp, 0x0070, 0x0202C111);
1302 + ndelay(1020);
1303 + regmap_write(pextp, 0x0070, 0x0202C101);
1304 + udelay(100);
1305 + regmap_write(pextp, 0x30B0, 0x00000030);
1306 + regmap_write(pextp, 0x00F4, 0x80201F00);
1307 + regmap_write(pextp, 0x3040, 0x30000000);
1308 + udelay(400);
1309 +}
1310 +
1311 +static void mtk_usxgmii_setup_phya_10gbaser(struct mtk_usxgmii_pcs *mpcs)
1312 +{
1313 + struct regmap *pextp;
1314 +
1315 + if (!mpcs->eth)
1316 + return;
1317 +
1318 + pextp = mpcs->eth->regmap_pextp[mpcs->id];
1319 + if (!pextp)
1320 + return;
1321 +
1322 + /* Setup operation mode */
1323 + regmap_write(pextp, 0x9024, 0x00C9071C);
1324 + regmap_write(pextp, 0x2020, 0xAA8585AA);
1325 + regmap_write(pextp, 0x2030, 0x0C020707);
1326 + regmap_write(pextp, 0x2034, 0x0E050F0F);
1327 + regmap_write(pextp, 0x2040, 0x00140032);
1328 + regmap_write(pextp, 0x50F0, 0x00C014AA);
1329 + regmap_write(pextp, 0x50E0, 0x3777C12B);
1330 + regmap_write(pextp, 0x506C, 0x005F9CFF);
1331 + regmap_write(pextp, 0x5070, 0x9D9DFAFA);
1332 + regmap_write(pextp, 0x5074, 0x27273F3F);
1333 + regmap_write(pextp, 0x5078, 0xA7883C68);
1334 + regmap_write(pextp, 0x507C, 0x11661166);
1335 + regmap_write(pextp, 0x5080, 0x0E000AAF);
1336 + regmap_write(pextp, 0x5084, 0x08080D0D);
1337 + regmap_write(pextp, 0x5088, 0x02030909);
1338 + regmap_write(pextp, 0x50E4, 0x0C0C0000);
1339 + regmap_write(pextp, 0x50E8, 0x04040000);
1340 + regmap_write(pextp, 0x50EC, 0x0F0F0C06);
1341 + regmap_write(pextp, 0x50A8, 0x506E8C8C);
1342 + regmap_write(pextp, 0x6004, 0x18190000);
1343 + regmap_write(pextp, 0x00F8, 0x01423342);
1344 + /* Force SGDT_OUT off and select PCS */
1345 + regmap_write(pextp, 0x00F4, 0x80201F20);
1346 + /* Force GLB_CKDET_OUT */
1347 + regmap_write(pextp, 0x0030, 0x00050C00);
1348 + /* Force AEQ on */
1349 + regmap_write(pextp, 0x0070, 0x02002800);
1350 + ndelay(1020);
1351 + /* Setup DA default value */
1352 + regmap_write(pextp, 0x30B0, 0x00000020);
1353 + regmap_write(pextp, 0x3028, 0x00008A01);
1354 + regmap_write(pextp, 0x302C, 0x0000A884);
1355 + regmap_write(pextp, 0x3024, 0x00083002);
1356 + regmap_write(pextp, 0x3010, 0x00022220);
1357 + regmap_write(pextp, 0x5064, 0x0F020A01);
1358 + regmap_write(pextp, 0x50B4, 0x06100600);
1359 + regmap_write(pextp, 0x3048, 0x47684100);
1360 + regmap_write(pextp, 0x3050, 0x00000000);
1361 + regmap_write(pextp, 0x3054, 0x00000000);
1362 + regmap_write(pextp, 0x306C, 0x00000F00);
1363 + if (mpcs->id == 0)
1364 + regmap_write(pextp, 0xA008, 0x0007B400);
1365 +
1366 + regmap_write(pextp, 0xA060, 0x00040000);
1367 + regmap_write(pextp, 0x90D0, 0x00000001);
1368 + /* Release reset */
1369 + regmap_write(pextp, 0x0070, 0x0200E800);
1370 + udelay(150);
1371 + /* Switch to P0 */
1372 + regmap_write(pextp, 0x0070, 0x0200C111);
1373 + ndelay(1020);
1374 + regmap_write(pextp, 0x0070, 0x0200C101);
1375 + udelay(15);
1376 + /* Switch to Gen3 */
1377 + regmap_write(pextp, 0x0070, 0x0202C111);
1378 + ndelay(1020);
1379 + regmap_write(pextp, 0x0070, 0x0202C101);
1380 + udelay(100);
1381 + regmap_write(pextp, 0x30B0, 0x00000030);
1382 + regmap_write(pextp, 0x00F4, 0x80201F00);
1383 + regmap_write(pextp, 0x3040, 0x30000000);
1384 + udelay(400);
1385 +}
1386 +
1387 +void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id)
1388 +{
1389 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1390 + struct regmap *pextp;
1391 +
1392 + if (id >= eth->soc->num_devs)
1393 + return;
1394 +
1395 + pextp = eth->regmap_pextp[id];
1396 + if (!pextp)
1397 + return;
1398 +
1399 + /* Setup operation mode */
1400 + regmap_write(pextp, 0x9024, 0x00D9071C);
1401 + regmap_write(pextp, 0x2020, 0xAA8585AA);
1402 + regmap_write(pextp, 0x2030, 0x0C020207);
1403 + regmap_write(pextp, 0x2034, 0x0E05050F);
1404 + regmap_write(pextp, 0x2040, 0x00200032);
1405 + regmap_write(pextp, 0x50F0, 0x00C014BA);
1406 + regmap_write(pextp, 0x50E0, 0x3777C12B);
1407 + regmap_write(pextp, 0x506C, 0x005F9CFF);
1408 + regmap_write(pextp, 0x5070, 0x9D9DFAFA);
1409 + regmap_write(pextp, 0x5074, 0x27273F3F);
1410 + regmap_write(pextp, 0x5078, 0xA7883C68);
1411 + regmap_write(pextp, 0x507C, 0x11661166);
1412 + regmap_write(pextp, 0x5080, 0x0E000EAF);
1413 + regmap_write(pextp, 0x5084, 0x08080E0D);
1414 + regmap_write(pextp, 0x5088, 0x02030B09);
1415 + regmap_write(pextp, 0x50E4, 0x0C0C0000);
1416 + regmap_write(pextp, 0x50E8, 0x04040000);
1417 + regmap_write(pextp, 0x50EC, 0x0F0F0606);
1418 + regmap_write(pextp, 0x50A8, 0x506E8C8C);
1419 + regmap_write(pextp, 0x6004, 0x18190000);
1420 + regmap_write(pextp, 0x00F8, 0x00FA32FA);
1421 + /* Force SGDT_OUT off and select PCS */
1422 + regmap_write(pextp, 0x00F4, 0x80201F21);
1423 + /* Force GLB_CKDET_OUT */
1424 + regmap_write(pextp, 0x0030, 0x00050C00);
1425 + /* Force AEQ on */
1426 + regmap_write(pextp, 0x0070, 0x02002800);
1427 + ndelay(1020);
1428 + /* Setup DA default value */
1429 + regmap_write(pextp, 0x30B0, 0x00000020);
1430 + regmap_write(pextp, 0x3028, 0x00008A01);
1431 + regmap_write(pextp, 0x302C, 0x0000A884);
1432 + regmap_write(pextp, 0x3024, 0x00083002);
1433 + regmap_write(pextp, 0x3010, 0x00011110);
1434 + regmap_write(pextp, 0x3048, 0x40704000);
1435 + regmap_write(pextp, 0x3064, 0x0000C000);
1436 + regmap_write(pextp, 0x3050, 0xA8000000);
1437 + regmap_write(pextp, 0x3054, 0x000000AA);
1438 + regmap_write(pextp, 0x306C, 0x20200F00);
1439 + regmap_write(pextp, 0xA060, 0x00050000);
1440 + regmap_write(pextp, 0x90D0, 0x00000007);
1441 + /* Release reset */
1442 + regmap_write(pextp, 0x0070, 0x0200E800);
1443 + udelay(150);
1444 + /* Switch to P0 */
1445 + regmap_write(pextp, 0x0070, 0x0200C111);
1446 + ndelay(1020);
1447 + regmap_write(pextp, 0x0070, 0x0200C101);
1448 + udelay(15);
1449 + /* Switch to Gen2 */
1450 + regmap_write(pextp, 0x0070, 0x0201C111);
1451 + ndelay(1020);
1452 + regmap_write(pextp, 0x0070, 0x0201C101);
1453 + udelay(100);
1454 + regmap_write(pextp, 0x30B0, 0x00000030);
1455 + regmap_write(pextp, 0x00F4, 0x80201F01);
1456 + regmap_write(pextp, 0x3040, 0x30000000);
1457 + udelay(400);
1458 +}
1459 +
1460 +void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id)
1461 +{
1462 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1463 + struct regmap *pextp;
1464 +
1465 + if (id >= eth->soc->num_devs)
1466 + return;
1467 +
1468 + pextp = eth->regmap_pextp[id];
1469 + if (!pextp)
1470 + return;
1471 +
1472 + /* Setup operation mode */
1473 + regmap_write(pextp, 0x9024, 0x00D9071C);
1474 + regmap_write(pextp, 0x2020, 0xAA8585AA);
1475 + regmap_write(pextp, 0x2030, 0x0C020707);
1476 + regmap_write(pextp, 0x2034, 0x0E050F0F);
1477 + regmap_write(pextp, 0x2040, 0x00140032);
1478 + regmap_write(pextp, 0x50F0, 0x00C014AA);
1479 + regmap_write(pextp, 0x50E0, 0x3777C12B);
1480 + regmap_write(pextp, 0x506C, 0x005F9CFF);
1481 + regmap_write(pextp, 0x5070, 0x9D9DFAFA);
1482 + regmap_write(pextp, 0x5074, 0x27273F3F);
1483 + regmap_write(pextp, 0x5078, 0xA7883C68);
1484 + regmap_write(pextp, 0x507C, 0x11661166);
1485 + regmap_write(pextp, 0x5080, 0x0E000AAF);
1486 + regmap_write(pextp, 0x5084, 0x08080D0D);
1487 + regmap_write(pextp, 0x5088, 0x02030909);
1488 + regmap_write(pextp, 0x50E4, 0x0C0C0000);
1489 + regmap_write(pextp, 0x50E8, 0x04040000);
1490 + regmap_write(pextp, 0x50EC, 0x0F0F0C06);
1491 + regmap_write(pextp, 0x50A8, 0x506E8C8C);
1492 + regmap_write(pextp, 0x6004, 0x18190000);
1493 + regmap_write(pextp, 0x00F8, 0x009C329C);
1494 + /* Force SGDT_OUT off and select PCS */
1495 + regmap_write(pextp, 0x00F4, 0x80201F21);
1496 + /* Force GLB_CKDET_OUT */
1497 + regmap_write(pextp, 0x0030, 0x00050C00);
1498 + /* Force AEQ on */
1499 + regmap_write(pextp, 0x0070, 0x02002800);
1500 + ndelay(1020);
1501 + /* Setup DA default value */
1502 + regmap_write(pextp, 0x30B0, 0x00000020);
1503 + regmap_write(pextp, 0x3028, 0x00008A01);
1504 + regmap_write(pextp, 0x302C, 0x0000A884);
1505 + regmap_write(pextp, 0x3024, 0x00083002);
1506 + regmap_write(pextp, 0x3010, 0x00011110);
1507 + regmap_write(pextp, 0x3048, 0x40704000);
1508 + regmap_write(pextp, 0x3050, 0xA8000000);
1509 + regmap_write(pextp, 0x3054, 0x000000AA);
1510 + regmap_write(pextp, 0x306C, 0x22000F00);
1511 + regmap_write(pextp, 0xA060, 0x00050000);
1512 + regmap_write(pextp, 0x90D0, 0x00000005);
1513 + /* Release reset */
1514 + regmap_write(pextp, 0x0070, 0x0200E800);
1515 + udelay(150);
1516 + /* Switch to P0 */
1517 + regmap_write(pextp, 0x0070, 0x0200C111);
1518 + ndelay(1020);
1519 + regmap_write(pextp, 0x0070, 0x0200C101);
1520 + udelay(15);
1521 + /* Switch to Gen2 */
1522 + regmap_write(pextp, 0x0070, 0x0201C111);
1523 + ndelay(1020);
1524 + regmap_write(pextp, 0x0070, 0x0201C101);
1525 + udelay(100);
1526 + regmap_write(pextp, 0x30B0, 0x00000030);
1527 + regmap_write(pextp, 0x00F4, 0x80201F01);
1528 + regmap_write(pextp, 0x3040, 0x30000000);
1529 + udelay(400);
1530 +}
1531 +
1532 +static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
1533 +{
1534 + u32 val = 0;
1535 +
1536 + if (id >= eth->soc->num_devs || !eth->toprgu)
1537 + return;
1538 +
1539 + switch (id) {
1540 + case 0:
1541 + /* Enable software reset */
1542 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1543 + val |= SWSYSRST_XFI_PEXPT0_GRST |
1544 + SWSYSRST_XFI0_GRST;
1545 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1546 +
1547 + /* Assert USXGMII reset */
1548 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1549 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
1550 + SWSYSRST_XFI_PEXPT0_GRST |
1551 + SWSYSRST_XFI0_GRST;
1552 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1553 +
1554 + udelay(100);
1555 +
1556 + /* De-assert USXGMII reset */
1557 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1558 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
1559 + val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
1560 + SWSYSRST_XFI0_GRST);
1561 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1562 +
1563 + /* Disable software reset */
1564 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1565 + val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
1566 + SWSYSRST_XFI0_GRST);
1567 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1568 + break;
1569 + case 1:
1570 + /* Enable software reset */
1571 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1572 + val |= SWSYSRST_XFI_PEXPT1_GRST |
1573 + SWSYSRST_XFI1_GRST;
1574 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1575 +
1576 + /* Assert USXGMII reset */
1577 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1578 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
1579 + SWSYSRST_XFI_PEXPT1_GRST |
1580 + SWSYSRST_XFI1_GRST;
1581 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1582 +
1583 + udelay(100);
1584 +
1585 + /* De-assert USXGMII reset */
1586 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1587 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
1588 + val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
1589 + SWSYSRST_XFI1_GRST);
1590 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1591 +
1592 + /* Disable software reset */
1593 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1594 + val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
1595 + SWSYSRST_XFI1_GRST);
1596 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1597 + break;
1598 + }
1599 +
1600 + mdelay(10);
1601 +}
1602 +
1603 +void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id)
1604 +{
1605 + u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
1606 +
1607 + mtk_usxgmii_reset(eth, xgmii_id);
1608 +}
1609 +
1610 +
1611 +static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
1612 + phy_interface_t interface,
1613 + const unsigned long *advertising,
1614 + bool permit_pause_to_mac)
1615 +{
1616 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1617 + struct mtk_eth *eth = mpcs->eth;
1618 + unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
1619 + bool mode_changed = false;
1620 +
1621 + if (interface == PHY_INTERFACE_MODE_USXGMII) {
1622 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) |
1623 + USXGMII_AN_ENABLE;
1624 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
1625 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
1626 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
1627 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
1628 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
1629 + } else if (interface == PHY_INTERFACE_MODE_10GKR) {
1630 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
1631 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
1632 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
1633 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
1634 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
1635 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
1636 + adapt_mode = USXGMII_RATE_UPDATE_MODE;
1637 + } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
1638 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
1639 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
1640 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
1641 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
1642 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
1643 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
1644 + adapt_mode = USXGMII_RATE_UPDATE_MODE;
1645 + } else
1646 + return -EINVAL;
1647 +
1648 + adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
1649 +
1650 + if (mpcs->interface != interface) {
1651 + mpcs->interface = interface;
1652 + mode_changed = true;
1653 + }
1654 +
1655 + mtk_xfi_pll_enable(eth);
1656 + mtk_usxgmii_reset(eth, mpcs->id);
1657 +
1658 + /* Setup USXGMII AN ctrl */
1659 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
1660 + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
1661 + an_ctrl);
1662 +
1663 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
1664 + USXGMII_LINK_TIMER_IDLE_DETECT |
1665 + USXGMII_LINK_TIMER_COMP_ACK_DETECT |
1666 + USXGMII_LINK_TIMER_AN_RESTART,
1667 + link_timer);
1668 +
1669 + /* Gated MAC CK */
1670 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1671 + USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
1672 +
1673 + /* Enable interface force mode */
1674 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1675 + USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
1676 +
1677 + /* Setup USXGMII adapt mode */
1678 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1679 + USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
1680 + adapt_mode);
1681 +
1682 + /* Setup USXGMII speed */
1683 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1684 + USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
1685 + xfi_mode);
1686 +
1687 + udelay(1);
1688 +
1689 + /* Un-gated MAC CK */
1690 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1691 + USXGMII_MAC_CK_GATED, 0);
1692 +
1693 + udelay(1);
1694 +
1695 + /* Disable interface force mode for the AN mode */
1696 + if (an_ctrl & USXGMII_AN_ENABLE)
1697 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1698 + USXGMII_IF_FORCE_EN, 0);
1699 +
1700 + /* Setup USXGMIISYS with the determined property */
1701 + if (interface == PHY_INTERFACE_MODE_USXGMII)
1702 + mtk_usxgmii_setup_phya_usxgmii(mpcs);
1703 + else if (interface == PHY_INTERFACE_MODE_10GKR)
1704 + mtk_usxgmii_setup_phya_10gbaser(mpcs);
1705 + else if (interface == PHY_INTERFACE_MODE_5GBASER)
1706 + mtk_usxgmii_setup_phya_5gbaser(mpcs);
1707 +
1708 + return mode_changed;
1709 +}
1710 +
1711 +static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
1712 + struct phylink_link_state *state)
1713 +{
1714 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1715 + struct mtk_eth *eth = mpcs->eth;
1716 + struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
1717 + u32 val = 0;
1718 +
1719 + regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
1720 + if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
1721 + /* Refresh LPA by inverting LPA_LATCH */
1722 + regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
1723 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
1724 + USXGMII_LPA_LATCH,
1725 + !(val & USXGMII_LPA_LATCH));
1726 +
1727 + regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
1728 +
1729 + state->interface = mpcs->interface;
1730 + state->link = FIELD_GET(USXGMII_LPA_LINK, val);
1731 + state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val);
1732 +
1733 + switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) {
1734 + case USXGMII_LPA_SPEED_10:
1735 + state->speed = SPEED_10;
1736 + break;
1737 + case USXGMII_LPA_SPEED_100:
1738 + state->speed = SPEED_100;
1739 + break;
1740 + case USXGMII_LPA_SPEED_1000:
1741 + state->speed = SPEED_1000;
1742 + break;
1743 + case USXGMII_LPA_SPEED_2500:
1744 + state->speed = SPEED_2500;
1745 + break;
1746 + case USXGMII_LPA_SPEED_5000:
1747 + state->speed = SPEED_5000;
1748 + break;
1749 + case USXGMII_LPA_SPEED_10000:
1750 + state->speed = SPEED_10000;
1751 + break;
1752 + }
1753 + } else {
1754 + val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
1755 +
1756 + if (mac->id == MTK_GMAC2_ID)
1757 + val = val >> 16;
1758 +
1759 + switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
1760 + case 0:
1761 + state->speed = SPEED_10000;
1762 + break;
1763 + case 1:
1764 + state->speed = SPEED_5000;
1765 + break;
1766 + case 2:
1767 + state->speed = SPEED_2500;
1768 + break;
1769 + case 3:
1770 + state->speed = SPEED_1000;
1771 + break;
1772 + }
1773 +
1774 + state->interface = mpcs->interface;
1775 + state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
1776 + state->duplex = DUPLEX_FULL;
1777 + }
1778 +
1779 + if (state->link == 0)
1780 + mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND,
1781 + state->interface, NULL, false);
1782 +}
1783 +
1784 +static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
1785 +{
1786 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1787 + unsigned int val = 0;
1788 +
1789 + if (!mpcs->regmap)
1790 + return;
1791 +
1792 + regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
1793 + val |= USXGMII_AN_RESTART;
1794 + regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
1795 +}
1796 +
1797 +static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
1798 + phy_interface_t interface,
1799 + int speed, int duplex)
1800 +{
1801 + /* Reconfiguring USXGMII to ensure the quality of the RX signal
1802 + * after the line side link up.
1803 + */
1804 + mtk_usxgmii_pcs_config(pcs, mode,
1805 + interface, NULL, false);
1806 +}
1807 +
1808 +static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
1809 + .pcs_config = mtk_usxgmii_pcs_config,
1810 + .pcs_get_state = mtk_usxgmii_pcs_get_state,
1811 + .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
1812 + .pcs_link_up = mtk_usxgmii_pcs_link_up,
1813 +};
1814 +
1815 +int mtk_usxgmii_init(struct mtk_eth *eth)
1816 +{
1817 + struct device_node *r = eth->dev->of_node;
1818 + struct device *dev = eth->dev;
1819 + struct device_node *np;
1820 + int i, ret;
1821 +
1822 + eth->usxgmii_pcs = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->usxgmii_pcs), GFP_KERNEL);
1823 + if (!eth->usxgmii_pcs)
1824 + return -ENOMEM;
1825 +
1826 + for (i = 0; i < eth->soc->num_devs; i++) {
1827 + np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
1828 + if (!np)
1829 + break;
1830 +
1831 + eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs), GFP_KERNEL);
1832 + if (!eth->usxgmii_pcs[i])
1833 + return -ENOMEM;
1834 +
1835 + eth->usxgmii_pcs[i]->id = i;
1836 + eth->usxgmii_pcs[i]->eth = eth;
1837 + eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
1838 + if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
1839 + return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
1840 +
1841 + eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
1842 + eth->usxgmii_pcs[i]->pcs.poll = true;
1843 + eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
1844 +
1845 + of_node_put(np);
1846 + }
1847 +
1848 + ret = mtk_xfi_pextp_init(eth);
1849 + if (ret)
1850 + return ret;
1851 +
1852 + ret = mtk_xfi_pll_init(eth);
1853 + if (ret)
1854 + return ret;
1855 +
1856 + return mtk_toprgu_init(eth);
1857 +}
1858 +
1859 +struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
1860 +{
1861 + u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
1862 +
1863 + if (!eth->usxgmii_pcs[xgmii_id]->regmap)
1864 + return NULL;
1865 +
1866 + return &eth->usxgmii_pcs[xgmii_id]->pcs;
1867 +}
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