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kernel: fix busy wait loop in mediatek PPE code
[openwrt/openwrt.git] / target / linux / generic / pending-5.4 / 770-15-net-ethernet-mediatek-mtk_eth_soc-add-support-for-in.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sun, 11 Oct 2020 22:23:08 +0200
3 Subject: [PATCH] ethernet: mediatek: mtk_eth_soc: add support for
4 initializing the PPE
5
6 The PPE (packet processing engine) is used to offload NAT/routed or even
7 bridged flows. This patch brings up the PPE and uses it to get a packet
8 hash. It also contains some functionality that will be used to bring up
9 flow offloading later
10
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 ---
13 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
14 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h
15 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h
16
17 --- a/drivers/net/ethernet/mediatek/Makefile
18 +++ b/drivers/net/ethernet/mediatek/Makefile
19 @@ -4,4 +4,4 @@
20 #
21
22 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
23 -mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
24 +mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o
25 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
26 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
27 @@ -2280,12 +2280,17 @@ static int mtk_open(struct net_device *d
28
29 /* we run 2 netdevs on the same dma ring so we only bring it up once */
30 if (!refcount_read(&eth->dma_refcnt)) {
31 - int err = mtk_start_dma(eth);
32 + u32 gdm_config = MTK_GDMA_TO_PDMA;
33 + int err;
34
35 + err = mtk_start_dma(eth);
36 if (err)
37 return err;
38
39 - mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
40 + if (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)
41 + gdm_config = MTK_GDMA_TO_PPE;
42 +
43 + mtk_gdm_config(eth, gdm_config);
44
45 napi_enable(&eth->tx_napi);
46 napi_enable(&eth->rx_napi);
47 @@ -2355,6 +2360,9 @@ static int mtk_stop(struct net_device *d
48
49 mtk_dma_free(eth);
50
51 + if (eth->soc->offload_version)
52 + mtk_ppe_stop(&eth->ppe);
53 +
54 return 0;
55 }
56
57 @@ -3144,6 +3152,13 @@ static int mtk_probe(struct platform_dev
58 goto err_free_dev;
59 }
60
61 + if (eth->soc->offload_version) {
62 + err = mtk_ppe_init(&eth->ppe, eth->dev,
63 + eth->base + MTK_ETH_PPE_BASE, 2);
64 + if (err)
65 + goto err_free_dev;
66 + }
67 +
68 for (i = 0; i < MTK_MAX_DEVS; i++) {
69 if (!eth->netdev[i])
70 continue;
71 @@ -3218,6 +3233,7 @@ static const struct mtk_soc_data mt7621_
72 .hw_features = MTK_HW_FEATURES,
73 .required_clks = MT7621_CLKS_BITMAP,
74 .required_pctl = false,
75 + .offload_version = 2,
76 };
77
78 static const struct mtk_soc_data mt7622_data = {
79 @@ -3226,6 +3242,7 @@ static const struct mtk_soc_data mt7622_
80 .hw_features = MTK_HW_FEATURES,
81 .required_clks = MT7622_CLKS_BITMAP,
82 .required_pctl = false,
83 + .offload_version = 2,
84 };
85
86 static const struct mtk_soc_data mt7623_data = {
87 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
88 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
89 @@ -16,6 +16,7 @@
90 #include <linux/refcount.h>
91 #include <linux/phylink.h>
92 #include <linux/dim.h>
93 +#include "mtk_ppe.h"
94
95 #define MTK_QDMA_PAGE_SIZE 2048
96 #define MTK_MAX_RX_LENGTH 1536
97 @@ -87,6 +88,7 @@
98 #define MTK_GDMA_TCS_EN BIT(21)
99 #define MTK_GDMA_UCS_EN BIT(20)
100 #define MTK_GDMA_TO_PDMA 0x0
101 +#define MTK_GDMA_TO_PPE 0x4444
102 #define MTK_GDMA_DROP_ALL 0x7777
103
104 /* Unicast Filter MAC Address Register - Low */
105 @@ -308,6 +310,12 @@
106 #define RX_DMA_VID(_x) ((_x) & 0xfff)
107
108 /* QDMA descriptor rxd4 */
109 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
110 +#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
111 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
112 +#define MTK_RXD4_ALG GENMASK(31, 22)
113 +
114 +/* QDMA descriptor rxd4 */
115 #define RX_DMA_L4_VALID BIT(24)
116 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
117 #define RX_DMA_FPORT_SHIFT 19
118 @@ -807,6 +815,7 @@ struct mtk_soc_data {
119 u32 caps;
120 u32 required_clks;
121 bool required_pctl;
122 + u8 offload_version;
123 netdev_features_t hw_features;
124 };
125
126 @@ -918,6 +927,8 @@ struct mtk_eth {
127 u32 tx_int_status_reg;
128 u32 rx_dma_l4_valid;
129 int ip_align;
130 +
131 + struct mtk_ppe ppe;
132 };
133
134 /* struct mtk_mac - the structure that holds the info about the MACs of the
135 --- /dev/null
136 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
137 @@ -0,0 +1,497 @@
138 +// SPDX-License-Identifier: GPL-2.0-only
139 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
140 +
141 +#include <linux/kernel.h>
142 +#include <linux/jiffies.h>
143 +#include <linux/delay.h>
144 +#include <linux/io.h>
145 +#include <linux/etherdevice.h>
146 +#include <linux/platform_device.h>
147 +#include "mtk_ppe.h"
148 +#include "mtk_ppe_regs.h"
149 +
150 +static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)
151 +{
152 + writel(val, ppe->base + reg);
153 +}
154 +
155 +static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)
156 +{
157 + return readl(ppe->base + reg);
158 +}
159 +
160 +static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)
161 +{
162 + u32 val;
163 +
164 + val = ppe_r32(ppe, reg);
165 + val &= ~mask;
166 + val |= set;
167 + ppe_w32(ppe, reg, val);
168 +
169 + return val;
170 +}
171 +
172 +static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)
173 +{
174 + return ppe_m32(ppe, reg, 0, val);
175 +}
176 +
177 +static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)
178 +{
179 + return ppe_m32(ppe, reg, val, 0);
180 +}
181 +
182 +static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)
183 +{
184 + unsigned long timeout = jiffies + HZ;
185 +
186 + while (time_is_after_jiffies(timeout)) {
187 + if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))
188 + return 0;
189 +
190 + usleep_range(10, 20);
191 + }
192 +
193 + dev_err(ppe->dev, "PPE table busy");
194 +
195 + return -ETIMEDOUT;
196 +}
197 +
198 +static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
199 +{
200 + ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
201 + ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
202 +}
203 +
204 +static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)
205 +{
206 + mtk_ppe_cache_clear(ppe);
207 +
208 + ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,
209 + enable * MTK_PPE_CACHE_CTL_EN);
210 +}
211 +
212 +static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
213 +{
214 + u32 hv1, hv2, hv3;
215 + u32 hash;
216 +
217 + switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {
218 + case MTK_PPE_PKT_TYPE_BRIDGE:
219 + hv1 = e->bridge.src_mac_lo;
220 + hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);
221 + hv2 = e->bridge.src_mac_hi >> 16;
222 + hv2 ^= e->bridge.dest_mac_lo;
223 + hv3 = e->bridge.dest_mac_hi;
224 + break;
225 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
226 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
227 + hv1 = e->ipv4.orig.ports;
228 + hv2 = e->ipv4.orig.dest_ip;
229 + hv3 = e->ipv4.orig.src_ip;
230 + break;
231 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
232 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
233 + hv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3];
234 + hv1 ^= e->ipv6.ports;
235 +
236 + hv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2];
237 + hv2 ^= e->ipv6.dest_ip[0];
238 +
239 + hv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1];
240 + hv3 ^= e->ipv6.src_ip[0];
241 + break;
242 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
243 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
244 + default:
245 + WARN_ON_ONCE(1);
246 + return MTK_PPE_HASH_MASK;
247 + }
248 +
249 + hash = (hv1 & hv2) | ((~hv1) & hv3);
250 + hash = (hash >> 24) | ((hash & 0xffffff) << 8);
251 + hash ^= hv1 ^ hv2 ^ hv3;
252 + hash ^= hash >> 16;
253 + hash <<= 1;
254 + hash &= MTK_PPE_ENTRIES - 1;
255 +
256 + return hash;
257 +}
258 +
259 +static inline struct mtk_foe_mac_info *
260 +mtk_foe_entry_l2(struct mtk_foe_entry *entry)
261 +{
262 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
263 +
264 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
265 + return &entry->ipv6.l2;
266 +
267 + return &entry->ipv4.l2;
268 +}
269 +
270 +static inline u32 *
271 +mtk_foe_entry_ib2(struct mtk_foe_entry *entry)
272 +{
273 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
274 +
275 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
276 + return &entry->ipv6.ib2;
277 +
278 + return &entry->ipv4.ib2;
279 +}
280 +
281 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
282 + u8 pse_port, u8 *src_mac, u8 *dest_mac)
283 +{
284 + struct mtk_foe_mac_info *l2;
285 + u32 ports_pad, val;
286 +
287 + memset(entry, 0, sizeof(*entry));
288 +
289 + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
290 + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) |
291 + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
292 + MTK_FOE_IB1_BIND_TTL |
293 + MTK_FOE_IB1_BIND_CACHE |
294 + MTK_FOE_IB1_BIND_KEEPALIVE;
295 + entry->ib1 = val;
296 +
297 + val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
298 + FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |
299 + FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);
300 +
301 + if (is_multicast_ether_addr(dest_mac))
302 + val |= MTK_FOE_IB2_MULTICAST;
303 +
304 + ports_pad = 0xa5a5a500 | (l4proto & 0xff);
305 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
306 + entry->ipv4.orig.ports = ports_pad;
307 + if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
308 + entry->ipv6.ports = ports_pad;
309 +
310 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
311 + entry->ipv6.ib2 = val;
312 + l2 = &entry->ipv6.l2;
313 + } else {
314 + entry->ipv4.ib2 = val;
315 + l2 = &entry->ipv4.l2;
316 + }
317 +
318 + l2->dest_mac_hi = get_unaligned_be32(dest_mac);
319 + l2->dest_mac_lo = get_unaligned_be16(dest_mac + 4);
320 + l2->src_mac_hi = get_unaligned_be32(src_mac);
321 + l2->src_mac_lo = get_unaligned_be16(src_mac + 4);
322 +
323 + if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
324 + l2->etype = ETH_P_IPV6;
325 + else
326 + l2->etype = ETH_P_IP;
327 +
328 + return 0;
329 +}
330 +
331 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress,
332 + __be32 src_addr, __be16 src_port,
333 + __be32 dest_addr, __be16 dest_port)
334 +{
335 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
336 + struct mtk_ipv4_tuple *t;
337 +
338 + switch (type) {
339 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
340 + if (egress) {
341 + t = &entry->ipv4.new;
342 + break;
343 + }
344 + fallthrough;
345 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
346 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
347 + t = &entry->ipv4.orig;
348 + break;
349 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
350 + entry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr);
351 + entry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr);
352 + return 0;
353 + default:
354 + WARN_ON_ONCE(1);
355 + return -EINVAL;
356 + }
357 +
358 + t->src_ip = be32_to_cpu(src_addr);
359 + t->dest_ip = be32_to_cpu(dest_addr);
360 +
361 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
362 + return 0;
363 +
364 + t->src_port = be16_to_cpu(src_port);
365 + t->dest_port = be16_to_cpu(dest_port);
366 +
367 + return 0;
368 +}
369 +
370 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
371 + __be32 *src_addr, __be16 src_port,
372 + __be32 *dest_addr, __be16 dest_port)
373 +{
374 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
375 + u32 *src, *dest;
376 + int i;
377 +
378 + switch (type) {
379 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
380 + src = entry->dslite.tunnel_src_ip;
381 + dest = entry->dslite.tunnel_dest_ip;
382 + break;
383 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
384 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
385 + entry->ipv6.src_port = be16_to_cpu(src_port);
386 + entry->ipv6.dest_port = be16_to_cpu(dest_port);
387 + fallthrough;
388 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
389 + src = entry->ipv6.src_ip;
390 + dest = entry->ipv6.dest_ip;
391 + break;
392 + default:
393 + WARN_ON_ONCE(1);
394 + return -EINVAL;
395 + };
396 +
397 + for (i = 0; i < 4; i++)
398 + src[i] = be32_to_cpu(src_addr[i]);
399 + for (i = 0; i < 4; i++)
400 + dest[i] = be32_to_cpu(dest_addr[i]);
401 +
402 + return 0;
403 +}
404 +
405 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port)
406 +{
407 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
408 +
409 + l2->etype = BIT(port);
410 +
411 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER))
412 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
413 + else
414 + l2->etype |= BIT(8);
415 +
416 + entry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG;
417 +
418 + return 0;
419 +}
420 +
421 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid)
422 +{
423 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
424 +
425 + switch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) {
426 + case 0:
427 + entry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG |
428 + FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
429 + l2->vlan1 = vid;
430 + return 0;
431 + case 1:
432 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) {
433 + l2->vlan1 = vid;
434 + l2->etype |= BIT(8);
435 + } else {
436 + l2->vlan2 = vid;
437 + entry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
438 + }
439 + return 0;
440 + default:
441 + return -ENOSPC;
442 + }
443 +}
444 +
445 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
446 +{
447 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
448 +
449 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) ||
450 + (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG))
451 + l2->etype = ETH_P_PPP_SES;
452 +
453 + entry->ib1 |= MTK_FOE_IB1_BIND_PPPOE;
454 + l2->pppoe_id = sid;
455 +
456 + return 0;
457 +}
458 +
459 +static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)
460 +{
461 + return !(entry->ib1 & MTK_FOE_IB1_STATIC) &&
462 + FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;
463 +}
464 +
465 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
466 + u16 timestamp)
467 +{
468 + struct mtk_foe_entry *hwe;
469 + u32 hash;
470 +
471 + timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;
472 + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;
473 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);
474 +
475 + hash = mtk_ppe_hash_entry(entry);
476 + hwe = &ppe->foe_table[hash];
477 + if (!mtk_foe_entry_usable(hwe)) {
478 + hwe++;
479 + hash++;
480 +
481 + if (!mtk_foe_entry_usable(hwe))
482 + return -ENOSPC;
483 + }
484 +
485 + memcpy(&hwe->data, &entry->data, sizeof(hwe->data));
486 + wmb();
487 + hwe->ib1 = entry->ib1;
488 +
489 + dma_wmb();
490 +
491 + mtk_ppe_cache_clear(ppe);
492 +
493 + return hash;
494 +}
495 +
496 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
497 + int version)
498 +{
499 + struct mtk_foe_entry *foe;
500 +
501 + /* need to allocate a separate device, since it PPE DMA access is
502 + * not coherent.
503 + */
504 + ppe->base = base;
505 + ppe->dev = dev;
506 + ppe->version = version;
507 +
508 + foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),
509 + &ppe->foe_phys, GFP_KERNEL);
510 + if (!foe)
511 + return -ENOMEM;
512 +
513 + ppe->foe_table = foe;
514 +
515 + return 0;
516 +}
517 +
518 +static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)
519 +{
520 + static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };
521 + int i, k;
522 +
523 + memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));
524 +
525 + if (!IS_ENABLED(CONFIG_SOC_MT7621))
526 + return;
527 +
528 + /* skip all entries that cross the 1024 byte boundary */
529 + for (i = 0; i < MTK_PPE_ENTRIES; i += 128)
530 + for (k = 0; k < ARRAY_SIZE(skip); k++)
531 + ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;
532 +}
533 +
534 +int mtk_ppe_start(struct mtk_ppe *ppe)
535 +{
536 + u32 val;
537 +
538 + mtk_ppe_init_foe_table(ppe);
539 + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
540 +
541 + val = MTK_PPE_TB_CFG_ENTRY_80B |
542 + MTK_PPE_TB_CFG_AGE_NON_L4 |
543 + MTK_PPE_TB_CFG_AGE_UNBIND |
544 + MTK_PPE_TB_CFG_AGE_TCP |
545 + MTK_PPE_TB_CFG_AGE_UDP |
546 + MTK_PPE_TB_CFG_AGE_TCP_FIN |
547 + FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
548 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |
549 + FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,
550 + MTK_PPE_KEEPALIVE_DUP_CPU) |
551 + FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |
552 + FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,
553 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
554 + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
555 + MTK_PPE_ENTRIES_SHIFT);
556 + ppe_w32(ppe, MTK_PPE_TB_CFG, val);
557 +
558 + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
559 + MTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6);
560 +
561 + mtk_ppe_cache_enable(ppe, true);
562 +
563 + val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |
564 + MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |
565 + MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |
566 + MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |
567 + MTK_PPE_FLOW_CFG_IP6_6RD |
568 + MTK_PPE_FLOW_CFG_IP4_NAT |
569 + MTK_PPE_FLOW_CFG_IP4_NAPT |
570 + MTK_PPE_FLOW_CFG_IP4_DSLITE |
571 + MTK_PPE_FLOW_CFG_L2_BRIDGE |
572 + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
573 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);
574 +
575 + val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |
576 + FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3);
577 + ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);
578 +
579 + val = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) |
580 + FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1);
581 + ppe_w32(ppe, MTK_PPE_BIND_AGE0, val);
582 +
583 + val = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) |
584 + FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7);
585 + ppe_w32(ppe, MTK_PPE_BIND_AGE1, val);
586 +
587 + val = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF;
588 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);
589 +
590 + val = MTK_PPE_BIND_LIMIT1_FULL |
591 + FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1);
592 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);
593 +
594 + val = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) |
595 + FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1);
596 + ppe_w32(ppe, MTK_PPE_BIND_RATE, val);
597 +
598 + /* enable PPE */
599 + val = MTK_PPE_GLO_CFG_EN |
600 + MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
601 + MTK_PPE_GLO_CFG_IP4_CS_DROP |
602 + MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
603 + ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
604 +
605 + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
606 +
607 + return 0;
608 +}
609 +
610 +int mtk_ppe_stop(struct mtk_ppe *ppe)
611 +{
612 + u32 val;
613 + int i;
614 +
615 + for (i = 0; i < MTK_PPE_ENTRIES; i++)
616 + ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,
617 + MTK_FOE_STATE_INVALID);
618 +
619 + mtk_ppe_cache_enable(ppe, false);
620 +
621 + /* disable offload engine */
622 + ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
623 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
624 +
625 + /* disable aging */
626 + val = MTK_PPE_TB_CFG_AGE_NON_L4 |
627 + MTK_PPE_TB_CFG_AGE_UNBIND |
628 + MTK_PPE_TB_CFG_AGE_TCP |
629 + MTK_PPE_TB_CFG_AGE_UDP |
630 + MTK_PPE_TB_CFG_AGE_TCP_FIN;
631 + ppe_clear(ppe, MTK_PPE_TB_CFG, val);
632 +
633 + return mtk_ppe_wait_busy(ppe);
634 +}
635 --- /dev/null
636 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
637 @@ -0,0 +1,274 @@
638 +// SPDX-License-Identifier: GPL-2.0-only
639 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
640 +
641 +#ifndef __MTK_PPE_H
642 +#define __MTK_PPE_H
643 +
644 +#include <linux/kernel.h>
645 +#include <linux/bitfield.h>
646 +
647 +#define MTK_ETH_PPE_BASE 0xc00
648 +
649 +#define MTK_PPE_ENTRIES_SHIFT 3
650 +#define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT)
651 +#define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1)
652 +
653 +#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
654 +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
655 +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24)
656 +
657 +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
658 +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15)
659 +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16)
660 +#define MTK_FOE_IB1_BIND_PPPOE BIT(19)
661 +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20)
662 +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21)
663 +#define MTK_FOE_IB1_BIND_CACHE BIT(22)
664 +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
665 +#define MTK_FOE_IB1_BIND_TTL BIT(24)
666 +
667 +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25)
668 +#define MTK_FOE_IB1_STATE GENMASK(29, 28)
669 +#define MTK_FOE_IB1_UDP BIT(30)
670 +#define MTK_FOE_IB1_STATIC BIT(31)
671 +
672 +enum {
673 + MTK_PPE_PKT_TYPE_IPV4_HNAPT = 0,
674 + MTK_PPE_PKT_TYPE_IPV4_ROUTE = 1,
675 + MTK_PPE_PKT_TYPE_BRIDGE = 2,
676 + MTK_PPE_PKT_TYPE_IPV4_DSLITE = 3,
677 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
678 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
679 + MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
680 +};
681 +
682 +#define MTK_FOE_IB2_QID GENMASK(3, 0)
683 +#define MTK_FOE_IB2_PSE_QOS BIT(4)
684 +#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
685 +#define MTK_FOE_IB2_MULTICAST BIT(8)
686 +
687 +#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12)
688 +#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16)
689 +#define MTK_FOE_IB2_WHNAT_NAT BIT(17)
690 +
691 +#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12)
692 +
693 +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18)
694 +
695 +#define MTK_FOE_IB2_DSCP GENMASK(31, 24)
696 +
697 +#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0)
698 +#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6)
699 +#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14)
700 +
701 +enum {
702 + MTK_FOE_STATE_INVALID,
703 + MTK_FOE_STATE_UNBIND,
704 + MTK_FOE_STATE_BIND,
705 + MTK_FOE_STATE_FIN
706 +};
707 +
708 +struct mtk_foe_mac_info {
709 + u16 vlan1;
710 + u16 etype;
711 +
712 + u32 dest_mac_hi;
713 +
714 + u16 vlan2;
715 + u16 dest_mac_lo;
716 +
717 + u32 src_mac_hi;
718 +
719 + u16 pppoe_id;
720 + u16 src_mac_lo;
721 +};
722 +
723 +struct mtk_foe_bridge {
724 + u32 dest_mac_hi;
725 +
726 + u16 src_mac_lo;
727 + u16 dest_mac_lo;
728 +
729 + u32 src_mac_hi;
730 +
731 + u32 ib2;
732 +
733 + u32 _rsv[5];
734 +
735 + u32 udf_tsid;
736 + struct mtk_foe_mac_info l2;
737 +};
738 +
739 +struct mtk_ipv4_tuple {
740 + u32 src_ip;
741 + u32 dest_ip;
742 + union {
743 + struct {
744 + u16 dest_port;
745 + u16 src_port;
746 + };
747 + struct {
748 + u8 protocol;
749 + u8 _pad[3]; /* fill with 0xa5a5a5 */
750 + };
751 + u32 ports;
752 + };
753 +};
754 +
755 +struct mtk_foe_ipv4 {
756 + struct mtk_ipv4_tuple orig;
757 +
758 + u32 ib2;
759 +
760 + struct mtk_ipv4_tuple new;
761 +
762 + u16 timestamp;
763 + u16 _rsv0[3];
764 +
765 + u32 udf_tsid;
766 +
767 + struct mtk_foe_mac_info l2;
768 +};
769 +
770 +struct mtk_foe_ipv4_dslite {
771 + struct mtk_ipv4_tuple ip4;
772 +
773 + u32 tunnel_src_ip[4];
774 + u32 tunnel_dest_ip[4];
775 +
776 + u8 flow_label[3];
777 + u8 priority;
778 +
779 + u32 udf_tsid;
780 +
781 + u32 ib2;
782 +
783 + struct mtk_foe_mac_info l2;
784 +};
785 +
786 +struct mtk_foe_ipv6 {
787 + u32 src_ip[4];
788 + u32 dest_ip[4];
789 +
790 + union {
791 + struct {
792 + u8 protocol;
793 + u8 _pad[3]; /* fill with 0xa5a5a5 */
794 + }; /* 3-tuple */
795 + struct {
796 + u16 dest_port;
797 + u16 src_port;
798 + }; /* 5-tuple */
799 + u32 ports;
800 + };
801 +
802 + u32 _rsv[3];
803 +
804 + u32 udf;
805 +
806 + u32 ib2;
807 + struct mtk_foe_mac_info l2;
808 +};
809 +
810 +struct mtk_foe_ipv6_6rd {
811 + u32 src_ip[4];
812 + u32 dest_ip[4];
813 + u16 dest_port;
814 + u16 src_port;
815 +
816 + u32 tunnel_src_ip;
817 + u32 tunnel_dest_ip;
818 +
819 + u16 hdr_csum;
820 + u8 dscp;
821 + u8 ttl;
822 +
823 + u8 flag;
824 + u8 pad;
825 + u8 per_flow_6rd_id;
826 + u8 pad2;
827 +
828 + u32 ib2;
829 + struct mtk_foe_mac_info l2;
830 +};
831 +
832 +struct mtk_foe_entry {
833 + u32 ib1;
834 +
835 + union {
836 + struct mtk_foe_bridge bridge;
837 + struct mtk_foe_ipv4 ipv4;
838 + struct mtk_foe_ipv4_dslite dslite;
839 + struct mtk_foe_ipv6 ipv6;
840 + struct mtk_foe_ipv6_6rd ipv6_6rd;
841 + u32 data[19];
842 + };
843 +};
844 +
845 +enum {
846 + MTK_PPE_CPU_REASON_TTL_EXCEEDED = 0x02,
847 + MTK_PPE_CPU_REASON_OPTION_HEADER = 0x03,
848 + MTK_PPE_CPU_REASON_NO_FLOW = 0x07,
849 + MTK_PPE_CPU_REASON_IPV4_FRAG = 0x08,
850 + MTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
851 + MTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
852 + MTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
853 + MTK_PPE_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
854 + MTK_PPE_CPU_REASON_UN_HIT = 0x0d,
855 + MTK_PPE_CPU_REASON_HIT_UNBIND = 0x0e,
856 + MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
857 + MTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
858 + MTK_PPE_CPU_REASON_HIT_TTL_1 = 0x11,
859 + MTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
860 + MTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
861 + MTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
862 + MTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
863 + MTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
864 + MTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
865 + MTK_PPE_CPU_REASON_MULTICAST_TO_CPU = 0x18,
866 + MTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
867 + MTK_PPE_CPU_REASON_HIT_PRE_BIND = 0x1a,
868 + MTK_PPE_CPU_REASON_PACKET_SAMPLING = 0x1b,
869 + MTK_PPE_CPU_REASON_EXCEED_MTU = 0x1c,
870 + MTK_PPE_CPU_REASON_PPE_BYPASS = 0x1e,
871 + MTK_PPE_CPU_REASON_INVALID = 0x1f,
872 +};
873 +
874 +struct mtk_ppe {
875 + struct device *dev;
876 + void __iomem *base;
877 + int version;
878 +
879 + struct mtk_foe_entry *foe_table;
880 + dma_addr_t foe_phys;
881 +
882 + void *acct_table;
883 +};
884 +
885 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
886 + int version);
887 +int mtk_ppe_start(struct mtk_ppe *ppe);
888 +int mtk_ppe_stop(struct mtk_ppe *ppe);
889 +
890 +static inline void
891 +mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)
892 +{
893 + ppe->foe_table[hash].ib1 = 0;
894 + dma_wmb();
895 +}
896 +
897 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
898 + u8 pse_port, u8 *src_mac, u8 *dest_mac);
899 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig,
900 + __be32 src_addr, __be16 src_port,
901 + __be32 dest_addr, __be16 dest_port);
902 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
903 + __be32 *src_addr, __be16 src_port,
904 + __be32 *dest_addr, __be16 dest_port);
905 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
906 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
907 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
908 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
909 + u16 timestamp);
910 +
911 +#endif
912 --- /dev/null
913 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
914 @@ -0,0 +1,144 @@
915 +// SPDX-License-Identifier: GPL-2.0-only
916 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
917 +
918 +#ifndef __MTK_PPE_REGS_H
919 +#define __MTK_PPE_REGS_H
920 +
921 +#define MTK_PPE_GLO_CFG 0x200
922 +#define MTK_PPE_GLO_CFG_EN BIT(0)
923 +#define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
924 +#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
925 +#define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
926 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
927 +#define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
928 +#define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
929 +#define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
930 +#define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
931 +#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9)
932 +#define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
933 +#define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
934 +#define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
935 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
936 +
937 +#define MTK_PPE_FLOW_CFG 0x204
938 +#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6)
939 +#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7)
940 +#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8)
941 +#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9)
942 +#define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10)
943 +#define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12)
944 +#define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13)
945 +#define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14)
946 +#define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15)
947 +#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16)
948 +#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17)
949 +#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18)
950 +#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19)
951 +#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20)
952 +
953 +#define MTK_PPE_IP_PROTO_CHK 0x208
954 +#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
955 +#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)
956 +
957 +#define MTK_PPE_TB_CFG 0x21c
958 +#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
959 +#define MTK_PPE_TB_CFG_ENTRY_80B BIT(3)
960 +#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)
961 +#define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6)
962 +#define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7)
963 +#define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8)
964 +#define MTK_PPE_TB_CFG_AGE_TCP BIT(9)
965 +#define MTK_PPE_TB_CFG_AGE_UDP BIT(10)
966 +#define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11)
967 +#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
968 +#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)
969 +#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)
970 +#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)
971 +
972 +enum {
973 + MTK_PPE_SCAN_MODE_DISABLED,
974 + MTK_PPE_SCAN_MODE_CHECK_AGE,
975 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE,
976 +};
977 +
978 +enum {
979 + MTK_PPE_KEEPALIVE_DISABLE,
980 + MTK_PPE_KEEPALIVE_UNICAST_CPU,
981 + MTK_PPE_KEEPALIVE_DUP_CPU = 3,
982 +};
983 +
984 +enum {
985 + MTK_PPE_SEARCH_MISS_ACTION_DROP,
986 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,
987 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,
988 +};
989 +
990 +#define MTK_PPE_TB_BASE 0x220
991 +
992 +#define MTK_PPE_TB_USED 0x224
993 +#define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
994 +
995 +#define MTK_PPE_BIND_RATE 0x228
996 +#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)
997 +#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16)
998 +
999 +#define MTK_PPE_BIND_LIMIT0 0x22c
1000 +#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
1001 +#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16)
1002 +
1003 +#define MTK_PPE_BIND_LIMIT1 0x230
1004 +#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
1005 +#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16)
1006 +
1007 +#define MTK_PPE_KEEPALIVE 0x234
1008 +#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)
1009 +#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16)
1010 +#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24)
1011 +
1012 +#define MTK_PPE_UNBIND_AGE 0x238
1013 +#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16)
1014 +#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)
1015 +
1016 +#define MTK_PPE_BIND_AGE0 0x23c
1017 +#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
1018 +#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)
1019 +
1020 +#define MTK_PPE_BIND_AGE1 0x240
1021 +#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
1022 +#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)
1023 +
1024 +#define MTK_PPE_HASH_SEED 0x244
1025 +
1026 +#define MTK_PPE_DEFAULT_CPU_PORT 0x248
1027 +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))
1028 +
1029 +#define MTK_PPE_MTU_DROP 0x308
1030 +
1031 +#define MTK_PPE_VLAN_MTU0 0x30c
1032 +#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
1033 +#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16)
1034 +
1035 +#define MTK_PPE_VLAN_MTU1 0x310
1036 +#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
1037 +#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16)
1038 +
1039 +#define MTK_PPE_VPM_TPID 0x318
1040 +
1041 +#define MTK_PPE_CACHE_CTL 0x320
1042 +#define MTK_PPE_CACHE_CTL_EN BIT(0)
1043 +#define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4)
1044 +#define MTK_PPE_CACHE_CTL_REQ BIT(8)
1045 +#define MTK_PPE_CACHE_CTL_CLEAR BIT(9)
1046 +#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)
1047 +
1048 +#define MTK_PPE_MIB_CFG 0x334
1049 +#define MTK_PPE_MIB_CFG_EN BIT(0)
1050 +#define MTK_PPE_MIB_CFG_RD_CLR BIT(1)
1051 +
1052 +#define MTK_PPE_MIB_TB_BASE 0x338
1053 +
1054 +#define MTK_PPE_MIB_CACHE_CTL 0x350
1055 +#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
1056 +#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
1057 +
1058 +#endif
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