target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_mei_ioctl.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_mei_ioctl.h
   4 ** PROJECT      : Danube
   5 ** MODULES      : MEI
   6 **
   7 ** DATE         : 1 Jan 2006
   8 ** AUTHOR       : TC Chen
   9 ** DESCRIPTION  : MEI Driver
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Version $Date      $Author     $Comment
  21 *******************************************************************************/
  22 #ifndef         _IFXMIPS_MEI_IOCTL_H
  23 #define         _IFXMIPS_MEI_IOCTL_H
  24
  25 /////////////////////////////////////////////////////////////////////////////////////////////////////
  26 #define PCM_BUFF_SIZE           1024    //bytes
  27 //  interrupt numbers
  28
  29 #if !(defined(_IFXMIPS_ADSL_APP) || defined (_AMAZON_ADSL_APP))
  30
  31 // Number of intervals
  32 #define INTERVAL_NUM                                    192     //two days
  33 typedef struct ifxmips_mei_mib {
  34         struct list_head list;
  35         struct timeval start_time;      //start of current interval
  36
  37         int AtucPerfLof;
  38         int AtucPerfLos;
  39         int AtucPerfEs;
  40         int AtucPerfInit;
  41
  42         int AturPerfLof;
  43         int AturPerfLos;
  44         int AturPerfLpr;
  45         int AturPerfEs;
  46
  47         int AturChanPerfRxBlk;
  48         int AturChanPerfTxBlk;
  49         int AturChanPerfCorrBlk;
  50         int AturChanPerfUncorrBlk;
  51
  52         //RFC-3440
  53         int AtucPerfStatFastR;
  54         int AtucPerfStatFailedFastR;
  55         int AtucPerfStatSesL;
  56         int AtucPerfStatUasL;
  57         int AturPerfStatSesL;
  58         int AturPerfStatUasL;
  59 } ifxmips_mei_mib;
  60
  61 typedef struct adslChanPrevTxRate {
  62         u32 adslAtucChanPrevTxRate;
  63         u32 adslAturChanPrevTxRate;
  64 } adslChanPrevTxRate;
  65
  66 typedef struct adslPhysCurrStatus {
  67         u32 adslAtucCurrStatus;
  68         u32 adslAturCurrStatus;
  69 } adslPhysCurrStatus;
  70
  71 typedef struct ChanType {
  72         int interleave;
  73         int fast;
  74         int bearchannel0;
  75         int bearchannel1;
  76 } ChanType;
  77
  78 typedef struct mib_previous_read {
  79         u16 ATUC_PERF_ESS;
  80         u16 ATUR_PERF_ESS;
  81         u32 ATUR_CHAN_RECV_BLK;
  82         u16 ATUR_CHAN_CORR_BLK_INTL;
  83         u16 ATUR_CHAN_CORR_BLK_FAST;
  84         u16 ATUR_CHAN_UNCORR_BLK_INTL;
  85         u16 ATUR_CHAN_UNCORR_BLK_FAST;
  86         u16 ATUC_PERF_STAT_FASTR;
  87         u16 ATUC_PERF_STAT_FAILED_FASTR;
  88         u16 ATUC_PERF_STAT_SESL;
  89         u16 ATUC_PERF_STAT_UASL;
  90         u16 ATUR_PERF_STAT_SESL;
  91 } mib_previous_read;
  92
  93 typedef struct mib_flags_pretime {
  94         struct timeval ATUC_PERF_LOSS_PTIME;
  95         struct timeval ATUC_PERF_LOFS_PTIME;
  96         struct timeval ATUR_PERF_LOSS_PTIME;
  97         struct timeval ATUR_PERF_LOFS_PTIME;
  98         struct timeval ATUR_PERF_LPR_PTIME;
  99 } mib_flags_pretime;
 100
 101                 //  cmv message structures
 102 #define MP_PAYLOAD_SIZE                                 12
 103 typedef struct mpmessage {
 104         u16 iFunction;
 105         u16 iGroup;
 106         u16 iAddress;
 107         u16 iIndex;
 108         u16 iPayload[MP_PAYLOAD_SIZE];
 109 } MPMessage;
 110 #endif
 111
 112 typedef struct meireg {
 113         u32 iAddress;
 114         u32 iData;
 115 } meireg;
 116
 117 #define MEIDEBUG_BUFFER_SIZES 50
 118 typedef struct meidebug {
 119         u32 iAddress;
 120         u32 iCount;
 121         u32 buffer[MEIDEBUG_BUFFER_SIZES];
 122 } meidebug;
 123
 124 //==============================================================================
 125 // Group definitions
 126 //==============================================================================
 127 #define OPTN                    5
 128 #define CNFG                    8
 129 #define CNTL                    1
 130 #define STAT                    2
 131 #define RATE                    6
 132 #define PLAM                    7
 133 #define INFO                    3
 134 #define TEST                    4
 135 //==============================================================================
 136 // Opcode definitions
 137 //==============================================================================
 138 #define H2D_CMV_READ                            0x00
 139 #define H2D_CMV_WRITE                           0x04
 140 #define H2D_CMV_INDICATE_REPLY                  0x10
 141 #define H2D_ERROR_OPCODE_UNKNOWN                0x20
 142 #define H2D_ERROR_CMV_UNKNOWN                   0x30
 143
 144 #define D2H_CMV_READ_REPLY                      0x01
 145 #define D2H_CMV_WRITE_REPLY                     0x05
 146 #define D2H_CMV_INDICATE                        0x11
 147 #define D2H_ERROR_OPCODE_UNKNOWN                0x21
 148 #define D2H_ERROR_CMV_UNKNOWN                   0x31
 149 #define D2H_ERROR_CMV_READ_NOT_AVAILABLE        0x41
 150 #define D2H_ERROR_CMV_WRITE_ONLY                0x51
 151 #define D2H_ERROR_CMV_READ_ONLY                 0x61
 152
 153 #define H2D_DEBUG_READ_DM                       0x02
 154 #define H2D_DEBUG_READ_PM                       0x06
 155 #define H2D_DEBUG_WRITE_DM                      0x0a
 156 #define H2D_DEBUG_WRITE_PM                      0x0e
 157
 158 #define D2H_DEBUG_READ_DM_REPLY                 0x03
 159 #define D2H_DEBUG_READ_FM_REPLY                 0x07
 160 #define D2H_DEBUG_WRITE_DM_REPLY                0x0b
 161 #define D2H_DEBUG_WRITE_FM_REPLY                0x0f
 162 #define D2H_ERROR_ADDR_UNKNOWN                  0x33
 163
 164 #define D2H_AUTONOMOUS_MODEM_READY_MSG          0xf1
 165 //==============================================================================
 166 // INFO register address field definitions
 167 //==============================================================================
 168
 169 #define INFO_TxState                                    0
 170 #define INFO_RxState                                    1
 171 #define INFO_TxNextState                                2
 172 #define INFO_RxNextState                                3
 173 #define INFO_TxStateJumpFrom                            4
 174 #define INFO_RxStateJumpFrom                            5
 175
 176 #define INFO_ReverbSnrBuf                               8
 177 #define INFO_ReverbEchoSnrBuf                           9
 178 #define INFO_MedleySnrBuf                               10
 179 #define INFO_RxShowtimeSnrBuf                           11
 180 #define INFO_DECdelay                                   12
 181 #define INFO_DECExponent                                13
 182 #define INFO_DECTaps                                    14
 183 #define INFO_AECdelay                                   15
 184 #define INFO_AECExponent                                16
 185 #define INFO_AECTaps                                    17
 186 #define INFO_TDQExponent                                18
 187 #define INFO_TDQTaps                                    19
 188 #define INFO_FDQExponent                                20
 189 #define INFO_FDQTaps                                    21
 190 #define INFO_USBat                                      22
 191 #define INFO_DSBat                                      23
 192 #define INFO_USFineGains                                24
 193 #define INFO_DSFineGains                                25
 194 #define INFO_BitloadFirstChannel                        26
 195 #define INFO_BitloadLastChannel                         27
 196 #define INFO_PollEOCData                                28      // CO specific
 197 #define INFO_CSNRMargin                                 29      // CO specific
 198 #define INFO_RCMsgs1                                    30
 199 #define INFO_RMsgs1                                     31
 200 #define INFO_RMsgRA                                     32
 201 #define INFO_RCMsgRA                                    33
 202 #define INFO_RMsg2                                      34
 203 #define INFO_RCMsg2                                     35
 204 #define INFO_BitLoadOK                                  36
 205 #define INFO_RCRates1                                   37
 206 #define INFO_RRates1Tab                                 38
 207 #define INFO_RMsgs1Tab                                  39
 208 #define INFO_RMsgRATab                                  40
 209 #define INFO_RRatesRA                                   41
 210 #define INFO_RCRatesRA                                  42
 211 #define INFO_RRates2                                    43
 212 #define INFO_RCRates2                                   44
 213 #define INFO_PackedRMsg2                                45
 214 #define INFO_RxBitSwapFlag                              46
 215 #define INFO_TxBitSwapFlag                              47
 216 #define INFO_ShowtimeSNRUpdateCount                     48
 217 #define INFO_ShowtimeFDQUpdateCount                     49
 218 #define INFO_ShowtimeDECUpdateCount                     50
 219 #define INFO_CopyRxBuffer                               51
 220 #define INFO_RxToneBuf                                  52
 221 #define INFO_TxToneBuf                                  53
 222 #define INFO_Version                                    54
 223 #define INFO_TimeStamp                                  55
 224 #define INFO_feVendorID                                 56
 225 #define INFO_feSerialNum                                57
 226 #define INFO_feVersionNum                               58
 227 #define INFO_BulkMemory                                 59      //Points to start of bulk memory
 228 #define INFO_neVendorID                                 60
 229 #define INFO_neVersionNum                               61
 230 #define INFO_neSerialNum                                62
 231
 232 //==============================================================================
 233 // RATE register address field definitions
 234 //==============================================================================
 235
 236 #define RATE_UsRate                                     0
 237 #define RATE_DsRate                                     1
 238
 239 //==============================================================================
 240 // PLAM (Physical Layer Management) register address field definitions
 241 //      (See G997.1 for reference)
 242 //==============================================================================
 243
 244         //                                      ///
 245         // Failure Flags        ///
 246         //                                      ///
 247
 248 #define PLAM_NearEndFailureFlags                0
 249 #define PLAM_FarEndFailureFlags                 1
 250
 251         //                                                                      ///
 252         // Near End Failure Flags Bit Definitions       ///
 253         //                                                                      ///
 254
 255 // ADSL Failures ///
 256 #define PLAM_LOS_FailureBit                             0x0001
 257 #define PLAM_LOF_FailureBit                             0x0002
 258 #define PLAM_LPR_FailureBit                             0x0004
 259 #define PLAM_RFI_FailureBit                             0x0008
 260
 261 // ATM Failures ///
 262 #define PLAM_NCD_LP0_FailureBit                         0x0010
 263 #define PLAM_NCD_LP1_FailureBit                         0x0020
 264 #define PLAM_LCD_LP0_FailureBit                         0x0040
 265 #define PLAM_LCD_LP1_FailureBit                         0x0080
 266
 267 #define PLAM_NCD_BC0_FailureBit                         0x0100
 268 #define PLAM_NCD_BC1_FailureBit                         0x0200
 269 #define PLAM_LCD_BC0_FailureBit                         0x0400
 270 #define PLAM_LCD_BC1_FailureBit                         0x0800
 271         //                                              ///
 272         // Performance Counts   ///
 273         //                                              ///
 274
 275 #define PLAM_NearEndCrcCnt                              2
 276 #define PLAM_CorrectedRSErrors                          3
 277
 278 #define PLAM_NearEndECSCnt                              6
 279 #define PLAM_NearEndESCnt                               7
 280 #define PLAM_NearEndSESCnt                              8
 281 #define PLAM_NearEndLOSSCnt                             9
 282 #define PLAM_NearEndUASLCnt                             10
 283
 284 #define PLAM_NearEndHECErrCnt                           11
 285
 286 #define PLAM_NearEndHECTotCnt                           16
 287 #define PLAM_NearEndCellTotCnt                          18
 288 #define PLAM_NearEndSfCntLSW                            20
 289 #define PLAM_NearEndSfCntMSW                            21
 290
 291 #define PLAM_FarEndFebeCnt                              24
 292
 293 #define PLAM_FarEndFecCnt                               28
 294
 295 #define PLAM_FarEndFECSCnt                              32
 296 #define PLAM_FarEndESCnt                                33
 297 #define PLAM_FarEndSESCnt                               34
 298 #define PLAM_FarEndLOSSCnt                              35
 299 #define PLAM_FarEndUASLCnt                              36
 300
 301 #define PLAM_FarEndHECErrCnt                            37
 302
 303 #define PLAM_FarEndHECTotCnt                            41
 304
 305 #define PLAM_FarEndCellTotCnt                           43
 306
 307 #define PLAM_SNRMargin_0_1db                            45
 308
 309 #define PLAM_SNRMargin                                  46
 310
 311 //==============================================================================
 312 // CNTL register address and bit field definitions
 313 //==============================================================================
 314
 315 #define CNTL_ModemControl                               0
 316
 317 #define CNTL_ModemReset                                 0x0
 318 #define CNTL_ModemStart                                 0x2
 319
 320 //==============================================================================
 321 // STAT register address and bit field definitions
 322 //==============================================================================
 323
 324 #define STAT_MacroState                                 0
 325 #define STAT_Mode                                       1
 326 #define STAT_DMTFramingMode                             2
 327 #define STAT_SleepState                                 3
 328 #define STAT_Misc                                       4
 329 #define STAT_FailureState                               5
 330
 331 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 332  // STAT_OLRStatus provides status of OLR
 333  //16-bit STAT_OLRStatus_DS
 334  //  [1:0]      :       OLR status 00=IDLE,  01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
 335  //  [3:2]:             Reserved
 336  //  [5:4]:             OLR_Type (1:bitswap; 2: DRR; 3: SRA)
 337  //  [7:6]:             Reserved
 338  //  [10:8]:            >0=Request. 0=not.   For DS, # of request transmissions/retransmissions (3 bits).
 339  //  [11]:              1=Receive Response, 0=not
 340  //  [15:12]:   Reserved
 341  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 342  ///
 343 #define STAT_OLRStatus_DS                               6
 344
 345 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 346  // STAT_OLRStatus provides status of OLR
 347  // 16-bit STAT_OLRStatus_US CMV
 348  //  [1:0]      :       OLR status 00=IDLE,  01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
 349  //  [3:2]:             Reserved
 350  //  [5:4]:             OLR_Type (1:bitswap; 2: DRR; 3: SRA)
 351  //  [7:6]:             Reserved
 352  //  [8]:               1=Request Received. 0=not.
 353  //  [10:9]:     Reserved
 354  //  [11]:              1=Response Sent, 0=not
 355  //  [15:12]:   Reserved
 356  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 357 ///
 358 #define STAT_OLRStatus_US                               7
 359
 360 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 361  // STAT_PMStatus provides status of PM
 362  // 16-bit STAT_PMStatus CMV
 363  //  [1:0]      :       PM Status 00=IDLE,  01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
 364  //  [2] :              0=ATU_R initiated PM; 1 = ATU_C initiated PM
 365  //  [3]:               Reserved
 366  //  [5:4]:             PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
 367  //  [7:6]:             Reserved
 368  //  [10:8]:            >0=Request. 0=not.   # of request transmissions/retransmissions (3 bits).
 369  //  [11]:              1=Response, 0=not
 370  //  [15:12]:   Reserved
 371  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 372  ///
 373 #define STAT_PMStatus                                   8
 374
 375 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 376  // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
 377  // [3:0]:          OLR/PM response reason code
 378  // [7:4]:             OLR/PM Internal error code
 379  // [15:8]:         OLR/PM Reserved for future
 380  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 381  ///
 382 #define STAT_OLRError_DS                                9
 383 #define STAT_OLRError_US                                10
 384 #define STAT_PMError                                    11
 385
 386 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 387 // STAT_MacroState
 388 // MacroState reflects the high level state of the modem
 389
 390 #define STAT_InitState                          0x0000
 391 #define STAT_ReadyState                         0x0001
 392 #define STAT_FailState                          0x0002
 393 #define STAT_IdleState                          0x0003
 394 #define STAT_QuietState                         0x0004
 395 #define STAT_GhsState                           0x0005
 396 #define STAT_FullInitState                      0x0006
 397 #define STAT_ShowTimeState                      0x0007
 398 #define STAT_FastRetrainState                   0x0008
 399 #define STAT_LoopDiagMode                       0x0009
 400 #define STAT_ShortInit                          0x000A  // Bis short initialization ///
 401
 402 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 403 // STAT_Mode
 404 // ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
 405 // G.Hs or some other mechanism to negotiate the specific mode of operation.
 406 // The OPTN_modeControl CMV is used to select a set of desired modes.
 407 // The STAT_Mode CMV indicates which mode was actually selected.
 408
 409 #define STAT_ConfigMode_T1413                   0x0001
 410 #define STAT_ConfigMode_G992_2_AB               0x0002
 411 #define STAT_ConfigMode_G992_1_A                0x0004
 412 #define STAT_ConfigMode_G992_1_B                0x0008
 413 #define STAT_ConfigMode_G992_1_C                0x0010
 414 #define STAT_ConfigMode_G992_2_C                0x0020
 415
 416 #define STAT_ConfigMode_G992_3_A                0x0100
 417 #define STAT_ConfigMode_G992_3_B                0x0200
 418 #define STAT_ConfigMode_G992_3_I                0x0400
 419 #define STAT_ConfigMode_G992_3_J                0x0800
 420 #define STAT_ConfigMode_G992_3_L                0x1000
 421
 422 #define STAT_ConfigMode_G992_4_A                0x2000
 423 #define STAT_ConfigMode_G992_4_I                0x4000
 424
 425 #define STAT_ConfigMode_G992_5                  0x8000
 426
 427 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 428 // STAT_DMTFramingMode
 429 // FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
 430 // status is not applicable in BIS mode and its value is undefined
 431 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 432
 433 #define STAT_FramingModeMask                    0x0003
 434
 435 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 436 // STAT_Misc
 437 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 438
 439 #define STAT_OverlappedSpectrum         0x0008
 440 #define STAT_TCM                        0x0010
 441 #define STAT_TDQ_at_1104                0x0020
 442 #define STAT_T1413_Signal_Detected      0x0040
 443 #define STAT_AnnexL_US_Mask1_PSD        0x1000  //indicate we actually selected G992.3 AnnexL US PSD mask1
 444 #define STAT_AnnexL_US_Mask2_PSD        0x2000  //indicate we actually selected G992.3 AnnexL US PSD mask2
 445
 446 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 447 // STAT_FailureState
 448 // when the MacroSTate indicates the fail state, FailureState provides a failure code
 449 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 450
 451 #define E_CODE_NO_ERROR                                                         0
 452 #define E_CODE_BAT_TX                                                           1       // TX BAT table is incorrect */
 453 #define E_CODE_BAT_RX                                                           2       //  RX BAT table is incorrect */
 454 #define E_CODE_PROFILE                                                          3       //  profile is not selected in fast retrain */
 455 #define E_CODE_TX_AOC_FIFO_OVERFLOW                                             4
 456 #define E_CODE_TRUNCATE_FR                                                      5       //Fast Retrain truncated due to no stored profiles*/
 457 #define E_CODE_BITLOAD                                                          6       //  bit loading fails */
 458 #define E_CODE_ST_ERROR                                                         7       //  showtime CRC error */
 459 #define E_CODE_RESERVED                                                         8       //  using parameters reserved by the ITU-T */
 460 #define E_CODE_C_TONES                                                          9       //  detected C_TONES */
 461 #define E_CODE_CODESWAP_ERR                                                     10      //  codeswap not finished in time */
 462 #define E_CODE_FIFO_OVERFLOW                                                    11      // we have run out of fifo space */
 463 #define E_CODE_C_BG_DECODE_ERR                                                  12      // error in decoding C-BG message */
 464 #define E_CODE_C_RATES2_DECODE_ERR                                              13      // error in decoding C-MSGS2 and C-RATES2 */
 465 #define E_CODE_RCMedleyRx_C_SEGUE2_Failure                                      14      //  Timeout after RCMedleyRx waiting for C_SEGUE2 */
 466 #define E_CODE_RReverbRATx_C_SEGUE2_Failure                                     15      //  Timeout after RReverbRATx waiting for C_SEGUE2 */
 467 #define E_CODE_RReverb3Tx_C_SEGUE1_Failure                                      16      //  Timeout after RReverb3Tx waiting for C_SEGUE1 */
 468 #define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR                                      17      //  Received CRC not equal to computed CRC */
 469 #define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR                                      18      //  Received CRC not equal to computed CRC */
 470 #define E_CODE_RReverb5Tx_C_SEGUE2_Failure                                      19      //  Timeout after RReverb5Tx waiting for C_SEGUE2 */
 471 #define E_CODE_RReverb6Tx_C_SEGUE3_Failure                                      20      //  Timeout after RReverb6Tx waiting for C_SEGUE3 */
 472 #define E_CODE_RSegue5Tx_C_SEGUE3_Failure                                       21      //  Timeout after RSegue5Tx waiting for C_SEGUE3 */
 473 #define E_CODE_RCReverb5Rx_C_SEGUE_Failure                                      22      //  Timeout after RCReverb5Rx waiting for C_SEGUE */
 474 #define E_CODE_RCReverbRARx_C_SEGUE2_Failure                                    23      //  Timeout after RCReverbRARx waiting for C_SEGUE2 */
 475 #define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR                                        24      //  Received CRC not equal to computed CRC */
 476 #define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR                                          25      //  Received CRC not equal to computed CRC */
 477 #define E_CODE_RCCRC3Rx_DECOD_ERR                                               26      //  Received CRC not equal to computed CRC */
 478 #define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT                                    27      //  DEC Path Delay timeout */
 479 #define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT                                    28      //  DEC Training timeout */
 480 #define E_CODE_RCReverb3Rx_C_SEGUE1_Failure                                     29      //  Timeout after RCReverb3Rx waiting for C_SEGUE1 */
 481 #define E_CODE_RCReverb2Rx_SignalEnd_Failure                                    30      //  Timeout waiting for the end of RCReverb2Rx signal */
 482 #define E_CODE_RQuiet2_SignalEnd_Failure                                        31      //  Timeout waiting for the end of RQuiet2 signal */
 483 #define E_CODE_RCReverbFR1Rx_Failure                                            32      //  Timeout waiting for the end of RCReverbFR1Rx signal */
 484 #define E_CODE_RCPilotFR1Rx_SignalEnd_Failure                                   33      //  Timeout waiting for the end of RCPilotFR1Rx signal */
 485 #define E_CODE_RCReverbFR2Rx_C_Segue_Failure                                    34      //  Timeout after RCReverbFR2Rx waiting for C_SEGUE */
 486 #define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT                                  35      //  Timeout waiting for the end of RCReverbFR5Rx signal */
 487 #define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure                                    36      //  Timeout after RCReverbFR6Rx waiting for C_SEGUE */
 488 #define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure                                37      //  Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
 489 #define E_CODE_RCReverbFR8Rx_No_PROFILE                                         38      //  Timeout since no profile was selected */
 490 #define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT                                  39      //  Timeout waiting for the end of RCReverbFR8Rx signal */
 491 #define E_CODE_RCCRCFR1_DECOD_ERR                                               40      //  Received CRC not equal to computed CRC */
 492 #define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT                                     41      //  Timeout waiting for the end of RCRecovRx signal */
 493 #define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT                                 42      //  Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
 494 #define E_CODE_RRecovTx_SignalEnd_TIMEOUT                                       43      //  Timeout waiting for the end of RRecovTx signal */
 495 #define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure                                    44      //  Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
 496 #define E_CODE_CONFIGURATION_PARAMETERS_ERROR                                   45      // one of the configuration parameters do not meet the standard */
 497 #define E_CODE_BAD_MEM_ACCESS                                                   46
 498 #define E_CODE_BAD_INSTRUCTION_ACCESS                                           47
 499 #define E_CODE_TX_EOC_FIFO_OVERFLOW                                             48
 500 #define E_CODE_RX_EOC_FIFO_OVERFLOW                                             49
 501 #define E_CODE_GHS_CD_FLAG_TIME_OUT                                             50      // Timeout when transmitting Flag in handshake cleardown */
 502
 503 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 504 //STAT_OLRStatus:
 505 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 506
 507 #define STAT_OLRPM_IDLE                                 0x0000
 508 #define STAT_OLRPM_IN_PROGRESS                          0x0001
 509 #define STAT_OLRPM_COMPLETE                             0x0002
 510 #define STAT_OLRPM_ABORTED                              0x0003
 511 #define STAT_OLRPM_RESPONSE                             0x0800
 512
 513 #define STAT_OLR_BITSWAP                                0x0010
 514 #define STAT_OLR_DRR                                    0x0020
 515 #define STAT_OLR_SRA                                    0x0030
 516
 517 //STAT_PMStatus_US:
 518 #define STAT_PM_CO_REQ                                  0x0004
 519 #define STAT_PM_SIMPLE_REQ                              0x0010
 520 #define STAT_PM_L2_REQ                                  0x0020
 521 #define STAT_PM_L2_TRIM_REQ                             0x0030
 522
 523 // STAT_OLRError_DS, STAT_OLRError_US
 524 //4 bit response reason code:
 525 #define RESP_BUSY                                       0x01
 526 #define RESP_INVALID_PARAMETERS                         0x02
 527 #define RESP_NOT_ENABLED                                0x03
 528 #define RESP_NOT_SUPPORTED                              0x04
 529
 530 //4 bit internal error code (common for OLR and PM)
 531 #define REQ_INVALID_BiGi                                0x10
 532 #define REQ_INVALID_Lp                                  0x20
 533 #define REQ_INVALID_Bpn                                 0x30
 534 #define REQ_INVALID_FRAMING_CONSTRAINT                  0x40
 535 #define REQ_NOT_IN_L0_STATE                             0x50
 536 #define REQ_NOT_IN_L2_STATE                             0x60
 537 #define REQ_INVALID_PCB                                 0x70
 538 #define REQ_VIOLATES_MARGIN                             0x80
 539
 540 //STAT_PMError
 541 //4 bit response reason code:
 542 #define RESP_STATE_NOT_DESIRED                          0x03
 543 #define RESP_INFEASIBLE_PARAMETERS                      0x04
 544
 545 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 546 // OPTN register address and bit field definitions
 547 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 548
 549 #define OPTN_ModeControl                                0
 550 #define OPTN_DMTLnkCtl                                  1
 551 // Reserved                                             2
 552 #define OPTN_GhsControl                                 3
 553 // Reserved                                             4
 554 #define OPTN_PwrManControl                              5
 555 #define OPTN_AnnexControl                               6
 556 #define OPTN_ModeControl1                               7
 557 // Reserved                                             8
 558 #define OPTN_StateMachineCtrl                           9
 559 // Reserved                                             10
 560 // Reserved                                             11
 561 #define OPTN_BisLinkControl                             12
 562 #define OPTN_ATMAddrConfig                              13
 563 #define OPTN_ATMNumCellConfig                           14
 564
 565 // Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
 566 // use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
 567 // The OPTN_ModeControl CMV is used to select a set of desired modes ///
 568 // The STAT_ModeControl CMV indicates which mode was actually selected ///
 569
 570 // OPTN_ModeControl
 571 #define OPTN_ConfigMode_T1413                   0x0001
 572 #define OPTN_ConfigMode_G992_2_AB               0x0002
 573 #define OPTN_ConfigMode_G992_1_A                0x0004
 574 #define OPTN_ConfigMode_G992_1_B                0x0008
 575 #define OPTN_ConfigMode_G992_1_C                0x0010
 576 #define OPTN_ConfigMode_G992_2_C                0x0020
 577
 578 #define OPTN_ConfigMode_G992_3_A                0x0100
 579 #define OPTN_ConfigMode_G992_3_B                0x0200
 580 #define OPTN_ConfigMode_G992_3_I                0x0400
 581 #define OPTN_ConfigMode_G992_3_J                0x0800
 582 #define OPTN_ConfigMode_G992_3_L                0x1000
 583
 584 #define OPTN_ConfigMode_G992_4_A                0x2000
 585 #define OPTN_ConfigMode_G992_4_I                0x4000
 586
 587 #define OPTN_ConfigMode_G992_5                  0x8000
 588
 589 // OPTN_PwrManControl
 590 #define OPTN_PwrManWakeUpGhs                    0x1
 591 #define OPTN_PwrManWakeUpFR                     0x2
 592
 593 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 594 // OPTN_DMT Link Control
 595 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 596 #define OPTN_DMT_DualLatency_Dis                0x200
 597 #define OPTN_DMT_S_Dis                          0x100
 598 #define OPTN_DMT_FRAMINGMODE                    0x1
 599 #define OPTN_DMT_FRAMINGMODE_MASK               0x7
 600
 601 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 602 // OPTN_BIS Link Control
 603 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 604 #define OPTN_BisLinkContrl_LineProbeDis         0x1
 605 #define OPTN_BisLinkContrl_DSBlackBitsEn        0x2
 606 #define OPTN_BisLinkContrl_DiagnosticModeEn     0x4
 607 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 608 // OPTN_GhsControl
 609 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 610 //
 611 // for OPTN_GhsControl, we will assign 16bit word as follows
 612 // bit 0~3: set the control over which start(initial) message CPE will send:
 613 //
 614 //              BIT: 2  1  0
 615 //                       0  0  1  CLR
 616 //                       0  1  0  MR
 617 //                       0  1  1  MS
 618 //                       1  0  0  MP
 619 //
 620 //  // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
 621 //        BIT: 5  4
 622 //                   0  1  MS
 623 //                       1  0  MR
 624 //                       1  1  MP
 625 //
 626 //  // bit 15: RT initiated G.hs sample sessions one through eight.  Session one is default.
 627 //        BIT: 15
 628 //                        1  means session one
 629 //
 630 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 631
 632 #define OPTN_GHS_ST_GHS                                 0x8000
 633 #define OPTN_GHS_INIT_MASK                              0x000F
 634 #define OPTN_GHS_RESP_MASK                              0x00F0
 635
 636 #define OPTN_RTInitTxMsg_CLR                            0x0001
 637 #define OPTN_RTInitTxMsg_MR                             0x0002
 638 #define OPTN_RTInitTxMsg_MS                             0x0003
 639 #define OPTN_RTInitTxMsg_MP                             0x0004
 640
 641 #define OPTN_RTRespTxMsg_MS                             0x0010
 642 #define OPTN_RTRespTxMsg_MR                             0x0020
 643 #define OPTN_RTRespTxMsg_MP                             0x0030
 644
 645 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 646 //      OPTN_AnnexControl
 647 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 648
 649 // G.992.3 Annex A/L1/L2 US PSD Mask preferred
 650
 651 #define OPTN_G992_3_AnnexA_PreferredModeMask            0x3000
 652 #define OPTN_G992_3_AnnexA_PreferredModeA               0x0000  // default AnnexA PSD mask ///
 653 #define OPTN_G992_3_AnnexA_PreferredModeL1              0x1000  // AnnexL wide spectrum upstream PSD mask ///
 654 #define OPTN_G992_3_AnnexA_PreferredModeL2              0x2000  // AnnexL narrow spectrum upstream PSD mask ///
 655
 656 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 657 //OPTN_ATMAddrConfig
 658 // Bits 4:0             are Utopia address for BC1
 659 // Bits 9:5             are Utopia address for BC0
 660 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 661
 662 #define OPTN_UTPADDR_BC1                                0x001F
 663 #define OPTN_UTPADDR_BC0                                0x03E0
 664
 665 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 666 //OPTN_ATMNumCellConfig
 667 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 668
 669 #define OPTN_BC1_NUM_CELL_PAGES                         0x000F  // Bits 0:3 ///
 670 #define OPTN_BC0_NUM_CELL_PAGES                         0x00F0  // Bits 4:7 ///
 671
 672 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 673 // CNFG register address field ///
 674 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 675
 676 ///////////////////////////////////////////
 677 // these cmvs are used by bis handshake ///
 678 ///////////////////////////////////////////
 679
 680 // Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
 681 #define CNFG_TPS_TC_DS0                                 0
 682 #define CNFG_TPS_TC_DS1                                 1
 683 #define CNFG_TPS_TC_US0                                 2
 684 #define CNFG_TPS_TC_US1                                 3
 685
 686 #define CNFG_HDLC_Overhead_Requirements                 4
 687
 688 // Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
 689 #define CNFG_PMS_TC_DS0                                 5
 690 #define CNFG_PMS_TC_DS1                                 6
 691 #define CNFG_PMS_TC_US0                                 7
 692 #define CNFG_PMS_TC_US1                                 8
 693
 694 // CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
 695 #define CNFG_PMD_PARAMETERS                             9
 696
 697 ////////////////////////////////////////////////////////////
 698 // these cmvs are used by bis training and showtime code ///
 699 ////////////////////////////////////////////////////////////
 700
 701 ////////////////
 702 // Tx Config ///
 703 ////////////////
 704 #define CNFG_tx_Cnfg_Nbc                                10
 705 #define CNFG_tx_Cnfg_Nlp                                11
 706 #define CNFG_tx_Cnfg_Rp                                 12
 707 #define CNFG_tx_Cnfg_Mp                                 13
 708 #define CNFG_tx_Cnfg_Lp                                 14
 709 #define CNFG_tx_Cnfg_Tp                                 15
 710 #define CNFG_tx_Cnfg_Dp                                 16
 711 #define CNFG_tx_Cnfg_Bpn                                17
 712 #define CNFG_tx_Cnfg_FramingMode                        18
 713 #define CNFG_tx_Cnfg_MSGLp                              19
 714 #define CNFG_tx_Cnfg_MSGc                               20
 715
 716 ////////////////
 717 // Rx Config ///
 718 ////////////////
 719 #define CNFG_rx_Cnfg_Nbc                                21
 720 #define CNFG_rx_Cnfg_Nlp                                22
 721 #define CNFG_rx_Cnfg_Rp                                 23
 722 #define CNFG_rx_Cnfg_Mp                                 24
 723 #define CNFG_rx_Cnfg_Lp                                 25
 724 #define CNFG_rx_Cnfg_Tp                                 26
 725 #define CNFG_rx_Cnfg_Dp                                 27
 726 #define CNFG_rx_Cnfg_Bpn                                28
 727 #define CNFG_rx_Cnfg_FramingMode                        29
 728 #define CNFG_rx_Cnfg_MSGLp                              30
 729 #define CNFG_rx_Cnfg_MSGc                               31
 730
 731 #define CNFG_tx_Cnfg_BCnToLPp                           32
 732 #define CNFG_rx_Cnfg_BCnToLPp                           33
 733
 734 #endif