target/linux/imx/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch

   1 From 125120298dc05bb55a8874f07aa3f4bb6056bfb3 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Wed, 8 Jan 2020 07:44:21 -0800
   4 Subject: [PATCH 1/4] ARM: dts: imx: Add GW5907 board support
   5
   6 The Gateworks GW5907 is an IMX6 SoC based single board computer with:
   7  - IMX6Q or IMX6DL
   8  - 32bit DDR3 DRAM
   9  - FEC GbE Phy
  10  - bi-color front-panel LED
  11  - 256MB NAND boot device
  12  - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  13  - Digital IO expander (pca9555)
  14  - Joystick 12bit adc (ads1015)
  15
  16 Signed-off-by: Robert Jones <rjones@gateworks.com>
  17 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
  18 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  19 ---
  20  arch/arm/boot/dts/Makefile            |   2 +
  21  arch/arm/boot/dts/imx6dl-gw5907.dts   |  14 ++
  22  arch/arm/boot/dts/imx6q-gw5907.dts    |  14 ++
  23  arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 399 ++++++++++++++++++++++++++++++++++
  24  4 files changed, 429 insertions(+)
  25  create mode 100644 arch/arm/boot/dts/imx6dl-gw5907.dts
  26  create mode 100644 arch/arm/boot/dts/imx6q-gw5907.dts
  27  create mode 100644 arch/arm/boot/dts/imx6qdl-gw5907.dtsi
  28
  29 --- a/arch/arm/boot/dts/Makefile
  30 +++ b/arch/arm/boot/dts/Makefile
  31 @@ -418,6 +418,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  32         imx6dl-gw560x.dtb \
  33         imx6dl-gw5903.dtb \
  34         imx6dl-gw5904.dtb \
  35 +       imx6dl-gw5907.dtb \
  36         imx6dl-hummingboard.dtb \
  37         imx6dl-hummingboard-emmc-som-v15.dtb \
  38         imx6dl-hummingboard-som-v15.dtb \
  39 @@ -489,6 +490,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  40         imx6q-gw560x.dtb \
  41         imx6q-gw5903.dtb \
  42         imx6q-gw5904.dtb \
  43 +       imx6q-gw5907.dtb \
  44         imx6q-h100.dtb \
  45         imx6q-hummingboard.dtb \
  46         imx6q-hummingboard-emmc-som-v15.dtb \
  47 --- /dev/null
  48 +++ b/arch/arm/boot/dts/imx6dl-gw5907.dts
  49 @@ -0,0 +1,14 @@
  50 +// SPDX-License-Identifier: GPL-2.0
  51 +/*
  52 + * Copyright 2019 Gateworks Corporation
  53 + */
  54 +
  55 +/dts-v1/;
  56 +
  57 +#include "imx6dl.dtsi"
  58 +#include "imx6qdl-gw5907.dtsi"
  59 +
  60 +/ {
  61 +       model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
  62 +       compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
  63 +};
  64 --- /dev/null
  65 +++ b/arch/arm/boot/dts/imx6q-gw5907.dts
  66 @@ -0,0 +1,14 @@
  67 +// SPDX-License-Identifier: GPL-2.0
  68 +/*
  69 + * Copyright 2019 Gateworks Corporation
  70 + */
  71 +
  72 +/dts-v1/;
  73 +
  74 +#include "imx6q.dtsi"
  75 +#include "imx6qdl-gw5907.dtsi"
  76 +
  77 +/ {
  78 +       model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
  79 +       compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
  80 +};
  81 --- /dev/null
  82 +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
  83 @@ -0,0 +1,398 @@
  84 +// SPDX-License-Identifier: GPL-2.0
  85 +/*
  86 + * Copyright 2019 Gateworks Corporation
  87 + */
  88 +
  89 +#include <dt-bindings/gpio/gpio.h>
  90 +
  91 +/ {
  92 +       /* these are used by bootloader for disabling nodes */
  93 +       aliases {
  94 +               led0 = &led0;
  95 +               led1 = &led1;
  96 +               nand = &gpmi;
  97 +               usb0 = &usbh1;
  98 +               usb1 = &usbotg;
  99 +       };
 100 +
 101 +       chosen {
 102 +               stdout-path = &uart2;
 103 +       };
 104 +
 105 +       leds {
 106 +               compatible = "gpio-leds";
 107 +               pinctrl-names = "default";
 108 +               pinctrl-0 = <&pinctrl_gpio_leds>;
 109 +
 110 +               led0: user1 {
 111 +                       label = "user1";
 112 +                       gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 113 +                       default-state = "on";
 114 +                       linux,default-trigger = "heartbeat";
 115 +               };
 116 +
 117 +               led1: user2 {
 118 +                       label = "user2";
 119 +                       gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 120 +               };
 121 +       };
 122 +
 123 +       memory@10000000 {
 124 +               device_type = "memory";
 125 +               reg = <0x10000000 0x20000000>;
 126 +       };
 127 +
 128 +       pps {
 129 +               compatible = "pps-gpio";
 130 +               pinctrl-names = "default";
 131 +               pinctrl-0 = <&pinctrl_pps>;
 132 +               gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 133 +               status = "okay";
 134 +       };
 135 +
 136 +       reg_3p3v: regulator-3p3v {
 137 +               compatible = "regulator-fixed";
 138 +               regulator-name = "3P3V";
 139 +               regulator-min-microvolt = <3300000>;
 140 +               regulator-max-microvolt = <3300000>;
 141 +               regulator-always-on;
 142 +       };
 143 +
 144 +       reg_5p0v: regulator-5p0v {
 145 +               compatible = "regulator-fixed";
 146 +               regulator-name = "5P0V";
 147 +               regulator-min-microvolt = <5000000>;
 148 +               regulator-max-microvolt = <5000000>;
 149 +               regulator-always-on;
 150 +       };
 151 +
 152 +       reg_usb_otg_vbus: regulator-usb-otg-vbus {
 153 +               compatible = "regulator-fixed";
 154 +               regulator-name = "usb_otg_vbus";
 155 +               regulator-min-microvolt = <5000000>;
 156 +               regulator-max-microvolt = <5000000>;
 157 +               gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 158 +               enable-active-high;
 159 +       };
 160 +};
 161 +
 162 +&fec {
 163 +       pinctrl-names = "default";
 164 +       pinctrl-0 = <&pinctrl_enet>;
 165 +       phy-mode = "rgmii-id";
 166 +       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 167 +       status = "okay";
 168 +};
 169 +
 170 +&gpmi {
 171 +       pinctrl-names = "default";
 172 +       pinctrl-0 = <&pinctrl_gpmi_nand>;
 173 +       status = "okay";
 174 +};
 175 +
 176 +&hdmi {
 177 +       ddc-i2c-bus = <&i2c3>;
 178 +       status = "okay";
 179 +};
 180 +
 181 +&i2c1 {
 182 +       clock-frequency = <100000>;
 183 +       pinctrl-names = "default";
 184 +       pinctrl-0 = <&pinctrl_i2c1>;
 185 +       status = "okay";
 186 +
 187 +       gpio@23 {
 188 +               compatible = "nxp,pca9555";
 189 +               reg = <0x23>;
 190 +               gpio-controller;
 191 +               #gpio-cells = <2>;
 192 +       };
 193 +
 194 +       eeprom@50 {
 195 +               compatible = "atmel,24c02";
 196 +               reg = <0x50>;
 197 +               pagesize = <16>;
 198 +       };
 199 +
 200 +       eeprom@51 {
 201 +               compatible = "atmel,24c02";
 202 +               reg = <0x51>;
 203 +               pagesize = <16>;
 204 +       };
 205 +
 206 +       eeprom@52 {
 207 +               compatible = "atmel,24c02";
 208 +               reg = <0x52>;
 209 +               pagesize = <16>;
 210 +       };
 211 +
 212 +       eeprom@53 {
 213 +               compatible = "atmel,24c02";
 214 +               reg = <0x53>;
 215 +               pagesize = <16>;
 216 +       };
 217 +
 218 +       rtc@68 {
 219 +               compatible = "dallas,ds1672";
 220 +               reg = <0x68>;
 221 +       };
 222 +};
 223 +
 224 +&i2c2 {
 225 +       clock-frequency = <100000>;
 226 +       pinctrl-names = "default";
 227 +       pinctrl-0 = <&pinctrl_i2c2>;
 228 +       status = "okay";
 229 +};
 230 +
 231 +&i2c3 {
 232 +       clock-frequency = <100000>;
 233 +       pinctrl-names = "default";
 234 +       pinctrl-0 = <&pinctrl_i2c3>;
 235 +       status = "okay";
 236 +
 237 +       gpio@20 {
 238 +               compatible = "nxp,pca9555";
 239 +               reg = <0x20>;
 240 +               gpio-controller;
 241 +               #gpio-cells = <2>;
 242 +       };
 243 +
 244 +       adc@48 {
 245 +               compatible = "ti,ads1015";
 246 +               reg = <0x48>;
 247 +               #address-cells = <1>;
 248 +               #size-cells = <0>;
 249 +
 250 +               channel@4 {
 251 +                       reg = <4>;
 252 +                       ti,gain = <0>;
 253 +                       ti,datarate = <5>;
 254 +               };
 255 +
 256 +               channel@5 {
 257 +                       reg = <5>;
 258 +                       ti,gain = <0>;
 259 +                       ti,datarate = <5>;
 260 +               };
 261 +
 262 +               channel@6 {
 263 +                       reg = <6>;
 264 +                       ti,gain = <0>;
 265 +                       ti,datarate = <5>;
 266 +               };
 267 +       };
 268 +};
 269 +
 270 +&pcie {
 271 +       pinctrl-names = "default";
 272 +       pinctrl-0 = <&pinctrl_pcie>;
 273 +       reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 274 +       status = "okay";
 275 +};
 276 +
 277 +&pwm2 {
 278 +       pinctrl-names = "default";
 279 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 280 +       status = "disabled";
 281 +};
 282 +
 283 +&pwm3 {
 284 +       pinctrl-names = "default";
 285 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 286 +       status = "disabled";
 287 +};
 288 +
 289 +&pwm4 {
 290 +       pinctrl-names = "default";
 291 +       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 292 +       status = "disabled";
 293 +};
 294 +
 295 +&uart1 {
 296 +       pinctrl-names = "default";
 297 +       pinctrl-0 = <&pinctrl_uart1>;
 298 +       status = "okay";
 299 +};
 300 +
 301 +&uart2 {
 302 +       pinctrl-names = "default";
 303 +       pinctrl-0 = <&pinctrl_uart2>;
 304 +       status = "okay";
 305 +};
 306 +
 307 +&uart3 {
 308 +       pinctrl-names = "default";
 309 +       pinctrl-0 = <&pinctrl_uart3>;
 310 +       status = "okay";
 311 +};
 312 +
 313 +&uart5 {
 314 +       pinctrl-names = "default";
 315 +       pinctrl-0 = <&pinctrl_uart5>;
 316 +       status = "okay";
 317 +};
 318 +
 319 +&usbotg {
 320 +       vbus-supply = <&reg_usb_otg_vbus>;
 321 +       pinctrl-names = "default";
 322 +       pinctrl-0 = <&pinctrl_usbotg>;
 323 +       disable-over-current;
 324 +       status = "okay";
 325 +};
 326 +
 327 +&usbh1 {
 328 +       status = "okay";
 329 +};
 330 +
 331 +&wdog1 {
 332 +       pinctrl-names = "default";
 333 +       pinctrl-0 = <&pinctrl_wdog>;
 334 +       fsl,ext-reset-output;
 335 +};
 336 +
 337 +&iomuxc {
 338 +       pinctrl_enet: enetgrp {
 339 +               fsl,pins = <
 340 +                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 341 +                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 342 +                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 343 +                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 344 +                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 345 +                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 346 +                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 347 +                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 348 +                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 349 +                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 350 +                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 351 +                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 352 +                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 353 +                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 354 +                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 355 +                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 356 +                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 357 +               >;
 358 +       };
 359 +
 360 +       pinctrl_gpio_leds: gpioledsgrp {
 361 +               fsl,pins = <
 362 +                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 363 +                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 364 +               >;
 365 +       };
 366 +
 367 +       pinctrl_gpmi_nand: gpminandgrp {
 368 +               fsl,pins = <
 369 +                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 370 +                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 371 +                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 372 +                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 373 +                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 374 +                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 375 +                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 376 +                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 377 +                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 378 +                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 379 +                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 380 +                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 381 +                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 382 +                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 383 +                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 384 +               >;
 385 +       };
 386 +
 387 +       pinctrl_i2c1: i2c1grp {
 388 +               fsl,pins = <
 389 +                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 390 +                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 391 +                       MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 392 +               >;
 393 +       };
 394 +
 395 +       pinctrl_i2c2: i2c2grp {
 396 +               fsl,pins = <
 397 +                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 398 +                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 399 +               >;
 400 +       };
 401 +
 402 +       pinctrl_i2c3: i2c3grp {
 403 +               fsl,pins = <
 404 +                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 405 +                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 406 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 407 +                       MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 408 +               >;
 409 +       };
 410 +
 411 +       pinctrl_pcie: pciegrp {
 412 +               fsl,pins = <
 413 +                       MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 414 +               >;
 415 +       };
 416 +
 417 +       pinctrl_pps: ppsgrp {
 418 +               fsl,pins = <
 419 +                       MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 420 +               >;
 421 +       };
 422 +
 423 +       pinctrl_pwm2: pwm2grp {
 424 +               fsl,pins = <
 425 +                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 426 +               >;
 427 +       };
 428 +
 429 +       pinctrl_pwm3: pwm3grp {
 430 +               fsl,pins = <
 431 +                       MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 432 +               >;
 433 +       };
 434 +
 435 +       pinctrl_pwm4: pwm4grp {
 436 +               fsl,pins = <
 437 +                       MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 438 +               >;
 439 +       };
 440 +
 441 +       pinctrl_uart1: uart1grp {
 442 +               fsl,pins = <
 443 +                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 444 +                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 445 +               >;
 446 +       };
 447 +
 448 +       pinctrl_uart2: uart2grp {
 449 +               fsl,pins = <
 450 +                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 451 +                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 452 +               >;
 453 +       };
 454 +
 455 +       pinctrl_uart3: uart3grp {
 456 +               fsl,pins = <
 457 +                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 458 +                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 459 +               >;
 460 +       };
 461 +
 462 +       pinctrl_uart5: uart5grp {
 463 +               fsl,pins = <
 464 +                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 465 +                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 466 +               >;
 467 +       };
 468 +
 469 +       pinctrl_usbotg: usbotggrp {
 470 +               fsl,pins = <
 471 +                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 472 +                       MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
 473 +               >;
 474 +       };
 475 +
 476 +       pinctrl_wdog: wdoggrp {
 477 +               fsl,pins = <
 478 +                       MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 479 +               >;
 480 +       };
 481 +};