target/linux/imx6/patches-3.10/0030-pcie-designware-fix-io-transfers.patch

   1 From: Pratyush Anand <pratyush.anand@st.com>
   2
   3 pp->io_base which is the input of the outbound IO address translation
   4 unit should be the cpu address, it was programmed wrongly to realio
   5 address.
   6
   7 We should pass global_io_offset rather than sys->io_offset to
   8 pci_ioremap_io, so we map the new window into the first available spot
   9 in the Linux view of the I/O space.
  10
  11 We must also pass cpu address instead  of realio address to
  12 pci_ioremap_io.
  13
  14 This patch fixes above issue. It has been tested with Lecroy PTC in AIC
  15 mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
  16 otherwise.
  17
  18 Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
  19 Tested-by: Mohit Kumar <mohit.kumar@st.com>
  20 Tested-by: Tim Harvey <tharvey@gateworks.com>
  21 Cc: Arnd Bergmann <arnd@arndb.de>
  22 Cc: Marek Vasut <marex@denx.de>
  23 Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
  24 Cc: linux-pci@vger.kernel.org
  25 Cc: spear-devel@list.st.com
  26 ---
  27  drivers/pci/host/pcie-designware.c |    5 ++---
  28  1 files changed, 2 insertions(+), 3 deletions(-)
  29
  30 http://thread.gmane.org/gmane.linux.kernel.pci/27204
  31
  32 --- a/drivers/pci/host/pcie-designware.c
  33 +++ b/drivers/pci/host/pcie-designware.c
  34 @@ -177,6 +177,7 @@ int __init dw_pcie_host_init(struct pcie
  35                                            + global_io_offset);
  36                         pp->config.io_size = resource_size(&pp->io);
  37                         pp->config.io_bus_addr = range.pci_addr;
  38 +                       pp->io_base = range.cpu_addr;
  39                 }
  40                 if (restype == IORESOURCE_MEM) {
  41                         of_pci_range_to_resource(&range, np, &pp->mem);
  42 @@ -202,7 +203,6 @@ int __init dw_pcie_host_init(struct pcie
  43
  44         pp->cfg0_base = pp->cfg.start;
  45         pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
  46 -       pp->io_base = pp->io.start;
  47         pp->mem_base = pp->mem.start;
  48
  49         pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
  50 @@ -449,7 +449,7 @@ int dw_pcie_setup(int nr, struct pci_sys
  51
  52         if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
  53                 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
  54 -               pci_ioremap_io(sys->io_offset, pp->io.start);
  55 +               pci_ioremap_io(global_io_offset, pp->io_base);
  56                 global_io_offset += SZ_64K;
  57                 pci_add_resource_offset(&sys->resources, &pp->io,
  58                                         sys->io_offset);