projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
octeon: disable edgerouter image
[openwrt/openwrt.git] / target / linux / imx6 / patches-4.19 / 004-ARM-dts-imx-Add-GW5912-board-support.patch
1 From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
2 From: Robert Jones <rjones@gateworks.com>
3 Date: Wed, 8 Jan 2020 07:44:24 -0800
4 Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
5
6 The Gateworks GW5912 is an IMX6 SoC based single board computer with:
7 - IMX6Q or IMX6DL
8 - 32bit DDR3 DRAM
9 - GbE RJ45 front-panel
10 - 4x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, mSATA
12 - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
13 - 10V to 60V DC input barrel jack
14 - 3axis accelerometer (lis2de12)
15 - GPS (ublox ZOE-M8Q)
16 - bi-color front-panel LED
17 - 256MB NAND boot device
18 - nanoSIM/microSD socket (with UHS-I support)
19 - user pushbutton
20 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
21 - CAN Bus transceiver (mcp2562)
22 - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
23 - off-board SPI connector (1x chip-select)
24
25 Signed-off-by: Robert Jones <rjones@gateworks.com>
26 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
27 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
28 ---
29 arch/arm/boot/dts/Makefile | 2 +
30 arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
31 arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
32 arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
33 4 files changed, 489 insertions(+)
34 create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
35 create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
36 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
37
38 --- a/arch/arm/boot/dts/Makefile
39 +++ b/arch/arm/boot/dts/Makefile
40 @@ -406,6 +406,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
41 imx6dl-gw5904.dtb \
42 imx6dl-gw5907.dtb \
43 imx6dl-gw5910.dtb \
44 + imx6dl-gw5912.dtb \
45 imx6dl-gw5913.dtb \
46 imx6dl-hummingboard.dtb \
47 imx6dl-hummingboard-emmc-som-v15.dtb \
48 @@ -476,6 +477,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
49 imx6q-gw5904.dtb \
50 imx6q-gw5907.dtb \
51 imx6q-gw5910.dtb \
52 + imx6q-gw5912.dtb \
53 imx6q-gw5913.dtb \
54 imx6q-h100.dtb \
55 imx6q-hummingboard.dtb \
56 --- /dev/null
57 +++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
58 @@ -0,0 +1,13 @@
59 +// SPDX-License-Identifier: GPL-2.0
60 +/*
61 + * Copyright 2019 Gateworks Corporation
62 + */
63 +
64 +/dts-v1/;
65 +#include "imx6dl.dtsi"
66 +#include "imx6qdl-gw5912.dtsi"
67 +
68 +/ {
69 + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
70 + compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
71 +};
72 --- /dev/null
73 +++ b/arch/arm/boot/dts/imx6q-gw5912.dts
74 @@ -0,0 +1,13 @@
75 +// SPDX-License-Identifier: GPL-2.0
76 +/*
77 + * Copyright 2019 Gateworks Corporation
78 + */
79 +
80 +/dts-v1/;
81 +#include "imx6q.dtsi"
82 +#include "imx6qdl-gw5912.dtsi"
83 +
84 +/ {
85 + model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
86 + compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
87 +};
88 --- /dev/null
89 +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
90 @@ -0,0 +1,461 @@
91 +// SPDX-License-Identifier: GPL-2.0
92 +/*
93 + * Copyright 2019 Gateworks Corporation
94 + */
95 +
96 +#include <dt-bindings/gpio/gpio.h>
97 +
98 +/ {
99 + /* these are used by bootloader for disabling nodes */
100 + aliases {
101 + led0 = &led0;
102 + led1 = &led1;
103 + led2 = &led2;
104 + nand = &gpmi;
105 + usb0 = &usbh1;
106 + usb1 = &usbotg;
107 + };
108 +
109 + chosen {
110 + stdout-path = &uart2;
111 + };
112 +
113 + leds {
114 + compatible = "gpio-leds";
115 + pinctrl-names = "default";
116 + pinctrl-0 = <&pinctrl_gpio_leds>;
117 +
118 + led0: user1 {
119 + label = "user1";
120 + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
121 + default-state = "on";
122 + linux,default-trigger = "heartbeat";
123 + };
124 +
125 + led1: user2 {
126 + label = "user2";
127 + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
128 + default-state = "off";
129 + };
130 +
131 + led2: user3 {
132 + label = "user3";
133 + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
134 + default-state = "off";
135 + };
136 + };
137 +
138 + memory@10000000 {
139 + device_type = "memory";
140 + reg = <0x10000000 0x40000000>;
141 + };
142 +
143 + pps {
144 + compatible = "pps-gpio";
145 + pinctrl-names = "default";
146 + pinctrl-0 = <&pinctrl_pps>;
147 + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
148 + };
149 +
150 + reg_3p3v: regulator-3p3v {
151 + compatible = "regulator-fixed";
152 + regulator-name = "3P3V";
153 + regulator-min-microvolt = <3300000>;
154 + regulator-max-microvolt = <3300000>;
155 + regulator-always-on;
156 + };
157 +
158 + reg_usb_vbus: regulator-5p0v {
159 + compatible = "regulator-fixed";
160 + regulator-name = "usb_vbus";
161 + regulator-min-microvolt = <5000000>;
162 + regulator-max-microvolt = <5000000>;
163 + regulator-always-on;
164 + };
165 +};
166 +
167 +&can1 {
168 + pinctrl-names = "default";
169 + pinctrl-0 = <&pinctrl_flexcan1>;
170 + status = "okay";
171 +};
172 +
173 +&ecspi2 {
174 + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
175 + pinctrl-names = "default";
176 + pinctrl-0 = <&pinctrl_ecspi2>;
177 + status = "okay";
178 +};
179 +
180 +&fec {
181 + pinctrl-names = "default";
182 + pinctrl-0 = <&pinctrl_enet>;
183 + phy-mode = "rgmii-id";
184 + status = "okay";
185 +};
186 +
187 +&gpmi {
188 + pinctrl-names = "default";
189 + pinctrl-0 = <&pinctrl_gpmi_nand>;
190 + status = "okay";
191 +};
192 +
193 +&i2c1 {
194 + clock-frequency = <100000>;
195 + pinctrl-names = "default";
196 + pinctrl-0 = <&pinctrl_i2c1>;
197 + status = "okay";
198 +
199 + gpio@23 {
200 + compatible = "nxp,pca9555";
201 + reg = <0x23>;
202 + gpio-controller;
203 + #gpio-cells = <2>;
204 + };
205 +
206 + eeprom@50 {
207 + compatible = "atmel,24c02";
208 + reg = <0x50>;
209 + pagesize = <16>;
210 + };
211 +
212 + eeprom@51 {
213 + compatible = "atmel,24c02";
214 + reg = <0x51>;
215 + pagesize = <16>;
216 + };
217 +
218 + eeprom@52 {
219 + compatible = "atmel,24c02";
220 + reg = <0x52>;
221 + pagesize = <16>;
222 + };
223 +
224 + eeprom@53 {
225 + compatible = "atmel,24c02";
226 + reg = <0x53>;
227 + pagesize = <16>;
228 + };
229 +
230 + rtc@68 {
231 + compatible = "dallas,ds1672";
232 + reg = <0x68>;
233 + };
234 +};
235 +
236 +&i2c2 {
237 + clock-frequency = <100000>;
238 + pinctrl-names = "default";
239 + pinctrl-0 = <&pinctrl_i2c2>;
240 + status = "okay";
241 +};
242 +
243 +&i2c3 {
244 + clock-frequency = <100000>;
245 + pinctrl-names = "default";
246 + pinctrl-0 = <&pinctrl_i2c3>;
247 + status = "okay";
248 +
249 + accel@19 {
250 + pinctrl-names = "default";
251 + pinctrl-0 = <&pinctrl_accel>;
252 + compatible = "st,lis2de12";
253 + reg = <0x19>;
254 + st,drdy-int-pin = <1>;
255 + interrupt-parent = <&gpio7>;
256 + interrupts = <13 0>;
257 + interrupt-names = "INT1";
258 + };
259 +};
260 +
261 +&pcie {
262 + pinctrl-names = "default";
263 + pinctrl-0 = <&pinctrl_pcie>;
264 + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
265 + status = "okay";
266 +};
267 +
268 +&pwm1 {
269 + pinctrl-names = "default";
270 + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
271 + status = "disabled";
272 +};
273 +
274 +&pwm2 {
275 + pinctrl-names = "default";
276 + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
277 + status = "disabled";
278 +};
279 +
280 +&pwm3 {
281 + pinctrl-names = "default";
282 + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
283 + status = "disabled";
284 +};
285 +
286 +&pwm4 {
287 + pinctrl-names = "default";
288 + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
289 + status = "disabled";
290 +};
291 +
292 +&uart1 {
293 + pinctrl-names = "default";
294 + pinctrl-0 = <&pinctrl_uart1>;
295 + rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
296 + status = "okay";
297 +};
298 +
299 +&uart2 {
300 + pinctrl-names = "default";
301 + pinctrl-0 = <&pinctrl_uart2>;
302 + status = "okay";
303 +};
304 +
305 +&uart5 {
306 + pinctrl-names = "default";
307 + pinctrl-0 = <&pinctrl_uart5>;
308 + status = "okay";
309 +};
310 +
311 +&usbotg {
312 + vbus-supply = <&reg_usb_vbus>;
313 + pinctrl-names = "default";
314 + pinctrl-0 = <&pinctrl_usbotg>;
315 + disable-over-current;
316 + dr_mode = "host";
317 + status = "okay";
318 +};
319 +
320 +&usbh1 {
321 + vbus-supply = <&reg_usb_vbus>;
322 + status = "okay";
323 +};
324 +
325 +&usdhc3 {
326 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
327 + pinctrl-0 = <&pinctrl_usdhc3>;
328 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
329 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
330 + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
331 + vmmc-supply = <&reg_3p3v>;
332 + no-1-8-v; /* firmware will remove if board revision supports */
333 + status = "okay";
334 +};
335 +
336 +&wdog1 {
337 + status = "disabled";
338 +};
339 +
340 +&wdog2 {
341 + pinctrl-names = "default";
342 + pinctrl-0 = <&pinctrl_wdog>;
343 + fsl,ext-reset-output;
344 + status = "okay";
345 +};
346 +
347 +&iomuxc {
348 + pinctrl_accel: accelmuxgrp {
349 + fsl,pins = <
350 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
351 + >;
352 + };
353 +
354 + pinctrl_enet: enetgrp {
355 + fsl,pins = <
356 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
357 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
358 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
359 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
360 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
361 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
362 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
363 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
364 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
365 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
366 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
367 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
368 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
369 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
370 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
371 + >;
372 + };
373 +
374 + pinctrl_ecspi2: escpi2grp {
375 + fsl,pins = <
376 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
377 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
378 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
379 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
380 + >;
381 + };
382 +
383 + pinctrl_flexcan1: flexcan1grp {
384 + fsl,pins = <
385 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
386 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
387 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
388 + >;
389 + };
390 +
391 + pinctrl_gpio_leds: gpioledsgrp {
392 + fsl,pins = <
393 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
394 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
395 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
396 + >;
397 + };
398 +
399 + pinctrl_gpmi_nand: gpminandgrp {
400 + fsl,pins = <
401 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
402 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
403 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
404 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
405 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
406 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
407 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
408 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
409 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
410 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
411 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
412 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
413 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
414 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
415 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
416 + >;
417 + };
418 +
419 + pinctrl_i2c1: i2c1grp {
420 + fsl,pins = <
421 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
422 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
423 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
424 + >;
425 + };
426 +
427 + pinctrl_i2c2: i2c2grp {
428 + fsl,pins = <
429 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
430 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
431 + >;
432 + };
433 +
434 + pinctrl_i2c3: i2c3grp {
435 + fsl,pins = <
436 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
437 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
438 + >;
439 + };
440 +
441 + pinctrl_pcie: pciegrp {
442 + fsl,pins = <
443 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
444 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
445 + >;
446 + };
447 +
448 + pinctrl_pps: ppsgrp {
449 + fsl,pins = <
450 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
451 + >;
452 + };
453 +
454 + pinctrl_pwm1: pwm1grp {
455 + fsl,pins = <
456 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
457 + >;
458 + };
459 +
460 + pinctrl_pwm2: pwm2grp {
461 + fsl,pins = <
462 + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
463 + >;
464 + };
465 +
466 + pinctrl_pwm3: pwm3grp {
467 + fsl,pins = <
468 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
469 + >;
470 + };
471 +
472 + pinctrl_pwm4: pwm4grp {
473 + fsl,pins = <
474 + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
475 + >;
476 + };
477 +
478 + pinctrl_uart1: uart1grp {
479 + fsl,pins = <
480 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
481 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
482 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
483 + >;
484 + };
485 +
486 + pinctrl_uart2: uart2grp {
487 + fsl,pins = <
488 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
489 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
490 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
491 + >;
492 + };
493 +
494 + pinctrl_uart5: uart5grp {
495 + fsl,pins = <
496 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
497 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
498 + >;
499 + };
500 +
501 + pinctrl_usbotg: usbotggrp {
502 + fsl,pins = <
503 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
504 + >;
505 + };
506 +
507 + pinctrl_usdhc3: usdhc3grp {
508 + fsl,pins = <
509 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
510 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
511 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
512 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
513 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
514 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
515 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
516 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
517 + >;
518 + };
519 +
520 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
521 + fsl,pins = <
522 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
523 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
524 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
525 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
526 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
527 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
528 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
529 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
530 + >;
531 + };
532 +
533 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
534 + fsl,pins = <
535 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
536 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
537 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
538 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
539 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
540 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
541 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
542 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
543 + >;
544 + };
545 +
546 + pinctrl_wdog: wdoggrp {
547 + fsl,pins = <
548 + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
549 + >;
550 + };
551 +};
OpenWrt Source Repository