target/linux/imx6/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch

   1 From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001
   2 From: Tim Harvey <tharvey@gateworks.com>
   3 Date: Wed, 8 Jan 2020 07:44:22 -0800
   4 Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support
   5
   6 The Gateworks GW5910 is an IMX6 SoC based single board computer with:
   7  - IMX6Q or IMX6DL
   8  - 32bit DDR3 DRAM
   9  - FEC GbE RJ45 front-panel
  10  - 1x miniPCIe socket with PCI Gen2, USB2
  11  - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
  12  - 5V to 60V DC input barrel jack
  13  - 3axis accelerometer (lis2de12)
  14  - GPS (ublox ZOE-M8Q)
  15  - bi-color front-panel LED
  16  - 256MB NAND boot device
  17  - microSD socket (with UHS-I support)
  18  - user pushbutton
  19  - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  20  - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
  21  - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
  22  - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
  23  - off-board SPI connector (1x chip-select)
  24
  25 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  26 Signed-off-by: Robert Jones <rjones@gateworks.com>
  27 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  28 ---
  29  arch/arm/boot/dts/Makefile            |   2 +
  30  arch/arm/boot/dts/imx6dl-gw5910.dts   |  14 +
  31  arch/arm/boot/dts/imx6q-gw5910.dts    |  14 +
  32  arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++
  33  4 files changed, 521 insertions(+)
  34  create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts
  35  create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts
  36  create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  37
  38 --- a/arch/arm/boot/dts/Makefile
  39 +++ b/arch/arm/boot/dts/Makefile
  40 @@ -419,6 +419,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  41         imx6dl-gw5903.dtb \
  42         imx6dl-gw5904.dtb \
  43         imx6dl-gw5907.dtb \
  44 +       imx6dl-gw5910.dtb \
  45         imx6dl-hummingboard.dtb \
  46         imx6dl-hummingboard-emmc-som-v15.dtb \
  47         imx6dl-hummingboard-som-v15.dtb \
  48 @@ -491,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  49         imx6q-gw5903.dtb \
  50         imx6q-gw5904.dtb \
  51         imx6q-gw5907.dtb \
  52 +       imx6q-gw5910.dtb \
  53         imx6q-h100.dtb \
  54         imx6q-hummingboard.dtb \
  55         imx6q-hummingboard-emmc-som-v15.dtb \
  56 --- /dev/null
  57 +++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
  58 @@ -0,0 +1,14 @@
  59 +// SPDX-License-Identifier: GPL-2.0
  60 +/*
  61 + * Copyright 2019 Gateworks Corporation
  62 + */
  63 +
  64 +/dts-v1/;
  65 +
  66 +#include "imx6dl.dtsi"
  67 +#include "imx6qdl-gw5910.dtsi"
  68 +
  69 +/ {
  70 +       model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
  71 +       compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
  72 +};
  73 --- /dev/null
  74 +++ b/arch/arm/boot/dts/imx6q-gw5910.dts
  75 @@ -0,0 +1,14 @@
  76 +// SPDX-License-Identifier: GPL-2.0
  77 +/*
  78 + * Copyright 2019 Gateworks Corporation
  79 + */
  80 +
  81 +/dts-v1/;
  82 +
  83 +#include "imx6q.dtsi"
  84 +#include "imx6qdl-gw5910.dtsi"
  85 +
  86 +/ {
  87 +       model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
  88 +       compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
  89 +};
  90 --- /dev/null
  91 +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  92 @@ -0,0 +1,491 @@
  93 +// SPDX-License-Identifier: GPL-2.0
  94 +/*
  95 + * Copyright 2019 Gateworks Corporation
  96 + */
  97 +
  98 +#include <dt-bindings/gpio/gpio.h>
  99 +
 100 +/ {
 101 +       /* these are used by bootloader for disabling nodes */
 102 +       aliases {
 103 +               led0 = &led0;
 104 +               led1 = &led1;
 105 +               led2 = &led2;
 106 +       };
 107 +
 108 +       chosen {
 109 +               stdout-path = &uart2;
 110 +       };
 111 +
 112 +       memory@10000000 {
 113 +               device_type = "memory";
 114 +               reg = <0x10000000 0x20000000>;
 115 +       };
 116 +
 117 +       leds {
 118 +               compatible = "gpio-leds";
 119 +               pinctrl-names = "default";
 120 +               pinctrl-0 = <&pinctrl_gpio_leds>;
 121 +
 122 +               led0: user1 {
 123 +                       label = "user1";
 124 +                       gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 125 +                       default-state = "on";
 126 +                       linux,default-trigger = "heartbeat";
 127 +               };
 128 +
 129 +               led1: user2 {
 130 +                       label = "user2";
 131 +                       gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 132 +                       default-state = "off";
 133 +               };
 134 +
 135 +               led2: user3 {
 136 +                       label = "user3";
 137 +                       gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 138 +                       default-state = "off";
 139 +               };
 140 +       };
 141 +
 142 +       pps {
 143 +               compatible = "pps-gpio";
 144 +               pinctrl-names = "default";
 145 +               pinctrl-0 = <&pinctrl_pps>;
 146 +               gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 147 +               status = "okay";
 148 +       };
 149 +
 150 +       reg_3p3v: regulator-3p3v {
 151 +               compatible = "regulator-fixed";
 152 +               regulator-name = "3P3V";
 153 +               regulator-min-microvolt = <3300000>;
 154 +               regulator-max-microvolt = <3300000>;
 155 +               regulator-always-on;
 156 +       };
 157 +
 158 +       reg_5p0v: regulator-5p0v {
 159 +               compatible = "regulator-fixed";
 160 +               regulator-name = "5P0V";
 161 +               regulator-min-microvolt = <5000000>;
 162 +               regulator-max-microvolt = <5000000>;
 163 +               regulator-always-on;
 164 +       };
 165 +
 166 +       reg_wl: regulator-wl {
 167 +               pinctrl-names = "default";
 168 +               pinctrl-0 = <&pinctrl_reg_wl>;
 169 +               compatible = "regulator-fixed";
 170 +               regulator-name = "wl";
 171 +               gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 172 +               startup-delay-us = <100>;
 173 +               enable-active-high;
 174 +               regulator-min-microvolt = <3300000>;
 175 +               regulator-max-microvolt = <3300000>;
 176 +               regulator-always-on;
 177 +       };
 178 +
 179 +       reg_bt: regulator-bt {
 180 +               pinctrl-names = "default";
 181 +               pinctrl-0 = <&pinctrl_reg_bt>;
 182 +               compatible = "regulator-fixed";
 183 +               regulator-name = "bt";
 184 +               gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 185 +               startup-delay-us = <100>;
 186 +               enable-active-high;
 187 +               regulator-min-microvolt = <3300000>;
 188 +               regulator-max-microvolt = <3300000>;
 189 +               regulator-always-on;
 190 +       };
 191 +};
 192 +
 193 +
 194 +&ecspi3 {
 195 +       cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 196 +       pinctrl-names = "default";
 197 +       pinctrl-0 = <&pinctrl_ecspi3>;
 198 +       status = "okay";
 199 +};
 200 +
 201 +&fec {
 202 +       pinctrl-names = "default";
 203 +       pinctrl-0 = <&pinctrl_enet>;
 204 +       phy-mode = "rgmii-id";
 205 +       status = "okay";
 206 +};
 207 +
 208 +&gpmi {
 209 +       pinctrl-names = "default";
 210 +       pinctrl-0 = <&pinctrl_gpmi_nand>;
 211 +       status = "okay";
 212 +};
 213 +
 214 +&i2c1 {
 215 +       clock-frequency = <100000>;
 216 +       pinctrl-names = "default";
 217 +       pinctrl-0 = <&pinctrl_i2c1>;
 218 +       status = "okay";
 219 +
 220 +       gpio@23 {
 221 +               compatible = "nxp,pca9555";
 222 +               reg = <0x23>;
 223 +               gpio-controller;
 224 +               #gpio-cells = <2>;
 225 +       };
 226 +
 227 +       eeprom@50 {
 228 +               compatible = "atmel,24c02";
 229 +               reg = <0x50>;
 230 +               pagesize = <16>;
 231 +       };
 232 +
 233 +       eeprom@51 {
 234 +               compatible = "atmel,24c02";
 235 +               reg = <0x51>;
 236 +               pagesize = <16>;
 237 +       };
 238 +
 239 +       eeprom@52 {
 240 +               compatible = "atmel,24c02";
 241 +               reg = <0x52>;
 242 +               pagesize = <16>;
 243 +       };
 244 +
 245 +       eeprom@53 {
 246 +               compatible = "atmel,24c02";
 247 +               reg = <0x53>;
 248 +               pagesize = <16>;
 249 +       };
 250 +
 251 +       rtc@68 {
 252 +               compatible = "dallas,ds1672";
 253 +               reg = <0x68>;
 254 +       };
 255 +};
 256 +
 257 +&i2c2 {
 258 +       clock-frequency = <100000>;
 259 +       pinctrl-names = "default";
 260 +       pinctrl-0 = <&pinctrl_i2c2>;
 261 +       status = "okay";
 262 +};
 263 +
 264 +&i2c3 {
 265 +       clock-frequency = <100000>;
 266 +       pinctrl-names = "default";
 267 +       pinctrl-0 = <&pinctrl_i2c3>;
 268 +       status = "okay";
 269 +
 270 +       accel@19 {
 271 +               pinctrl-names = "default";
 272 +               pinctrl-0 = <&pinctrl_accel>;
 273 +               compatible = "st,lis2de12";
 274 +               reg = <0x19>;
 275 +               st,drdy-int-pin = <1>;
 276 +               interrupt-parent = <&gpio7>;
 277 +               interrupts = <13 0>;
 278 +               interrupt-names = "INT1";
 279 +       };
 280 +};
 281 +
 282 +&pcie {
 283 +       pinctrl-names = "default";
 284 +       pinctrl-0 = <&pinctrl_pcie>;
 285 +       reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
 286 +       status = "okay";
 287 +};
 288 +
 289 +&pwm2 {
 290 +       pinctrl-names = "default";
 291 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 292 +       status = "disabled";
 293 +};
 294 +
 295 +&pwm3 {
 296 +       pinctrl-names = "default";
 297 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 298 +       status = "disabled";
 299 +};
 300 +
 301 +/* off-board RS232 */
 302 +&uart1 {
 303 +       pinctrl-names = "default";
 304 +       pinctrl-0 = <&pinctrl_uart1>;
 305 +       status = "okay";
 306 +};
 307 +
 308 +/* serial console */
 309 +&uart2 {
 310 +       pinctrl-names = "default";
 311 +       pinctrl-0 = <&pinctrl_uart2>;
 312 +       status = "okay";
 313 +};
 314 +
 315 +/* Sterling-LWB Bluetooth */
 316 +&uart4 {
 317 +       pinctrl-names = "default";
 318 +       pinctrl-0 = <&pinctrl_uart4>;
 319 +       uart-has-rtscts;
 320 +       status = "okay";
 321 +};
 322 +
 323 +/* GPS */
 324 +&uart5 {
 325 +       pinctrl-names = "default";
 326 +       pinctrl-0 = <&pinctrl_uart5>;
 327 +       status = "okay";
 328 +};
 329 +
 330 +&usbotg {
 331 +       vbus-supply = <&reg_5p0v>;
 332 +       pinctrl-names = "default";
 333 +       pinctrl-0 = <&pinctrl_usbotg>;
 334 +       disable-over-current;
 335 +       status = "okay";
 336 +};
 337 +
 338 +&usbh1 {
 339 +       status = "okay";
 340 +};
 341 +
 342 +/* Sterling-LWB SDIO WiFi */
 343 +&usdhc2 {
 344 +       pinctrl-names = "default";
 345 +       pinctrl-0 = <&pinctrl_usdhc2>;
 346 +       vmmc-supply = <&reg_3p3v>;
 347 +       non-removable;
 348 +       bus-width = <4>;
 349 +       status = "okay";
 350 +};
 351 +
 352 +&usdhc3 {
 353 +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
 354 +       pinctrl-0 = <&pinctrl_usdhc3>;
 355 +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 356 +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 357 +       cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 358 +       vmmc-supply = <&reg_3p3v>;
 359 +       status = "okay";
 360 +};
 361 +
 362 +&wdog1 {
 363 +       pinctrl-names = "default";
 364 +       pinctrl-0 = <&pinctrl_wdog>;
 365 +       fsl,ext-reset-output;
 366 +};
 367 +
 368 +&iomuxc {
 369 +       pinctrl_accel: accelmuxgrp {
 370 +               fsl,pins = <
 371 +                       MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 372 +               >;
 373 +       };
 374 +
 375 +       pinctrl_ecspi3: escpi3grp {
 376 +               fsl,pins = <
 377 +                       MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 378 +                       MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 379 +                       MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 380 +                       MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 381 +               >;
 382 +       };
 383 +
 384 +       pinctrl_enet: enetgrp {
 385 +               fsl,pins = <
 386 +                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 387 +                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 388 +                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 389 +                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 390 +                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 391 +                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 392 +                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 393 +                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 394 +                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 395 +                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 396 +                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 397 +                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 398 +                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 399 +                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 400 +                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 401 +                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 402 +                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 403 +               >;
 404 +       };
 405 +
 406 +       pinctrl_gpio_leds: gpioledsgrp {
 407 +               fsl,pins = <
 408 +                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 409 +                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 410 +                       MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 411 +               >;
 412 +       };
 413 +
 414 +       pinctrl_gpmi_nand: gpminandgrp {
 415 +               fsl,pins = <
 416 +                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 417 +                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 418 +                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 419 +                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 420 +                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 421 +                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 422 +                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 423 +                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 424 +                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 425 +                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 426 +                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 427 +                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 428 +                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 429 +                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 430 +                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 431 +               >;
 432 +       };
 433 +
 434 +       pinctrl_i2c1: i2c1grp {
 435 +               fsl,pins = <
 436 +                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 437 +                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 438 +                       MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 439 +               >;
 440 +       };
 441 +
 442 +       pinctrl_i2c2: i2c2grp {
 443 +               fsl,pins = <
 444 +                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 445 +                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 446 +               >;
 447 +       };
 448 +
 449 +       pinctrl_i2c3: i2c3grp {
 450 +               fsl,pins = <
 451 +                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 452 +                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 453 +               >;
 454 +       };
 455 +
 456 +       pinctrl_pcie: pciegrp {
 457 +               fsl,pins = <
 458 +                       MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 459 +               >;
 460 +       };
 461 +
 462 +       pinctrl_pps: ppsgrp {
 463 +               fsl,pins = <
 464 +                       MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16     0x1b0b1
 465 +               >;
 466 +       };
 467 +
 468 +       pinctrl_pwm2: pwm2grp {
 469 +               fsl,pins = <
 470 +                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 471 +               >;
 472 +       };
 473 +
 474 +       pinctrl_pwm3: pwm3grp {
 475 +               fsl,pins = <
 476 +                       MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 477 +               >;
 478 +       };
 479 +
 480 +       pinctrl_reg_bt: regbtgrp {
 481 +               fsl,pins = <
 482 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
 483 +               >;
 484 +       };
 485 +
 486 +       pinctrl_reg_wl: regwlgrp {
 487 +               fsl,pins = <
 488 +                       MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 489 +               >;
 490 +       };
 491 +
 492 +       pinctrl_uart1: uart1grp {
 493 +               fsl,pins = <
 494 +                       MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 495 +                       MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 496 +               >;
 497 +       };
 498 +
 499 +       pinctrl_uart2: uart2grp {
 500 +               fsl,pins = <
 501 +                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 502 +                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 503 +               >;
 504 +       };
 505 +
 506 +       pinctrl_uart4: uart4grp {
 507 +               fsl,pins = <
 508 +                       MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 509 +                       MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 510 +                       MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 511 +                       MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 512 +               >;
 513 +       };
 514 +
 515 +       pinctrl_uart5: uart5grp {
 516 +               fsl,pins = <
 517 +                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 518 +                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 519 +               >;
 520 +       };
 521 +
 522 +       pinctrl_usbotg: usbotggrp {
 523 +               fsl,pins = <
 524 +                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 525 +               >;
 526 +       };
 527 +
 528 +       pinctrl_usdhc2: usdhc2grp {
 529 +               fsl,pins = <
 530 +                       MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 531 +                       MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 532 +                       MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 533 +                       MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 534 +                       MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 535 +                       MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 536 +               >;
 537 +       };
 538 +
 539 +       pinctrl_usdhc3: usdhc3grp {
 540 +               fsl,pins = <
 541 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 542 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 543 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 544 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 545 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 546 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 547 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 548 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 549 +               >;
 550 +       };
 551 +
 552 +       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 553 +               fsl,pins = <
 554 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 555 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 556 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 557 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 558 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 559 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 560 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 561 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 562 +               >;
 563 +       };
 564 +
 565 +       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 566 +               fsl,pins = <
 567 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 568 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 569 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 570 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 571 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 572 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 573 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 574 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 575 +               >;
 576 +       };
 577 +
 578 +       pinctrl_wdog: wdoggrp {
 579 +               fsl,pins = <
 580 +                       MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 581 +               >;
 582 +       };
 583 +};