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imx6: backport v5.8 imx6qdl-gw dt patches
[openwrt/openwrt.git] / target / linux / imx6 / patches-5.4 / 003-ARM-dts-imx-Add-GW5913-board-support.patch
1 From 169e12f99cf9d5fce752564f32fd8df96461de43 Mon Sep 17 00:00:00 2001
2 From: Robert Jones <rjones@gateworks.com>
3 Date: Wed, 8 Jan 2020 07:44:23 -0800
4 Subject: [PATCH 3/4] ARM: dts: imx: Add GW5913 board support
5
6 The Gateworks GW5913 is an IMX6 SoC based single board computer with:
7 - IMX6Q or IMX6DL
8 - 32bit DDR3 DRAM
9 - FEC GbE RJ45 front-panel
10 - 1x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
12 - 6V to 60V DC input connector
13 - GPS (ublox ZOE-M8Q)
14 - bi-color front-panel LED
15 - 256MB NAND boot device
16 - nanoSIM socket
17 - user pushbutton
18 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
19
20 Signed-off-by: Robert Jones <rjones@gateworks.com>
21 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
22 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
23 ---
24 arch/arm/boot/dts/Makefile | 2 +
25 arch/arm/boot/dts/imx6dl-gw5913.dts | 14 ++
26 arch/arm/boot/dts/imx6q-gw5913.dts | 14 ++
27 arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 348 ++++++++++++++++++++++++++++++++++
28 4 files changed, 378 insertions(+)
29 create mode 100644 arch/arm/boot/dts/imx6dl-gw5913.dts
30 create mode 100644 arch/arm/boot/dts/imx6q-gw5913.dts
31 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5913.dtsi
32
33 --- a/arch/arm/boot/dts/Makefile
34 +++ b/arch/arm/boot/dts/Makefile
35 @@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
36 imx6dl-gw5904.dtb \
37 imx6dl-gw5907.dtb \
38 imx6dl-gw5910.dtb \
39 + imx6dl-gw5913.dtb \
40 imx6dl-hummingboard.dtb \
41 imx6dl-hummingboard-emmc-som-v15.dtb \
42 imx6dl-hummingboard-som-v15.dtb \
43 @@ -493,6 +494,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
44 imx6q-gw5904.dtb \
45 imx6q-gw5907.dtb \
46 imx6q-gw5910.dtb \
47 + imx6q-gw5913.dtb \
48 imx6q-h100.dtb \
49 imx6q-hummingboard.dtb \
50 imx6q-hummingboard-emmc-som-v15.dtb \
51 --- /dev/null
52 +++ b/arch/arm/boot/dts/imx6dl-gw5913.dts
53 @@ -0,0 +1,14 @@
54 +// SPDX-License-Identifier: GPL-2.0
55 +/*
56 + * Copyright 2019 Gateworks Corporation
57 + */
58 +
59 +/dts-v1/;
60 +
61 +#include "imx6dl.dtsi"
62 +#include "imx6qdl-gw5913.dtsi"
63 +
64 +/ {
65 + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
66 + compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
67 +};
68 --- /dev/null
69 +++ b/arch/arm/boot/dts/imx6q-gw5913.dts
70 @@ -0,0 +1,14 @@
71 +// SPDX-License-Identifier: GPL-2.0
72 +/*
73 + * Copyright 2019 Gateworks Corporation
74 + */
75 +
76 +/dts-v1/;
77 +
78 +#include "imx6q.dtsi"
79 +#include "imx6qdl-gw5913.dtsi"
80 +
81 +/ {
82 + model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
83 + compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
84 +};
85 --- /dev/null
86 +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
87 @@ -0,0 +1,348 @@
88 +// SPDX-License-Identifier: GPL-2.0
89 +/*
90 + * Copyright 2019 Gateworks Corporation
91 + */
92 +
93 +#include <dt-bindings/gpio/gpio.h>
94 +
95 +/ {
96 + /* these are used by bootloader for disabling nodes */
97 + aliases {
98 + led0 = &led0;
99 + led1 = &led1;
100 + nand = &gpmi;
101 + usb0 = &usbh1;
102 + usb1 = &usbotg;
103 + };
104 +
105 + chosen {
106 + stdout-path = &uart2;
107 + };
108 +
109 + leds {
110 + compatible = "gpio-leds";
111 + pinctrl-names = "default";
112 + pinctrl-0 = <&pinctrl_gpio_leds>;
113 +
114 + led0: user1 {
115 + label = "user1";
116 + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
117 + default-state = "on";
118 + linux,default-trigger = "heartbeat";
119 + };
120 +
121 + led1: user2 {
122 + label = "user2";
123 + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
124 + default-state = "off";
125 + };
126 + };
127 +
128 + memory@10000000 {
129 + device_type = "memory";
130 + reg = <0x10000000 0x20000000>;
131 + };
132 +
133 + pps {
134 + compatible = "pps-gpio";
135 + pinctrl-names = "default";
136 + pinctrl-0 = <&pinctrl_pps>;
137 + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
138 + status = "okay";
139 + };
140 +
141 + reg_3p3v: regulator-3p3v {
142 + compatible = "regulator-fixed";
143 + regulator-name = "3P3V";
144 + regulator-min-microvolt = <3300000>;
145 + regulator-max-microvolt = <3300000>;
146 + regulator-always-on;
147 + };
148 +
149 + reg_5p0v: regulator-5p0v {
150 + compatible = "regulator-fixed";
151 + regulator-name = "5P0V";
152 + regulator-min-microvolt = <5000000>;
153 + regulator-max-microvolt = <5000000>;
154 + regulator-always-on;
155 + };
156 +};
157 +
158 +&fec {
159 + pinctrl-names = "default";
160 + pinctrl-0 = <&pinctrl_enet>;
161 + phy-mode = "rgmii-id";
162 + status = "okay";
163 +};
164 +
165 +&gpmi {
166 + pinctrl-names = "default";
167 + pinctrl-0 = <&pinctrl_gpmi_nand>;
168 + status = "okay";
169 +};
170 +
171 +&i2c1 {
172 + clock-frequency = <100000>;
173 + pinctrl-names = "default";
174 + pinctrl-0 = <&pinctrl_i2c1>;
175 + status = "okay";
176 +
177 + gpio@23 {
178 + compatible = "nxp,pca9555";
179 + reg = <0x23>;
180 + gpio-controller;
181 + #gpio-cells = <2>;
182 + };
183 +
184 + eeprom@50 {
185 + compatible = "atmel,24c02";
186 + reg = <0x50>;
187 + pagesize = <16>;
188 + };
189 +
190 + eeprom@51 {
191 + compatible = "atmel,24c02";
192 + reg = <0x51>;
193 + pagesize = <16>;
194 + };
195 +
196 + eeprom@52 {
197 + compatible = "atmel,24c02";
198 + reg = <0x52>;
199 + pagesize = <16>;
200 + };
201 +
202 + eeprom@53 {
203 + compatible = "atmel,24c02";
204 + reg = <0x53>;
205 + pagesize = <16>;
206 + };
207 +
208 + rtc@68 {
209 + compatible = "dallas,ds1672";
210 + reg = <0x68>;
211 + };
212 +};
213 +
214 +&i2c2 {
215 + clock-frequency = <100000>;
216 + pinctrl-names = "default";
217 + pinctrl-0 = <&pinctrl_i2c2>;
218 + status = "okay";
219 +};
220 +
221 +&i2c3 {
222 + clock-frequency = <100000>;
223 + pinctrl-names = "default";
224 + pinctrl-0 = <&pinctrl_i2c3>;
225 + status = "okay";
226 +};
227 +
228 +&pcie {
229 + pinctrl-names = "default";
230 + pinctrl-0 = <&pinctrl_pcie>;
231 + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
232 + status = "okay";
233 +};
234 +
235 +&pwm2 {
236 + pinctrl-names = "default";
237 + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
238 + status = "disabled";
239 +};
240 +
241 +&pwm3 {
242 + pinctrl-names = "default";
243 + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
244 + status = "disabled";
245 +};
246 +
247 +&pwm4 {
248 + pinctrl-names = "default";
249 + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
250 + status = "disabled";
251 +};
252 +
253 +&uart1 {
254 + pinctrl-names = "default";
255 + pinctrl-0 = <&pinctrl_uart1>;
256 + status = "okay";
257 +};
258 +
259 +&uart2 {
260 + pinctrl-names = "default";
261 + pinctrl-0 = <&pinctrl_uart2>;
262 + status = "okay";
263 +};
264 +
265 +&uart3 {
266 + pinctrl-names = "default";
267 + pinctrl-0 = <&pinctrl_uart3>;
268 + status = "okay";
269 +};
270 +
271 +&uart5 {
272 + pinctrl-names = "default";
273 + pinctrl-0 = <&pinctrl_uart5>;
274 + status = "okay";
275 +};
276 +
277 +&usbotg {
278 + pinctrl-names = "default";
279 + pinctrl-0 = <&pinctrl_usbotg>;
280 + disable-over-current;
281 + status = "okay";
282 +};
283 +
284 +&usbh1 {
285 + status = "okay";
286 +};
287 +
288 +&wdog1 {
289 + pinctrl-names = "default";
290 + pinctrl-0 = <&pinctrl_wdog>;
291 + fsl,ext-reset-output;
292 +};
293 +
294 +&iomuxc {
295 + pinctrl_enet: enetgrp {
296 + fsl,pins = <
297 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
298 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
299 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
300 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
301 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
302 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
303 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
304 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
305 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
306 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
307 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
308 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
309 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
310 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
311 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
312 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
313 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
314 + >;
315 + };
316 +
317 + pinctrl_gpio_leds: gpioledsgrp {
318 + fsl,pins = <
319 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
320 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
321 + >;
322 + };
323 +
324 + pinctrl_gpmi_nand: gpminandgrp {
325 + fsl,pins = <
326 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
327 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
328 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
329 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
330 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
331 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
332 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
333 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
334 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
335 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
336 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
337 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
338 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
339 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
340 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
341 + >;
342 + };
343 +
344 + pinctrl_i2c1: i2c1grp {
345 + fsl,pins = <
346 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
347 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
348 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
349 + >;
350 + };
351 +
352 + pinctrl_i2c2: i2c2grp {
353 + fsl,pins = <
354 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
355 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
356 + >;
357 + };
358 +
359 + pinctrl_i2c3: i2c3grp {
360 + fsl,pins = <
361 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
362 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
363 + >;
364 + };
365 +
366 + pinctrl_pcie: pciegrp {
367 + fsl,pins = <
368 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
369 + >;
370 + };
371 +
372 + pinctrl_pps: ppsgrp {
373 + fsl,pins = <
374 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
375 + >;
376 + };
377 +
378 + pinctrl_pwm2: pwm2grp {
379 + fsl,pins = <
380 + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
381 + >;
382 + };
383 +
384 + pinctrl_pwm3: pwm3grp {
385 + fsl,pins = <
386 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
387 + >;
388 + };
389 +
390 + pinctrl_pwm4: pwm4grp {
391 + fsl,pins = <
392 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
393 + >;
394 + };
395 +
396 + pinctrl_uart1: uart1grp {
397 + fsl,pins = <
398 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
399 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
400 + >;
401 + };
402 +
403 + pinctrl_uart2: uart2grp {
404 + fsl,pins = <
405 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
406 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
407 + >;
408 + };
409 +
410 + pinctrl_uart3: uart3grp {
411 + fsl,pins = <
412 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
413 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
414 + >;
415 + };
416 +
417 + pinctrl_uart5: uart5grp {
418 + fsl,pins = <
419 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
420 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
421 + >;
422 + };
423 +
424 + pinctrl_usbotg: usbotggrp {
425 + fsl,pins = <
426 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
427 + >;
428 + };
429 +
430 + pinctrl_wdog: wdoggrp {
431 + fsl,pins = <
432 + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
433 + >;
434 + };
435 +};
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