target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch

   1 From 62e7f0b553038e3a1a1b2b067dd1fbdacd634e37 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Fri, 14 Feb 2020 13:02:41 -0800
   4 Subject: [PATCH] ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn support
   5
   6 Add one node for the accel/gyro i2c device and another for the separate
   7 magnetometer device in the lsm9ds1.
   8
   9 Signed-off-by: Robert Jones <rjones@gateworks.com>
  10 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  11 ---
  12  arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 31 +++++++++++++++++++++++++++++++
  13  1 file changed, 31 insertions(+)
  14
  15 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
  16 +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
  17 @@ -173,6 +173,25 @@
  18         pinctrl-0 = <&pinctrl_i2c2>;
  19         status = "okay";
  20
  21 +       magn@1c {
  22 +               compatible = "st,lsm9ds1-magn";
  23 +               reg = <0x1c>;
  24 +               pinctrl-names = "default";
  25 +               pinctrl-0 = <&pinctrl_mag>;
  26 +               interrupt-parent = <&gpio1>;
  27 +               interrupts = <2 IRQ_TYPE_EDGE_RISING>;
  28 +       };
  29 +
  30 +       imu@6a {
  31 +               compatible = "st,lsm9ds1-imu";
  32 +               reg = <0x6a>;
  33 +               st,drdy-int-pin = <1>;
  34 +               pinctrl-names = "default";
  35 +               pinctrl-0 = <&pinctrl_imu>;
  36 +               interrupt-parent = <&gpio7>;
  37 +               interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
  38 +       };
  39 +
  40         ltc3676: pmic@3c {
  41                 compatible = "lltc,ltc3676";
  42                 reg = <0x3c>;
  43 @@ -426,6 +445,12 @@
  44                 >;
  45         };
  46
  47 +       pinctrl_imu: imugrp {
  48 +               fsl,pins = <
  49 +                       MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
  50 +               >;
  51 +       };
  52 +
  53         pinctrl_ipu1_csi0: ipu1csi0grp {
  54                 fsl,pins = <
  55                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
  56 @@ -449,6 +474,12 @@
  57                 >;
  58         };
  59
  60 +       pinctrl_mag: maggrp {
  61 +               fsl,pins = <
  62 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
  63 +               >;
  64 +       };
  65 +
  66         pinctrl_pcie: pciegrp {
  67                 fsl,pins = <
  68                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0