target/linux/imx6/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch

   1 From d2cf2f91ba5b6d7696b1870e28017a3e1a7a1bb8 Mon Sep 17 00:00:00 2001
   2 From: Tim Harvey <tharvey@gateworks.com>
   3 Date: Fri, 28 Feb 2020 11:46:07 -0800
   4 Subject: [PATCH] ARM: dts: imx6qdl-gw5910: add CC1352 UART
   5
   6 The GW5910-C revision adds a TI CC1352 connected to IMX UART4
   7
   8 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
   9 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  10 ---
  11  arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 25 +++++++++++++++++++++++++
  12  1 file changed, 25 insertions(+)
  13
  14 diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  15 index be1af74..30fe47f 100644
  16 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  17 +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  18 @@ -220,6 +220,14 @@
  19         status = "okay";
  20  };
  21
  22 +/* cc1352 */
  23 +&uart3 {
  24 +       pinctrl-names = "default";
  25 +       pinctrl-0 = <&pinctrl_uart3>;
  26 +       uart-has-rtscts;
  27 +       status = "okay";
  28 +};
  29 +
  30  /* Sterling-LWB Bluetooth */
  31  &uart4 {
  32         pinctrl-names = "default";
  33 @@ -411,6 +419,23 @@
  34                 >;
  35         };
  36
  37 +       pinctrl_uart3: uart3grp {
  38 +               fsl,pins = <
  39 +                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
  40 +                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
  41 +                       MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
  42 +                       MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
  43 +                       MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x4001b0b1 /* DIO20 */
  44 +                       MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x4001b0b1 /* DIO14 */
  45 +                       MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x4001b0b1 /* DIO15 */
  46 +                       MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08      0x1b0b1 /* TMS */
  47 +                       MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b1 /* TCK */
  48 +                       MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10      0x1b0b1 /* TDO */
  49 +                       MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x1b0b1 /* TDI */
  50 +                       MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x4001b0b1 /* RST# */
  51 +               >;
  52 +       };
  53 +
  54         pinctrl_uart4: uart4grp {
  55                 fsl,pins = <
  56                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
  57 --
  58 2.7.4
  59