imx6: backport v5.8 imx6qdl-gw dt patches
[openwrt/openwrt.git] / target / linux / imx6 / patches-5.4 / 007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch
1 From 9e72702a3d9a967edac02d8e937bce2b68b77814 Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Tue, 12 May 2020 13:59:37 -0700
4 Subject: [PATCH 05/20] ARM: dts: imx6qdl-gw560x: add lsm9ds1 iio imu/magn
5 support
6
7 Add one node for the accel/gyro i2c device and another for the separate
8 magnetometer device in the lsm9ds1.
9
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
11 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
12 ---
13 arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 31 +++++++++++++++++++++++++++++++
14 1 file changed, 31 insertions(+)
15
16 diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
17 index e8e36df..69ca70d 100644
18 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
19 +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
20 @@ -295,6 +295,15 @@
21 VDDIO-supply = <&reg_3p3v>;
22 };
23
24 + magn@1c {
25 + compatible = "st,lsm9ds1-magn";
26 + reg = <0x1c>;
27 + pinctrl-names = "default";
28 + pinctrl-0 = <&pinctrl_mag>;
29 + interrupt-parent = <&gpio5>;
30 + interrupts = <9 IRQ_TYPE_EDGE_RISING>;
31 + };
32 +
33 tca8418: keypad@34 {
34 compatible = "ti,tca8418";
35 pinctrl-names = "default";
36 @@ -389,6 +398,16 @@
37 };
38 };
39 };
40 +
41 + imu@6a {
42 + compatible = "st,lsm9ds1-imu";
43 + reg = <0x6a>;
44 + st,drdy-int-pin = <1>;
45 + pinctrl-names = "default";
46 + pinctrl-0 = <&pinctrl_imu>;
47 + interrupt-parent = <&gpio5>;
48 + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
49 + };
50 };
51
52 &i2c3 {
53 @@ -609,6 +628,12 @@
54 >;
55 };
56
57 + pinctrl_imu: imugrp {
58 + fsl,pins = <
59 + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
60 + >;
61 + };
62 +
63 pinctrl_keypad: keypadgrp {
64 fsl,pins = <
65 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
66 @@ -616,6 +641,12 @@
67 >;
68 };
69
70 + pinctrl_mag: maggrp {
71 + fsl,pins = <
72 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
73 + >;
74 + };
75 +
76 pinctrl_pcie: pciegrp {
77 fsl,pins = <
78 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
79 --
80 2.7.4
81