target/linux/imx6/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch

   1 From c8756cbad816954be912ba32277ccd55fe7acc01 Mon Sep 17 00:00:00 2001
   2 From: Tim Harvey <tharvey@gateworks.com>
   3 Date: Tue, 12 May 2020 13:59:56 -0700
   4 Subject: [PATCH 06/20] ARM: dts: imx6qdl-gw5904: add lsm9ds1 iio imu/magn
   5  support
   6
   7 Add one node for the accel/gyro i2c device and another for the separate
   8 magnetometer device in the lsm9ds1.
   9
  10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  11 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  12 ---
  13  arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 31 +++++++++++++++++++++++++++++++
  14  1 file changed, 31 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
  17 +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
  18 @@ -248,6 +248,15 @@
  19         pinctrl-0 = <&pinctrl_i2c2>;
  20         status = "okay";
  21
  22 +       magn@1c {
  23 +               compatible = "st,lsm9ds1-magn";
  24 +               reg = <0x1c>;
  25 +               pinctrl-names = "default";
  26 +               pinctrl-0 = <&pinctrl_mag>;
  27 +               interrupt-parent = <&gpio5>;
  28 +               interrupts = <17 IRQ_TYPE_EDGE_RISING>;
  29 +       };
  30 +
  31         ltc3676: pmic@3c {
  32                 compatible = "lltc,ltc3676";
  33                 reg = <0x3c>;
  34 @@ -320,6 +329,16 @@
  35                         };
  36                 };
  37         };
  38 +
  39 +       imu@6a {
  40 +               compatible = "st,lsm9ds1-imu";
  41 +               reg = <0x6a>;
  42 +               st,drdy-int-pin = <1>;
  43 +               pinctrl-names = "default";
  44 +               pinctrl-0 = <&pinctrl_imu>;
  45 +               interrupt-parent = <&gpio4>;
  46 +               interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
  47 +       };
  48  };
  49
  50  &i2c3 {
  51 @@ -501,6 +520,18 @@
  52                 >;
  53         };
  54
  55 +       pinctrl_imu: imugrp {
  56 +               fsl,pins = <
  57 +                       MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
  58 +               >;
  59 +       };
  60 +
  61 +       pinctrl_mag: maggrp {
  62 +               fsl,pins = <
  63 +                       MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
  64 +               >;
  65 +       };
  66 +
  67         pinctrl_pcie: pciegrp {
  68                 fsl,pins = <
  69                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */