target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.h

   1 /*
   2  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for
   5  * any purpose with or without fee is hereby granted, provided that the
   6  * above copyright notice and this permission notice appear in all copies.
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  13  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16  #ifndef __AR40XX_H
  17 #define __AR40XX_H
  18
  19 #define AR40XX_MAX_VLANS        128
  20 #define AR40XX_NUM_PORTS        6
  21 #define AR40XX_NUM_PHYS 5
  22
  23 #define BITS(_s, _n)    (((1UL << (_n)) - 1) << _s)
  24
  25 struct ar40xx_priv {
  26         struct switch_dev dev;
  27
  28         u8  __iomem      *hw_addr;
  29         u8  __iomem      *psgmii_hw_addr;
  30         u32 mac_mode;
  31         struct reset_control *ess_rst;
  32         u32 cpu_bmp;
  33         u32 lan_bmp;
  34         u32 wan_bmp;
  35
  36         struct mii_bus *mii_bus;
  37         struct phy_device *phy;
  38
  39         /* mutex for qm task */
  40         struct mutex qm_lock;
  41         struct delayed_work qm_dwork;
  42         u32 port_link_up[AR40XX_NUM_PORTS];
  43         u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
  44         u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
  45
  46         u32 phy_t_status;
  47
  48         /* mutex for switch reg access */
  49         struct mutex reg_mutex;
  50
  51         /* mutex for mib task */
  52         struct mutex mib_lock;
  53         struct delayed_work mib_work;
  54         int mib_next_port;
  55         u64 *mib_stats;
  56
  57         char buf[2048];
  58
  59         /* all fields below will be cleared on reset */
  60         bool vlan;
  61         u16 vlan_id[AR40XX_MAX_VLANS];
  62         u8 vlan_table[AR40XX_MAX_VLANS];
  63         u8 vlan_tagged;
  64         u16 pvid[AR40XX_NUM_PORTS];
  65
  66         /* mirror */
  67         bool mirror_rx;
  68         bool mirror_tx;
  69         int source_port;
  70         int monitor_port;
  71 };
  72
  73 #define AR40XX_PORT_LINK_UP 1
  74 #define AR40XX_PORT_LINK_DOWN 0
  75 #define AR40XX_QM_NOT_EMPTY  1
  76 #define AR40XX_QM_EMPTY  0
  77
  78 #define AR40XX_LAN_VLAN 1
  79 #define AR40XX_WAN_VLAN 2
  80
  81 enum ar40xx_port_wrapper_cfg {
  82         PORT_WRAPPER_PSGMII = 0,
  83 };
  84
  85 struct ar40xx_mib_desc {
  86         u32 size;
  87         u32 offset;
  88         const char *name;
  89 };
  90
  91 #define AR40XX_PORT_CPU 0
  92
  93 #define AR40XX_PSGMII_MODE_CONTROL      0x1b4
  94 #define   AR40XX_PSGMII_ATHR_CSCO_MODE_25M      BIT(0)
  95
  96 #define AR40XX_PSGMIIPHY_TX_CONTROL      0x288
  97
  98 #define AR40XX_MII_ATH_MMD_ADDR         0x0d
  99 #define AR40XX_MII_ATH_MMD_DATA         0x0e
 100 #define AR40XX_MII_ATH_DBG_ADDR         0x1d
 101 #define AR40XX_MII_ATH_DBG_DATA         0x1e
 102
 103 #define AR40XX_STATS_RXBROAD            0x00
 104 #define AR40XX_STATS_RXPAUSE            0x04
 105 #define AR40XX_STATS_RXMULTI            0x08
 106 #define AR40XX_STATS_RXFCSERR           0x0c
 107 #define AR40XX_STATS_RXALIGNERR         0x10
 108 #define AR40XX_STATS_RXRUNT             0x14
 109 #define AR40XX_STATS_RXFRAGMENT         0x18
 110 #define AR40XX_STATS_RX64BYTE           0x1c
 111 #define AR40XX_STATS_RX128BYTE          0x20
 112 #define AR40XX_STATS_RX256BYTE          0x24
 113 #define AR40XX_STATS_RX512BYTE          0x28
 114 #define AR40XX_STATS_RX1024BYTE         0x2c
 115 #define AR40XX_STATS_RX1518BYTE         0x30
 116 #define AR40XX_STATS_RXMAXBYTE          0x34
 117 #define AR40XX_STATS_RXTOOLONG          0x38
 118 #define AR40XX_STATS_RXGOODBYTE         0x3c
 119 #define AR40XX_STATS_RXBADBYTE          0x44
 120 #define AR40XX_STATS_RXOVERFLOW         0x4c
 121 #define AR40XX_STATS_FILTERED           0x50
 122 #define AR40XX_STATS_TXBROAD            0x54
 123 #define AR40XX_STATS_TXPAUSE            0x58
 124 #define AR40XX_STATS_TXMULTI            0x5c
 125 #define AR40XX_STATS_TXUNDERRUN         0x60
 126 #define AR40XX_STATS_TX64BYTE           0x64
 127 #define AR40XX_STATS_TX128BYTE          0x68
 128 #define AR40XX_STATS_TX256BYTE          0x6c
 129 #define AR40XX_STATS_TX512BYTE          0x70
 130 #define AR40XX_STATS_TX1024BYTE         0x74
 131 #define AR40XX_STATS_TX1518BYTE         0x78
 132 #define AR40XX_STATS_TXMAXBYTE          0x7c
 133 #define AR40XX_STATS_TXOVERSIZE         0x80
 134 #define AR40XX_STATS_TXBYTE             0x84
 135 #define AR40XX_STATS_TXCOLLISION        0x8c
 136 #define AR40XX_STATS_TXABORTCOL         0x90
 137 #define AR40XX_STATS_TXMULTICOL         0x94
 138 #define AR40XX_STATS_TXSINGLECOL        0x98
 139 #define AR40XX_STATS_TXEXCDEFER         0x9c
 140 #define AR40XX_STATS_TXDEFER            0xa0
 141 #define AR40XX_STATS_TXLATECOL          0xa4
 142
 143 #define AR40XX_REG_MODULE_EN                    0x030
 144 #define   AR40XX_MODULE_EN_MIB                  BIT(0)
 145
 146 #define AR40XX_REG_MIB_FUNC                     0x034
 147 #define   AR40XX_MIB_BUSY               BIT(17)
 148 #define   AR40XX_MIB_CPU_KEEP                   BIT(20)
 149 #define   AR40XX_MIB_FUNC               BITS(24, 3)
 150 #define   AR40XX_MIB_FUNC_S             24
 151 #define   AR40XX_MIB_FUNC_NO_OP         0x0
 152 #define   AR40XX_MIB_FUNC_FLUSH         0x1
 153
 154 #define AR40XX_ESS_SERVICE_TAG          0x48
 155 #define AR40XX_ESS_SERVICE_TAG_STAG     BIT(17)
 156
 157 #define AR40XX_REG_PORT_STATUS(_i)              (0x07c + (_i) * 4)
 158 #define   AR40XX_PORT_SPEED                     BITS(0, 2)
 159 #define   AR40XX_PORT_STATUS_SPEED_S    0
 160 #define   AR40XX_PORT_TX_EN                     BIT(2)
 161 #define   AR40XX_PORT_RX_EN                     BIT(3)
 162 #define   AR40XX_PORT_STATUS_TXFLOW     BIT(4)
 163 #define   AR40XX_PORT_STATUS_RXFLOW     BIT(5)
 164 #define   AR40XX_PORT_DUPLEX                    BIT(6)
 165 #define   AR40XX_PORT_TXHALF_FLOW               BIT(7)
 166 #define   AR40XX_PORT_STATUS_LINK_UP    BIT(8)
 167 #define   AR40XX_PORT_AUTO_LINK_EN              BIT(9)
 168 #define   AR40XX_PORT_STATUS_FLOW_CONTROL  BIT(12)
 169
 170 #define AR40XX_REG_MAX_FRAME_SIZE               0x078
 171 #define   AR40XX_MAX_FRAME_SIZE_MTU             BITS(0, 14)
 172
 173 #define AR40XX_REG_PORT_HEADER(_i)              (0x09c + (_i) * 4)
 174
 175 #define AR40XX_REG_EEE_CTRL                     0x100
 176 #define   AR40XX_EEE_CTRL_DISABLE_PHY(_i)       BIT(4 + (_i) * 2)
 177
 178 #define AR40XX_REG_PORT_VLAN0(_i)               (0x420 + (_i) * 0x8)
 179 #define   AR40XX_PORT_VLAN0_DEF_SVID            BITS(0, 12)
 180 #define   AR40XX_PORT_VLAN0_DEF_SVID_S          0
 181 #define   AR40XX_PORT_VLAN0_DEF_CVID            BITS(16, 12)
 182 #define   AR40XX_PORT_VLAN0_DEF_CVID_S          16
 183
 184 #define AR40XX_REG_PORT_VLAN1(_i)               (0x424 + (_i) * 0x8)
 185 #define   AR40XX_PORT_VLAN1_CORE_PORT           BIT(9)
 186 #define   AR40XX_PORT_VLAN1_PORT_TLS_MODE       BIT(7)
 187 #define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP      BIT(6)
 188 #define   AR40XX_PORT_VLAN1_OUT_MODE            BITS(12, 2)
 189 #define   AR40XX_PORT_VLAN1_OUT_MODE_S          12
 190 #define   AR40XX_PORT_VLAN1_OUT_MODE_UNMOD      0
 191 #define   AR40XX_PORT_VLAN1_OUT_MODE_UNTAG      1
 192 #define   AR40XX_PORT_VLAN1_OUT_MODE_TAG                2
 193 #define   AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH    3
 194
 195 #define AR40XX_REG_VTU_FUNC0                    0x0610
 196 #define   AR40XX_VTU_FUNC0_EG_MODE              BITS(4, 14)
 197 #define   AR40XX_VTU_FUNC0_EG_MODE_S(_i)        (4 + (_i) * 2)
 198 #define   AR40XX_VTU_FUNC0_EG_MODE_KEEP         0
 199 #define   AR40XX_VTU_FUNC0_EG_MODE_UNTAG        1
 200 #define   AR40XX_VTU_FUNC0_EG_MODE_TAG          2
 201 #define   AR40XX_VTU_FUNC0_EG_MODE_NOT          3
 202 #define   AR40XX_VTU_FUNC0_IVL                  BIT(19)
 203 #define   AR40XX_VTU_FUNC0_VALID                BIT(20)
 204
 205 #define AR40XX_REG_VTU_FUNC1                    0x0614
 206 #define   AR40XX_VTU_FUNC1_OP                   BITS(0, 3)
 207 #define   AR40XX_VTU_FUNC1_OP_NOOP              0
 208 #define   AR40XX_VTU_FUNC1_OP_FLUSH             1
 209 #define   AR40XX_VTU_FUNC1_OP_LOAD              2
 210 #define   AR40XX_VTU_FUNC1_OP_PURGE             3
 211 #define   AR40XX_VTU_FUNC1_OP_REMOVE_PORT       4
 212 #define   AR40XX_VTU_FUNC1_OP_GET_NEXT          5
 213 #define   AR40XX7_VTU_FUNC1_OP_GET_ONE          6
 214 #define   AR40XX_VTU_FUNC1_FULL                 BIT(4)
 215 #define   AR40XX_VTU_FUNC1_PORT                 BIT(8, 4)
 216 #define   AR40XX_VTU_FUNC1_PORT_S               8
 217 #define   AR40XX_VTU_FUNC1_VID                  BIT(16, 12)
 218 #define   AR40XX_VTU_FUNC1_VID_S                16
 219 #define   AR40XX_VTU_FUNC1_BUSY                 BIT(31)
 220
 221 #define AR40XX_REG_FWD_CTRL0                    0x620
 222 #define   AR40XX_FWD_CTRL0_CPU_PORT_EN          BIT(10)
 223 #define   AR40XX_FWD_CTRL0_MIRROR_PORT          BITS(4, 4)
 224 #define   AR40XX_FWD_CTRL0_MIRROR_PORT_S        4
 225
 226 #define AR40XX_REG_FWD_CTRL1                    0x624
 227 #define   AR40XX_FWD_CTRL1_UC_FLOOD             BITS(0, 7)
 228 #define   AR40XX_FWD_CTRL1_UC_FLOOD_S           0
 229 #define   AR40XX_FWD_CTRL1_MC_FLOOD             BITS(8, 7)
 230 #define   AR40XX_FWD_CTRL1_MC_FLOOD_S           8
 231 #define   AR40XX_FWD_CTRL1_BC_FLOOD             BITS(16, 7)
 232 #define   AR40XX_FWD_CTRL1_BC_FLOOD_S           16
 233 #define   AR40XX_FWD_CTRL1_IGMP                 BITS(24, 7)
 234 #define   AR40XX_FWD_CTRL1_IGMP_S               24
 235
 236 #define AR40XX_REG_PORT_LOOKUP(_i)              (0x660 + (_i) * 0xc)
 237 #define   AR40XX_PORT_LOOKUP_MEMBER             BITS(0, 7)
 238 #define   AR40XX_PORT_LOOKUP_IN_MODE            BITS(8, 2)
 239 #define   AR40XX_PORT_LOOKUP_IN_MODE_S          8
 240 #define   AR40XX_PORT_LOOKUP_STATE              BITS(16, 3)
 241 #define   AR40XX_PORT_LOOKUP_STATE_S            16
 242 #define   AR40XX_PORT_LOOKUP_LEARN              BIT(20)
 243 #define   AR40XX_PORT_LOOKUP_LOOPBACK           BIT(21)
 244 #define   AR40XX_PORT_LOOKUP_ING_MIRROR_EN      BIT(25)
 245
 246 #define AR40XX_REG_ATU_FUNC                     0x60c
 247 #define   AR40XX_ATU_FUNC_OP                    BITS(0, 4)
 248 #define   AR40XX_ATU_FUNC_OP_NOOP               0x0
 249 #define   AR40XX_ATU_FUNC_OP_FLUSH              0x1
 250 #define   AR40XX_ATU_FUNC_OP_LOAD               0x2
 251 #define   AR40XX_ATU_FUNC_OP_PURGE              0x3
 252 #define   AR40XX_ATU_FUNC_OP_FLUSH_LOCKED       0x4
 253 #define   AR40XX_ATU_FUNC_OP_FLUSH_UNICAST      0x5
 254 #define   AR40XX_ATU_FUNC_OP_GET_NEXT           0x6
 255 #define   AR40XX_ATU_FUNC_OP_SEARCH_MAC         0x7
 256 #define   AR40XX_ATU_FUNC_OP_CHANGE_TRUNK       0x8
 257 #define   AR40XX_ATU_FUNC_BUSY                  BIT(31)
 258
 259 #define AR40XX_REG_QM_DEBUG_ADDR                0x820
 260 #define AR40XX_REG_QM_DEBUG_VALUE               0x824
 261 #define   AR40XX_REG_QM_PORT0_3_QNUM            0x1d
 262 #define   AR40XX_REG_QM_PORT4_6_QNUM            0x1e
 263
 264 #define AR40XX_REG_PORT_HOL_CTRL1(_i)           (0x974 + (_i) * 0x8)
 265 #define   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN    BIT(16)
 266
 267 #define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i)     (0x9b0 + (_i) * 0x4)
 268 #define   AR40XX_PORT0_FC_THRESH_ON_DFLT        0x60
 269 #define   AR40XX_PORT0_FC_THRESH_OFF_DFLT       0x90
 270
 271 #define AR40XX_PHY_DEBUG_0   0
 272 #define AR40XX_PHY_MANU_CTRL_EN  BIT(12)
 273
 274 #define AR40XX_PHY_DEBUG_2   2
 275
 276 #define AR40XX_PHY_SPEC_STATUS 0x11
 277 #define   AR40XX_PHY_SPEC_STATUS_LINK           BIT(10)
 278 #define   AR40XX_PHY_SPEC_STATUS_DUPLEX         BIT(13)
 279 #define   AR40XX_PHY_SPEC_STATUS_SPEED          BITS(14, 2)
 280
 281 /* port forwarding state */
 282 enum {
 283         AR40XX_PORT_STATE_DISABLED = 0,
 284         AR40XX_PORT_STATE_BLOCK = 1,
 285         AR40XX_PORT_STATE_LISTEN = 2,
 286         AR40XX_PORT_STATE_LEARN = 3,
 287         AR40XX_PORT_STATE_FORWARD = 4
 288 };
 289
 290 /* ingress 802.1q mode */
 291 enum {
 292         AR40XX_IN_PORT_ONLY = 0,
 293         AR40XX_IN_PORT_FALLBACK = 1,
 294         AR40XX_IN_VLAN_ONLY = 2,
 295         AR40XX_IN_SECURE = 3
 296 };
 297
 298 /* egress 802.1q mode */
 299 enum {
 300         AR40XX_OUT_KEEP = 0,
 301         AR40XX_OUT_STRIP_VLAN = 1,
 302         AR40XX_OUT_ADD_VLAN = 2
 303 };
 304
 305 /* port speed */
 306 enum {
 307         AR40XX_PORT_SPEED_10M = 0,
 308         AR40XX_PORT_SPEED_100M = 1,
 309         AR40XX_PORT_SPEED_1000M = 2,
 310         AR40XX_PORT_SPEED_ERR = 3,
 311 };
 312
 313 #define AR40XX_MIB_WORK_DELAY   2000 /* msecs */
 314
 315 #define AR40XX_QM_WORK_DELAY    100
 316
 317 #define   AR40XX_MIB_FUNC_CAPTURE       0x3
 318
 319 #define AR40XX_REG_PORT_STATS_START     0x1000
 320 #define AR40XX_REG_PORT_STATS_LEN               0x100
 321
 322 #define AR40XX_PORTS_ALL        0x3f
 323
 324 #define AR40XX_PSGMII_ID        5
 325 #define AR40XX_PSGMII_CALB_NUM  100
 326 #define AR40XX_MALIBU_PSGMII_MODE_CTRL  0x6d
 327 #define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL   0x220c
 328 #define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
 329 #define AR40XX_MALIBU_DAC_CTRL_MASK     0x380
 330 #define AR40XX_MALIBU_DAC_CTRL_VALUE    0x280
 331 #define AR40XX_MALIBU_PHY_RLP_CTRL       0x805a
 332 #define AR40XX_PSGMII_TX_DRIVER_1_CTRL  0xb
 333 #define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP   0x8a
 334 #define AR40XX_MALIBU_PHY_LAST_ADDR     4
 335
 336 static inline struct ar40xx_priv *
 337 swdev_to_ar40xx(struct switch_dev *swdev)
 338 {
 339         return container_of(swdev, struct ar40xx_priv, dev);
 340 }
 341
 342 #endif