target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "EZVIZ CS-W3-WD1200G EUP";
  10         compatible = "ezviz,cs-w3-wd1200g-eup";
  11
  12         aliases {
  13                 led-boot = &led_status_green;
  14                 led-failsafe = &led_status_red;
  15                 led-running = &led_status_blue;
  16                 led-upgrade = &led_status_green;
  17         };
  18
  19         soc {
  20                 rng@22000 {
  21                         status = "okay";
  22                 };
  23
  24                 mdio@90000 {
  25                         status = "okay";
  26                         pinctrl-0 = <&mdio_pins>;
  27                         pinctrl-names = "default";
  28                         reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
  29                         reset-delay-us = <5000>;
  30                 };
  31
  32                 tcsr@1949000 {
  33                         compatible = "qcom,tcsr";
  34                         reg = <0x1949000 0x100>;
  35                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  36                 };
  37
  38                 tcsr@194b000 {
  39                         compatible = "qcom,tcsr";
  40                         reg = <0x194b000 0x100>;
  41                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  42                 };
  43
  44                 ess_tcsr@1953000 {
  45                         compatible = "qcom,tcsr";
  46                         reg = <0x1953000 0x1000>;
  47                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  48                 };
  49
  50                 tcsr@1957000 {
  51                         compatible = "qcom,tcsr";
  52                         reg = <0x1957000 0x100>;
  53                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  54                 };
  55
  56                 crypto@8e3a000 {
  57                         status = "okay";
  58                 };
  59
  60                 watchdog@b017000 {
  61                         status = "okay";
  62                 };
  63         };
  64
  65         leds {
  66                 compatible = "gpio-leds";
  67
  68                 led_status_red: status_red {
  69                         label = "red:status";
  70                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  71                 };
  72
  73                 led_status_green: status_green {
  74                         label = "green:status";
  75                         gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
  76                 };
  77
  78                 led_status_blue: status_blue {
  79                         label = "blue:status";
  80                         gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
  81                 };
  82         };
  83
  84         keys {
  85                 compatible = "gpio-keys";
  86
  87                 reset {
  88                         label = "reset";
  89                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  90                         linux,code = <KEY_RESTART>;
  91                 };
  92         };
  93 };
  94
  95 &tlmm {
  96         serial_pins: serial_pinmux {
  97                 mux {
  98                         pins = "gpio60", "gpio61";
  99                         function = "blsp_uart0";
 100                         bias-disable;
 101                 };
 102         };
 103
 104         mdio_pins: mdio_pinmux {
 105                 mux_1 {
 106                         pins = "gpio53";
 107                         function = "mdio";
 108                         bias-pull-up;
 109                 };
 110
 111                 mux_2 {
 112                         pins = "gpio52";
 113                         function = "mdc";
 114                         bias-pull-up;
 115                 };
 116         };
 117
 118         spi_0_pins: spi_0_pinmux {
 119                 pin {
 120                         function = "blsp_spi0";
 121                         pins = "gpio55", "gpio56", "gpio57";
 122                         drive-strength = <12>;
 123                         bias-disable;
 124                 };
 125                 pin_cs {
 126                         function = "gpio";
 127                         pins = "gpio54";
 128                         drive-strength = <2>;
 129                         bias-disable;
 130                         output-high;
 131                 };
 132         };
 133 };
 134
 135 &blsp_dma {
 136         status = "okay";
 137 };
 138
 139 &blsp1_spi1 {
 140         pinctrl-0 = <&spi_0_pins>;
 141         pinctrl-names = "default";
 142         status = "okay";
 143         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 144
 145         flash@0 {
 146                 compatible = "jedec,spi-nor";
 147                 reg = <0>;
 148                 spi-max-frequency = <24000000>;
 149
 150                 partitions {
 151                         compatible = "fixed-partitions";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154
 155                         partition0@0 {
 156                                 label = "SBL1";
 157                                 reg = <0x00000000 0x00040000>;
 158                                 read-only;
 159                         };
 160
 161                         partition1@40000 {
 162                                 label = "MIBIB";
 163                                 reg = <0x00040000 0x00020000>;
 164                                 read-only;
 165                         };
 166
 167                         partition2@60000 {
 168                                 label = "QSEE";
 169                                 reg = <0x00060000 0x00060000>;
 170                                 read-only;
 171                         };
 172
 173                         partition3@c0000 {
 174                                 label = "CDT";
 175                                 reg = <0x000c0000 0x00010000>;
 176                                 read-only;
 177                         };
 178
 179                         partition4@d0000 {
 180                                 label = "DDRPARAMS";
 181                                 reg = <0x000d0000 0x00010000>;
 182                                 read-only;
 183                         };
 184
 185                         partition5@E0000 {
 186                                 label = "APPSBLENV";
 187                                 reg = <0x000e0000 0x00010000>;
 188                                 read-only;
 189                         };
 190
 191                         partition6@F0000 {
 192                                 label = "APPSBL";
 193                                 reg = <0x000f0000 0x00080000>;
 194                                 read-only;
 195                         };
 196
 197                         partition7@170000 {
 198                                 label = "ART";
 199                                 reg = <0x00170000 0x00010000>;
 200                                 read-only;
 201
 202                                 compatible = "nvmem-cells";
 203                                 #address-cells = <1>;
 204                                 #size-cells = <1>;
 205
 206                                 macaddr_art_0: macaddr@0 {
 207                                         reg = <0x0 0x6>;
 208                                 };
 209
 210                                 macaddr_art_6: macaddr@6 {
 211                                         reg = <0x6 0x6>;
 212                                 };
 213
 214                                 precal_art_1000: precal@1000 {
 215                                         reg = <0x1000 0x2f20>;
 216                                 };
 217
 218                                 precal_art_5000: precal@5000 {
 219                                         reg = <0x5000 0x2f20>;
 220                                 };
 221                         };
 222
 223                         partition9@580000 {
 224                                 compatible = "denx,fit";
 225                                 label = "firmware";
 226                                 reg = <0x00180000 0x00e80000>;
 227                         };
 228                 };
 229         };
 230 };
 231
 232 &blsp1_uart1 {
 233         pinctrl-0 = <&serial_pins>;
 234         pinctrl-names = "default";
 235         status = "okay";
 236 };
 237
 238 &cryptobam {
 239         status = "okay";
 240 };
 241
 242 &wifi0 {
 243         status = "okay";
 244         qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
 245         nvmem-cell-names = "pre-calibration";
 246         nvmem-cells = <&precal_art_1000>;
 247 };
 248
 249 &wifi1 {
 250         status = "okay";
 251         qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
 252         nvmem-cell-names = "pre-calibration";
 253         nvmem-cells = <&precal_art_5000>;
 254 };