target/linux/ipq40xx/patches-4.14/088-0005-i2c-qup-schedule-EOT-and-FLUSH-tags-at-the-end-of-tr.patch

   1 From c5adc0fa63a930e3313c74bb7c1d4d158130eb41 Mon Sep 17 00:00:00 2001
   2 From: Abhishek Sahu <absahu@codeaurora.org>
   3 Date: Mon, 12 Mar 2018 18:44:54 +0530
   4 Subject: [PATCH 05/13] i2c: qup: schedule EOT and FLUSH tags at the end of
   5  transfer
   6
   7 The role of FLUSH and EOT tag is to flush already scheduled
   8 descriptors in BAM HW in case of error. EOT is required only
   9 when descriptors are scheduled in RX FIFO. If all the messages
  10 are WRITE, then only FLUSH tag will be used.
  11
  12 A single BAM transfer can have multiple read and write messages.
  13 The EOT and FLUSH tags should be scheduled at the end of BAM HW
  14 descriptors. Since the READ and WRITE can be present in any order
  15 so for some of the cases, these tags are not being written
  16 correctly.
  17
  18 Following is one of the example
  19
  20    READ, READ, READ, READ
  21
  22 Currently EOT and FLUSH tags are being written after each READ.
  23 If QUP gets NACK for first READ itself, then flush will be
  24 triggered. It will look for first FLUSH tag in TX FIFO and will
  25 stop there so only descriptors for first READ descriptors be
  26 flushed. All the scheduled descriptors should be cleared to
  27 generate BAM DMA completion.
  28
  29 Now this patch is scheduling FLUSH and EOT only once after all the
  30 descriptors. So, flush will clear all the scheduled descriptors and
  31 BAM will generate the completion interrupt.
  32
  33 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  34 Reviewed-by: Sricharan R <sricharan@codeaurora.org>
  35 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
  36 ---
  37  drivers/i2c/busses/i2c-qup.c | 39 ++++++++++++++++++++++--------------
  38  1 file changed, 24 insertions(+), 15 deletions(-)
  39
  40 --- a/drivers/i2c/busses/i2c-qup.c
  41 +++ b/drivers/i2c/busses/i2c-qup.c
  42 @@ -551,7 +551,7 @@ static int qup_i2c_set_tags_smb(u16 addr
  43  }
  44
  45  static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
  46 -                           struct i2c_msg *msg,  int is_dma)
  47 +                           struct i2c_msg *msg)
  48  {
  49         u16 addr = i2c_8bit_addr_from_msg(msg);
  50         int len = 0;
  51 @@ -592,11 +592,6 @@ static int qup_i2c_set_tags(u8 *tags, st
  52         else
  53                 tags[len++] = data_len;
  54
  55 -       if ((msg->flags & I2C_M_RD) && last && is_dma) {
  56 -               tags[len++] = QUP_BAM_INPUT_EOT;
  57 -               tags[len++] = QUP_BAM_FLUSH_STOP;
  58 -       }
  59 -
  60         return len;
  61  }
  62
  63 @@ -605,7 +600,7 @@ static int qup_i2c_issue_xfer_v2(struct
  64         int data_len = 0, tag_len, index;
  65         int ret;
  66
  67 -       tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
  68 +       tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg);
  69         index = msg->len - qup->blk.data_len;
  70
  71         /* only tags are written for read */
  72 @@ -701,7 +696,7 @@ static int qup_i2c_bam_do_xfer(struct qu
  73                         while (qup->blk.pos < blocks) {
  74                                 tlen = (i == (blocks - 1)) ? rem : limit;
  75                                 tags = &qup->start_tag.start[off + len];
  76 -                               len += qup_i2c_set_tags(tags, qup, msg, 1);
  77 +                               len += qup_i2c_set_tags(tags, qup, msg);
  78                                 qup->blk.data_len -= tlen;
  79
  80                                 /* scratch buf to read the start and len tags */
  81 @@ -729,17 +724,11 @@ static int qup_i2c_bam_do_xfer(struct qu
  82                                 return ret;
  83
  84                         off += len;
  85 -                       /* scratch buf to read the BAM EOT and FLUSH tags */
  86 -                       ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
  87 -                                            &qup->brx.tag.start[0],
  88 -                                            2, qup, DMA_FROM_DEVICE);
  89 -                       if (ret)
  90 -                               return ret;
  91                 } else {
  92                         while (qup->blk.pos < blocks) {
  93                                 tlen = (i == (blocks - 1)) ? rem : limit;
  94                                 tags = &qup->start_tag.start[off + tx_len];
  95 -                               len = qup_i2c_set_tags(tags, qup, msg, 1);
  96 +                               len = qup_i2c_set_tags(tags, qup, msg);
  97                                 qup->blk.data_len -= tlen;
  98
  99                                 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++],
 100 @@ -779,6 +768,26 @@ static int qup_i2c_bam_do_xfer(struct qu
 101                 msg++;
 102         }
 103
 104 +       /* schedule the EOT and FLUSH I2C tags */
 105 +       len = 1;
 106 +       if (rx_cnt) {
 107 +               qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
 108 +               len++;
 109 +
 110 +               /* scratch buf to read the BAM EOT and FLUSH tags */
 111 +               ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
 112 +                                    &qup->brx.tag.start[0],
 113 +                                    2, qup, DMA_FROM_DEVICE);
 114 +               if (ret)
 115 +                       return ret;
 116 +       }
 117 +
 118 +       qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
 119 +       ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
 120 +                            len, qup, DMA_TO_DEVICE);
 121 +       if (ret)
 122 +               return ret;
 123 +
 124         txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
 125                                       DMA_MEM_TO_DEV,
 126                                       DMA_PREP_INTERRUPT | DMA_PREP_FENCE);