target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch

   1 From 234d6f40fb4b771b396b45a9492aab463771bd0b Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Tue, 6 Aug 2019 11:42:57 +0200
   4 Subject: [PATCH] phy: Add ipq40xx mdio driver
   5
   6 ---
   7  drivers/net/phy/Kconfig        |   7 +
   8  drivers/net/phy/Makefile       |   1 +
   9  drivers/net/phy/mdio-ipq40xx.c | 247 +++++++++++++++++++++++++++++++++
  10  3 files changed, 255 insertions(+)
  11  create mode 100644 drivers/net/phy/mdio-ipq40xx.c
  12
  13 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
  14 index 1f5fd24cd..eb71b47a3 100644
  15 --- a/drivers/net/phy/Kconfig
  16 +++ b/drivers/net/phy/Kconfig
  17 @@ -436,6 +436,13 @@ config XILINX_GMII2RGMII
  18           the Reduced Gigabit Media Independent Interface(RGMII) between
  19           Ethernet physical media devices and the Gigabit Ethernet controller.
  20
  21 +config MDIO_IPQ40XX
  22 +       tristate "Qualcomm Atheros ipq40xx MDIO interface"
  23 +       depends on HAS_IOMEM && OF
  24 +       ---help---
  25 +         This driver supports the MDIO interface found in Qualcomm
  26 +         Atheros ipq40xx Soc chip.
  27 +
  28  endif # PHYLIB
  29
  30  config MICREL_KS8995MA
  31 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
  32 index f21cda9d8..804c52634 100644
  33 --- a/drivers/net/phy/Makefile
  34 +++ b/drivers/net/phy/Makefile
  35 @@ -33,6 +33,7 @@ obj-$(CONFIG_MDIO_CAVIUM)     += mdio-cavium.o
  36  obj-$(CONFIG_MDIO_GPIO)                += mdio-gpio.o
  37  obj-$(CONFIG_MDIO_HISI_FEMAC)  += mdio-hisi-femac.o
  38  obj-$(CONFIG_MDIO_I2C)         += mdio-i2c.o
  39 +obj-$(CONFIG_MDIO_IPQ40XX)     += mdio-ipq40xx.o
  40  obj-$(CONFIG_MDIO_MOXART)      += mdio-moxart.o
  41  obj-$(CONFIG_MDIO_MSCC_MIIM)   += mdio-mscc-miim.o
  42  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  43 diff --git a/drivers/net/phy/mdio-ipq40xx.c b/drivers/net/phy/mdio-ipq40xx.c
  44 new file mode 100644
  45 index 000000000..88fe5dc2b
  46 --- /dev/null
  47 +++ b/drivers/net/phy/mdio-ipq40xx.c
  48 @@ -0,0 +1,247 @@
  49 +/*
  50 + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  51 + *
  52 + * Permission to use, copy, modify, and/or distribute this software for
  53 + * any purpose with or without fee is hereby granted, provided that the
  54 + * above copyright notice and this permission notice appear in all copies.
  55 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  56 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  57 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  58 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  59 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  60 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  61 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  62 + */
  63 +
  64 +#include <linux/delay.h>
  65 +#include <linux/kernel.h>
  66 +#include <linux/module.h>
  67 +#include <linux/mutex.h>
  68 +#include <linux/io.h>
  69 +#include <linux/of_address.h>
  70 +#include <linux/of_mdio.h>
  71 +#include <linux/of_gpio.h>
  72 +#include <linux/phy.h>
  73 +#include <linux/platform_device.h>
  74 +#include <linux/gpio.h>
  75 +
  76 +#define MDIO_CTRL_0_REG                0x40
  77 +#define MDIO_CTRL_1_REG                0x44
  78 +#define MDIO_CTRL_2_REG                0x48
  79 +#define MDIO_CTRL_3_REG                0x4c
  80 +#define MDIO_CTRL_4_REG                0x50
  81 +#define MDIO_CTRL_4_ACCESS_BUSY                BIT(16)
  82 +#define MDIO_CTRL_4_ACCESS_START               BIT(8)
  83 +#define MDIO_CTRL_4_ACCESS_CODE_READ           0
  84 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE  1
  85 +#define CTRL_0_REG_DEFAULT_VALUE       0x150FF
  86 +
  87 +#define IPQ40XX_MDIO_RETRY     1000
  88 +#define IPQ40XX_MDIO_DELAY     10
  89 +
  90 +struct ipq40xx_mdio_data {
  91 +       struct mii_bus  *mii_bus;
  92 +       void __iomem    *membase;
  93 +       struct device   *dev;
  94 +};
  95 +
  96 +static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
  97 +{
  98 +       int i;
  99 +
 100 +       for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
 101 +               unsigned int busy;
 102 +
 103 +               busy = readl(am->membase + MDIO_CTRL_4_REG) &
 104 +                       MDIO_CTRL_4_ACCESS_BUSY;
 105 +               if (!busy)
 106 +                       return 0;
 107 +
 108 +               /* BUSY might take to be cleard by 15~20 times of loop */
 109 +               udelay(IPQ40XX_MDIO_DELAY);
 110 +       }
 111 +
 112 +       dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
 113 +
 114 +       return -ETIMEDOUT;
 115 +}
 116 +
 117 +static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 118 +{
 119 +       struct ipq40xx_mdio_data *am = bus->priv;
 120 +       int value = 0;
 121 +       unsigned int cmd = 0;
 122 +
 123 +       lockdep_assert_held(&bus->mdio_lock);
 124 +
 125 +       if (ipq40xx_mdio_wait_busy(am))
 126 +               return -ETIMEDOUT;
 127 +
 128 +       /* issue the phy address and reg */
 129 +       writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
 130 +
 131 +       cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
 132 +
 133 +       /* issue read command */
 134 +       writel(cmd, am->membase + MDIO_CTRL_4_REG);
 135 +
 136 +       /* Wait read complete */
 137 +       if (ipq40xx_mdio_wait_busy(am))
 138 +               return -ETIMEDOUT;
 139 +
 140 +       /* Read data */
 141 +       value = readl(am->membase + MDIO_CTRL_3_REG);
 142 +
 143 +       return value;
 144 +}
 145 +
 146 +static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 147 +                           u16 value)
 148 +{
 149 +       struct ipq40xx_mdio_data *am = bus->priv;
 150 +       unsigned int cmd = 0;
 151 +
 152 +       lockdep_assert_held(&bus->mdio_lock);
 153 +
 154 +       if (ipq40xx_mdio_wait_busy(am))
 155 +               return -ETIMEDOUT;
 156 +
 157 +       /* issue the phy address and reg */
 158 +       writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
 159 +
 160 +       /* issue write data */
 161 +       writel(value, am->membase + MDIO_CTRL_2_REG);
 162 +
 163 +       cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
 164 +       /* issue write command */
 165 +       writel(cmd, am->membase + MDIO_CTRL_4_REG);
 166 +
 167 +       /* Wait write complete */
 168 +       if (ipq40xx_mdio_wait_busy(am))
 169 +               return -ETIMEDOUT;
 170 +
 171 +       return 0;
 172 +}
 173 +
 174 +static int ipq40xx_phy_reset(struct platform_device *pdev)
 175 +{
 176 +       struct device_node *mdio_node;
 177 +       int phy_reset_gpio_number;
 178 +       int ret;
 179 +
 180 +       mdio_node = of_find_node_by_name(NULL, "mdio");
 181 +       if (!mdio_node) {
 182 +               dev_err(&pdev->dev, "Could not find mdio node\n");
 183 +               return -ENOENT;
 184 +       }
 185 +
 186 +       ret = of_get_named_gpio(mdio_node, "phy-reset-gpio", 0);
 187 +       if (ret < 0) {
 188 +               dev_err(&pdev->dev, "Could not find phy-reset-gpio\n");
 189 +               return ret;
 190 +       }
 191 +
 192 +       phy_reset_gpio_number = ret;
 193 +
 194 +       ret = gpio_request(phy_reset_gpio_number, "phy-reset-gpio");
 195 +       if (ret) {
 196 +               dev_err(&pdev->dev, "Can't get phy-reset-gpio %d\n", ret);
 197 +               return ret;
 198 +       }
 199 +
 200 +       ret = gpio_direction_output(phy_reset_gpio_number, 0x0);
 201 +       if (ret) {
 202 +               dev_err(&pdev->dev,
 203 +                       "Can't set direction for phy-reset-gpio %d\n", ret);
 204 +               goto phy_reset_out;
 205 +       }
 206 +
 207 +       usleep_range(1000, 10005);
 208 +
 209 +       gpio_set_value(phy_reset_gpio_number, 0x01);
 210 +
 211 +phy_reset_out:
 212 +       gpio_free(phy_reset_gpio_number);
 213 +
 214 +       return ret;
 215 +}
 216 +
 217 +static int ipq40xx_mdio_probe(struct platform_device *pdev)
 218 +{
 219 +       struct ipq40xx_mdio_data *am;
 220 +       struct resource *res;
 221 +       int i, ret;
 222 +
 223 +       ret = ipq40xx_phy_reset(pdev);
 224 +       if (ret) {
 225 +               dev_err(&pdev->dev, "Could not find qca8075 reset gpio\n");
 226 +               return -ENODEV;
 227 +       }
 228 +
 229 +       am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
 230 +       if (!am)
 231 +               return -ENOMEM;
 232 +
 233 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 234 +       if (!res) {
 235 +               dev_err(&pdev->dev, "no iomem resource found\n");
 236 +               return -ENXIO;
 237 +       }
 238 +
 239 +       am->membase = devm_ioremap_resource(&pdev->dev, res);
 240 +       if (IS_ERR(am->membase)) {
 241 +               dev_err(&pdev->dev, "unable to ioremap registers\n");
 242 +               return PTR_ERR(am->membase);
 243 +       }
 244 +
 245 +       am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
 246 +       if (!am->mii_bus)
 247 +               return  -ENOMEM;
 248 +
 249 +       writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
 250 +
 251 +       am->mii_bus->name = "ipq40xx_mdio";
 252 +       am->mii_bus->read = ipq40xx_mdio_read;
 253 +       am->mii_bus->write = ipq40xx_mdio_write;
 254 +       am->mii_bus->priv = am;
 255 +       am->mii_bus->parent = &pdev->dev;
 256 +       snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
 257 +
 258 +       am->dev = &pdev->dev;
 259 +       platform_set_drvdata(pdev, am);
 260 +
 261 +       return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
 262 +}
 263 +
 264 +static int ipq40xx_mdio_remove(struct platform_device *pdev)
 265 +{
 266 +       struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
 267 +
 268 +       mdiobus_unregister(am->mii_bus);
 269 +
 270 +       return 0;
 271 +}
 272 +
 273 +static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
 274 +       { .compatible = "qcom,ipq4019-mdio" },
 275 +       { }
 276 +};
 277 +MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
 278 +
 279 +static struct platform_driver ipq40xx_mdio_driver = {
 280 +       .probe = ipq40xx_mdio_probe,
 281 +       .remove = ipq40xx_mdio_remove,
 282 +       .driver = {
 283 +               .name = "ipq40xx-mdio",
 284 +               .of_match_table = ipq40xx_mdio_dt_ids,
 285 +       },
 286 +};
 287 +
 288 +module_platform_driver(ipq40xx_mdio_driver);
 289 +
 290 +#define DRV_VERSION     "1.0"
 291 +
 292 +MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
 293 +MODULE_AUTHOR("Qualcomm Atheros");
 294 +MODULE_VERSION(DRV_VERSION);
 295 +MODULE_LICENSE("Dual BSD/GPL");
 296 --
 297 2.20.1