target/linux/ipq40xx/patches-5.4/077-qcom-ipq4019-add-USB-devicetree-nodes.patch

   1 From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 24 Jul 2018 14:47:55 +0200
   4 Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
   5
   6 This patch makes USB work on the Dakota EVB.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 ---
  10  arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
  11  arch/arm/boot/dts/qcom-ipq4019.dtsi           | 74 +++++++++++++++++++++++++++
  12  2 files changed, 94 insertions(+)
  13
  14 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  15 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  16 @@ -109,5 +109,25 @@
  17                 wifi@a800000 {
  18                         status = "ok";
  19                 };
  20 +
  21 +               usb3_ss_phy: ssphy@9a000 {
  22 +                       status = "ok";
  23 +               };
  24 +
  25 +               usb3_hs_phy: hsphy@a6000 {
  26 +                       status = "ok";
  27 +               };
  28 +
  29 +               usb3: usb3@8af8800 {
  30 +                       status = "ok";
  31 +               };
  32 +
  33 +               usb2_hs_phy: hsphy@a8000 {
  34 +                       status = "ok";
  35 +               };
  36 +
  37 +               usb2: usb2@60f8800 {
  38 +                       status = "ok";
  39 +               };
  40         };
  41  };
  42 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  43 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  44 @@ -563,5 +563,79 @@
  45                                           "legacy";
  46                         status = "disabled";
  47                 };
  48 +
  49 +               usb3_ss_phy: ssphy@9a000 {
  50 +                       compatible = "qcom,usb-ss-ipq4019-phy";
  51 +                       #phy-cells = <0>;
  52 +                       reg = <0x9a000 0x800>;
  53 +                       reg-names = "phy_base";
  54 +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
  55 +                       reset-names = "por_rst";
  56 +                       status = "disabled";
  57 +               };
  58 +
  59 +               usb3_hs_phy: hsphy@a6000 {
  60 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  61 +                       #phy-cells = <0>;
  62 +                       reg = <0xa6000 0x40>;
  63 +                       reg-names = "phy_base";
  64 +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
  65 +                       reset-names = "por_rst", "srif_rst";
  66 +                       status = "disabled";
  67 +               };
  68 +
  69 +               usb3@8af8800 {
  70 +                       compatible = "qcom,dwc3";
  71 +                       reg = <0x8af8800 0x100>;
  72 +                       #address-cells = <1>;
  73 +                       #size-cells = <1>;
  74 +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
  75 +                                <&gcc GCC_USB3_SLEEP_CLK>,
  76 +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  77 +                       clock-names = "master", "sleep", "mock_utmi";
  78 +                       ranges;
  79 +                       status = "disabled";
  80 +
  81 +                       dwc3@8a00000 {
  82 +                               compatible = "snps,dwc3";
  83 +                               reg = <0x8a00000 0xf8000>;
  84 +                               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  85 +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
  86 +                               phy-names = "usb2-phy", "usb3-phy";
  87 +                               dr_mode = "host";
  88 +                       };
  89 +               };
  90 +
  91 +               usb2_hs_phy: hsphy@a8000 {
  92 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  93 +                       #phy-cells = <0>;
  94 +                       reg = <0xa8000 0x40>;
  95 +                       reg-names = "phy_base";
  96 +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
  97 +                       reset-names = "por_rst", "srif_rst";
  98 +                       status = "disabled";
  99 +               };
 100 +
 101 +               usb2@60f8800 {
 102 +                       compatible = "qcom,dwc3";
 103 +                       reg = <0x60f8800 0x100>;
 104 +                       #address-cells = <1>;
 105 +                       #size-cells = <1>;
 106 +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
 107 +                                <&gcc GCC_USB2_SLEEP_CLK>,
 108 +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 109 +                       clock-names = "master", "sleep", "mock_utmi";
 110 +                       ranges;
 111 +                       status = "disabled";
 112 +
 113 +                       dwc3@6000000 {
 114 +                               compatible = "snps,dwc3";
 115 +                               reg = <0x6000000 0xf8000>;
 116 +                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 117 +                               phys = <&usb2_hs_phy>;
 118 +                               phy-names = "usb2-phy";
 119 +                               dr_mode = "host";
 120 +                       };
 121 +               };
 122         };
 123  };