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ipq806x: add missing gpio and gsbi declaration
[openwrt/openwrt.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 voltage-tolerance = <5>;
35 cooling-min-state = <0>;
36 cooling-max-state = <10>;
37 #cooling-cells = <2>;
38 cpu-idle-states = <&CPU_SPC>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
44 device_type = "cpu";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
51 clock-latency = <100000>;
52 cpu-supply = <&smb208_s2b>;
53 cooling-min-state = <0>;
54 cooling-max-state = <10>;
55 #cooling-cells = <2>;
56 cpu-idle-states = <&CPU_SPC>;
57 };
58
59 L2: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 qcom,saw = <&saw_l2>;
63 };
64
65 qcom,l2 {
66 qcom,l2-rates = <384000000 1000000000 1200000000>;
67 };
68
69 idle-states {
70 CPU_SPC: spc {
71 compatible = "qcom,idle-state-spc",
72 "arm,idle-state";
73 status = "okay";
74 entry-latency-us = <400>;
75 exit-latency-us = <900>;
76 min-residency-us = <3000>;
77 };
78 };
79 };
80
81 thermal-zones {
82 tsens_tz_sensor0 {
83 polling-delay-passive = <0>;
84 polling-delay = <0>;
85 thermal-sensors = <&tsens 0>;
86
87 trips {
88 cpu-critical-hi {
89 temperature = <125000>;
90 hysteresis = <2000>;
91 type = "critical_high";
92 };
93
94 cpu-config-hi {
95 temperature = <105000>;
96 hysteresis = <2000>;
97 type = "configurable_hi";
98 };
99
100 cpu-config-lo {
101 temperature = <95000>;
102 hysteresis = <2000>;
103 type = "configurable_lo";
104 };
105
106 cpu-critical-low {
107 temperature = <0>;
108 hysteresis = <2000>;
109 type = "critical_low";
110 };
111 };
112 };
113
114 tsens_tz_sensor1 {
115 polling-delay-passive = <0>;
116 polling-delay = <0>;
117 thermal-sensors = <&tsens 1>;
118
119 trips {
120 cpu-critical-hi {
121 temperature = <125000>;
122 hysteresis = <2000>;
123 type = "critical_high";
124 };
125
126 cpu-config-hi {
127 temperature = <105000>;
128 hysteresis = <2000>;
129 type = "configurable_hi";
130 };
131
132 cpu-config-lo {
133 temperature = <95000>;
134 hysteresis = <2000>;
135 type = "configurable_lo";
136 };
137
138 cpu-critical-low {
139 temperature = <0>;
140 hysteresis = <2000>;
141 type = "critical_low";
142 };
143 };
144 };
145
146 tsens_tz_sensor2 {
147 polling-delay-passive = <0>;
148 polling-delay = <0>;
149 thermal-sensors = <&tsens 2>;
150
151 trips {
152 cpu-critical-hi {
153 temperature = <125000>;
154 hysteresis = <2000>;
155 type = "critical_high";
156 };
157
158 cpu-config-hi {
159 temperature = <105000>;
160 hysteresis = <2000>;
161 type = "configurable_hi";
162 };
163
164 cpu-config-lo {
165 temperature = <95000>;
166 hysteresis = <2000>;
167 type = "configurable_lo";
168 };
169
170 cpu-critical-low {
171 temperature = <0>;
172 hysteresis = <2000>;
173 type = "critical_low";
174 };
175 };
176 };
177
178 tsens_tz_sensor3 {
179 polling-delay-passive = <0>;
180 polling-delay = <0>;
181 thermal-sensors = <&tsens 3>;
182
183 trips {
184 cpu-critical-hi {
185 temperature = <125000>;
186 hysteresis = <2000>;
187 type = "critical_high";
188 };
189
190 cpu-config-hi {
191 temperature = <105000>;
192 hysteresis = <2000>;
193 type = "configurable_hi";
194 };
195
196 cpu-config-lo {
197 temperature = <95000>;
198 hysteresis = <2000>;
199 type = "configurable_lo";
200 };
201
202 cpu-critical-low {
203 temperature = <0>;
204 hysteresis = <2000>;
205 type = "critical_low";
206 };
207 };
208 };
209
210 tsens_tz_sensor4 {
211 polling-delay-passive = <0>;
212 polling-delay = <0>;
213 thermal-sensors = <&tsens 4>;
214
215 trips {
216 cpu-critical-hi {
217 temperature = <125000>;
218 hysteresis = <2000>;
219 type = "critical_high";
220 };
221
222 cpu-config-hi {
223 temperature = <105000>;
224 hysteresis = <2000>;
225 type = "configurable_hi";
226 };
227
228 cpu-config-lo {
229 temperature = <95000>;
230 hysteresis = <2000>;
231 type = "configurable_lo";
232 };
233
234 cpu-critical-low {
235 temperature = <0>;
236 hysteresis = <2000>;
237 type = "critical_low";
238 };
239 };
240 };
241
242 tsens_tz_sensor5 {
243 polling-delay-passive = <0>;
244 polling-delay = <0>;
245 thermal-sensors = <&tsens 5>;
246
247 trips {
248 cpu-critical-hi {
249 temperature = <125000>;
250 hysteresis = <2000>;
251 type = "critical_high";
252 };
253
254 cpu-config-hi {
255 temperature = <105000>;
256 hysteresis = <2000>;
257 type = "configurable_hi";
258 };
259
260 cpu-config-lo {
261 temperature = <95000>;
262 hysteresis = <2000>;
263 type = "configurable_lo";
264 };
265
266 cpu-critical-low {
267 temperature = <0>;
268 hysteresis = <2000>;
269 type = "critical_low";
270 };
271 };
272 };
273
274 tsens_tz_sensor6 {
275 polling-delay-passive = <0>;
276 polling-delay = <0>;
277 thermal-sensors = <&tsens 6>;
278
279 trips {
280 cpu-critical-hi {
281 temperature = <125000>;
282 hysteresis = <2000>;
283 type = "critical_high";
284 };
285
286 cpu-config-hi {
287 temperature = <105000>;
288 hysteresis = <2000>;
289 type = "configurable_hi";
290 };
291
292 cpu-config-lo {
293 temperature = <95000>;
294 hysteresis = <2000>;
295 type = "configurable_lo";
296 };
297
298 cpu-critical-low {
299 temperature = <0>;
300 hysteresis = <2000>;
301 type = "critical_low";
302 };
303 };
304 };
305
306 tsens_tz_sensor7 {
307 polling-delay-passive = <0>;
308 polling-delay = <0>;
309 thermal-sensors = <&tsens 7>;
310
311 trips {
312 cpu-critical-hi {
313 temperature = <125000>;
314 hysteresis = <2000>;
315 type = "critical_high";
316 };
317
318 cpu-config-hi {
319 temperature = <105000>;
320 hysteresis = <2000>;
321 type = "configurable_hi";
322 };
323
324 cpu-config-lo {
325 temperature = <95000>;
326 hysteresis = <2000>;
327 type = "configurable_lo";
328 };
329
330 cpu-critical-low {
331 temperature = <0>;
332 hysteresis = <2000>;
333 type = "critical_low";
334 };
335 };
336 };
337
338 tsens_tz_sensor8 {
339 polling-delay-passive = <0>;
340 polling-delay = <0>;
341 thermal-sensors = <&tsens 8>;
342
343 trips {
344 cpu-critical-hi {
345 temperature = <125000>;
346 hysteresis = <2000>;
347 type = "critical_high";
348 };
349
350 cpu-config-hi {
351 temperature = <105000>;
352 hysteresis = <2000>;
353 type = "configurable_hi";
354 };
355
356 cpu-config-lo {
357 temperature = <95000>;
358 hysteresis = <2000>;
359 type = "configurable_lo";
360 };
361
362 cpu-critical-low {
363 temperature = <0>;
364 hysteresis = <2000>;
365 type = "critical_low";
366 };
367 };
368 };
369
370 tsens_tz_sensor9 {
371 polling-delay-passive = <0>;
372 polling-delay = <0>;
373 thermal-sensors = <&tsens 9>;
374
375 trips {
376 cpu-critical-hi {
377 temperature = <125000>;
378 hysteresis = <2000>;
379 type = "critical_high";
380 };
381
382 cpu-config-hi {
383 temperature = <105000>;
384 hysteresis = <2000>;
385 type = "configurable_hi";
386 };
387
388 cpu-config-lo {
389 temperature = <95000>;
390 hysteresis = <2000>;
391 type = "configurable_lo";
392 };
393
394 cpu-critical-low {
395 temperature = <0>;
396 hysteresis = <2000>;
397 type = "critical_low";
398 };
399 };
400 };
401
402 tsens_tz_sensor10 {
403 polling-delay-passive = <0>;
404 polling-delay = <0>;
405 thermal-sensors = <&tsens 10>;
406
407 trips {
408 cpu-critical-hi {
409 temperature = <125000>;
410 hysteresis = <2000>;
411 type = "critical_high";
412 };
413
414 cpu-config-hi {
415 temperature = <105000>;
416 hysteresis = <2000>;
417 type = "configurable_hi";
418 };
419
420 cpu-config-lo {
421 temperature = <95000>;
422 hysteresis = <2000>;
423 type = "configurable_lo";
424 };
425
426 cpu-critical-low {
427 temperature = <0>;
428 hysteresis = <2000>;
429 type = "critical_low";
430 };
431 };
432 };
433 };
434
435 cpu-pmu {
436 compatible = "qcom,krait-pmu";
437 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
438 IRQ_TYPE_LEVEL_HIGH)>;
439 };
440
441 reserved-memory {
442 #address-cells = <1>;
443 #size-cells = <1>;
444 ranges;
445
446 nss@40000000 {
447 reg = <0x40000000 0x1000000>;
448 no-map;
449 };
450
451 smem: smem@41000000 {
452 reg = <0x41000000 0x200000>;
453 no-map;
454 };
455 };
456
457 clocks {
458 cxo_board {
459 compatible = "fixed-clock";
460 #clock-cells = <0>;
461 clock-frequency = <25000000>;
462 };
463
464 pxo_board {
465 compatible = "fixed-clock";
466 #clock-cells = <0>;
467 clock-frequency = <25000000>;
468 };
469
470 sleep_clk: sleep_clk {
471 compatible = "fixed-clock";
472 clock-frequency = <32768>;
473 #clock-cells = <0>;
474 };
475 };
476
477 firmware {
478 scm {
479 compatible = "qcom,scm-ipq806x";
480 };
481 };
482
483 kraitcc: clock-controller {
484 compatible = "qcom,krait-cc-v1";
485 #clock-cells = <1>;
486 };
487
488 qcom,pvs {
489 qcom,pvs-format-a;
490 qcom,speed0-pvs0-bin-v0 =
491 < 1400000000 1250000 >,
492 < 1200000000 1200000 >,
493 < 1000000000 1150000 >,
494 < 800000000 1100000 >,
495 < 600000000 1050000 >,
496 < 384000000 1000000 >;
497
498 qcom,speed0-pvs1-bin-v0 =
499 < 1400000000 1175000 >,
500 < 1200000000 1125000 >,
501 < 1000000000 1075000 >,
502 < 800000000 1025000 >,
503 < 600000000 975000 >,
504 < 384000000 925000 >;
505
506 qcom,speed0-pvs2-bin-v0 =
507 < 1400000000 1125000 >,
508 < 1200000000 1075000 >,
509 < 1000000000 1025000 >,
510 < 800000000 995000 >,
511 < 600000000 925000 >,
512 < 384000000 875000 >;
513
514 qcom,speed0-pvs3-bin-v0 =
515 < 1400000000 1050000 >,
516 < 1200000000 1000000 >,
517 < 1000000000 950000 >,
518 < 800000000 900000 >,
519 < 600000000 850000 >,
520 < 384000000 800000 >;
521 };
522
523 soc: soc {
524 #address-cells = <1>;
525 #size-cells = <1>;
526 ranges;
527 compatible = "simple-bus";
528
529 lpass@28100000 {
530 compatible = "qcom,lpass-cpu";
531 status = "disabled";
532 clocks = <&lcc AHBIX_CLK>,
533 <&lcc MI2S_OSR_CLK>,
534 <&lcc MI2S_BIT_CLK>;
535 clock-names = "ahbix-clk",
536 "mi2s-osr-clk",
537 "mi2s-bit-clk";
538 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
539 interrupt-names = "lpass-irq-lpaif";
540 reg = <0x28100000 0x10000>;
541 reg-names = "lpass-lpaif";
542 };
543
544 qfprom: qfprom@700000 {
545 compatible = "qcom,qfprom", "syscon";
546 reg = <0x700000 0x1000>;
547 #address-cells = <1>;
548 #size-cells = <1>;
549 status = "okay";
550 tsens_calib: calib@400 {
551 reg = <0x400 0x10>;
552 };
553 tsens_backup: backup@410 {
554 reg = <0x410 0x10>;
555 };
556 };
557
558 rpm@108000 {
559 compatible = "qcom,rpm-ipq8064";
560 reg = <0x108000 0x1000>;
561 qcom,ipc = <&l2cc 0x8 2>;
562
563 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "ack",
567 "err",
568 "wakeup";
569
570 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
571 clock-names = "ram";
572
573 #address-cells = <1>;
574 #size-cells = <0>;
575
576 rpmcc: clock-controller {
577 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
578 #clock-cells = <1>;
579 };
580
581 regulators {
582 compatible = "qcom,rpm-smb208-regulators";
583
584 smb208_s1a: s1a {
585 regulator-min-microvolt = <1050000>;
586 regulator-max-microvolt = <1150000>;
587
588 qcom,switch-mode-frequency = <1200000>;
589
590 };
591
592 smb208_s1b: s1b {
593 regulator-min-microvolt = <1050000>;
594 regulator-max-microvolt = <1150000>;
595
596 qcom,switch-mode-frequency = <1200000>;
597 };
598
599 smb208_s2a: s2a {
600 regulator-min-microvolt = < 800000>;
601 regulator-max-microvolt = <1250000>;
602
603 qcom,switch-mode-frequency = <1200000>;
604 };
605
606 smb208_s2b: s2b {
607 regulator-min-microvolt = < 800000>;
608 regulator-max-microvolt = <1250000>;
609
610 qcom,switch-mode-frequency = <1200000>;
611 };
612 };
613 };
614
615 rng@1a500000 {
616 compatible = "qcom,prng";
617 reg = <0x1a500000 0x200>;
618 clocks = <&gcc PRNG_CLK>;
619 clock-names = "core";
620 };
621
622 qcom_pinmux: pinmux@800000 {
623 compatible = "qcom,ipq8064-pinctrl";
624 reg = <0x800000 0x4000>;
625
626 gpio-controller;
627 #gpio-cells = <2>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
630 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
631
632 pcie0_pins: pcie0_pinmux {
633 mux {
634 pins = "gpio3";
635 function = "pcie1_rst";
636 drive-strength = <2>;
637 bias-disable;
638 };
639 };
640
641 pcie1_pins: pcie1_pinmux {
642 mux {
643 pins = "gpio48";
644 function = "pcie2_rst";
645 drive-strength = <2>;
646 bias-disable;
647 };
648 };
649
650 pcie2_pins: pcie2_pinmux {
651 mux {
652 pins = "gpio63";
653 function = "pcie3_rst";
654 drive-strength = <2>;
655 bias-disable;
656 output-low;
657 };
658 };
659
660 spi_pins: spi_pins {
661 mux {
662 pins = "gpio18", "gpio19", "gpio21";
663 function = "gsbi5";
664 drive-strength = <10>;
665 bias-none;
666 };
667 };
668
669 leds_pins: leds_pins {
670 mux {
671 pins = "gpio7", "gpio8", "gpio9",
672 "gpio26", "gpio53";
673 function = "gpio";
674 drive-strength = <2>;
675 bias-pull-down;
676 output-low;
677 };
678 };
679
680 buttons_pins: buttons_pins {
681 mux {
682 pins = "gpio54";
683 drive-strength = <2>;
684 bias-pull-up;
685 };
686 };
687 };
688
689 intc: interrupt-controller@2000000 {
690 compatible = "qcom,msm-qgic2";
691 interrupt-controller;
692 #interrupt-cells = <3>;
693 reg = <0x02000000 0x1000>,
694 <0x02002000 0x1000>;
695 };
696
697 timer@200a000 {
698 compatible = "qcom,kpss-timer", "qcom,msm-timer";
699 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
700 IRQ_TYPE_EDGE_RISING)>,
701 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
702 IRQ_TYPE_EDGE_RISING)>,
703 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
704 IRQ_TYPE_EDGE_RISING)>,
705 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
706 IRQ_TYPE_EDGE_RISING)>,
707 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
708 IRQ_TYPE_EDGE_RISING)>;
709 reg = <0x0200a000 0x100>;
710 clock-frequency = <25000000>,
711 <32768>;
712 clocks = <&sleep_clk>;
713 clock-names = "sleep";
714 cpu-offset = <0x80000>;
715 };
716
717 acc0: clock-controller@2088000 {
718 compatible = "qcom,kpss-acc-v1";
719 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
720 clock-output-names = "acpu0_aux";
721 };
722
723 acc1: clock-controller@2098000 {
724 compatible = "qcom,kpss-acc-v1";
725 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
726 clock-output-names = "acpu1_aux";
727 };
728
729 l2cc: clock-controller@2011000 {
730 compatible = "qcom,kpss-gcc", "syscon";
731 reg = <0x2011000 0x1000>;
732 clock-output-names = "acpu_l2_aux";
733 };
734
735 saw0: regulator@2089000 {
736 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
737 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
738 regulator;
739 };
740
741 saw1: regulator@2099000 {
742 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
743 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
744 regulator;
745 };
746
747 saw_l2: regulator@02012000 {
748 compatible = "qcom,saw2", "syscon";
749 reg = <0x02012000 0x1000>;
750 regulator;
751 };
752
753 sic_non_secure: sic-non-secure@12100000 {
754 compatible = "syscon";
755 reg = <0x12100000 0x10000>;
756 };
757
758 gsbi2: gsbi@12480000 {
759 compatible = "qcom,gsbi-v1.0.0";
760 cell-index = <2>;
761 reg = <0x12480000 0x100>;
762 clocks = <&gcc GSBI2_H_CLK>;
763 clock-names = "iface";
764 #address-cells = <1>;
765 #size-cells = <1>;
766 ranges;
767 status = "disabled";
768
769 syscon-tcsr = <&tcsr>;
770
771 uart2: serial@12490000 {
772 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
773 reg = <0x12490000 0x1000>,
774 <0x12480000 0x1000>;
775 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
777 clock-names = "core", "iface";
778 status = "disabled";
779 };
780
781 i2c@124a0000 {
782 compatible = "qcom,i2c-qup-v1.1.1";
783 reg = <0x124a0000 0x1000>;
784 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
785
786 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
787 clock-names = "core", "iface";
788 status = "disabled";
789
790 #address-cells = <1>;
791 #size-cells = <0>;
792 };
793
794 };
795
796 gsbi4: gsbi@16300000 {
797 compatible = "qcom,gsbi-v1.0.0";
798 cell-index = <4>;
799 reg = <0x16300000 0x100>;
800 clocks = <&gcc GSBI4_H_CLK>;
801 clock-names = "iface";
802 #address-cells = <1>;
803 #size-cells = <1>;
804 ranges;
805 status = "disabled";
806
807 syscon-tcsr = <&tcsr>;
808
809 gsbi4_serial: serial@16340000 {
810 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
811 reg = <0x16340000 0x1000>,
812 <0x16300000 0x1000>;
813 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
815 clock-names = "core", "iface";
816 status = "disabled";
817 };
818
819 i2c@16380000 {
820 compatible = "qcom,i2c-qup-v1.1.1";
821 reg = <0x16380000 0x1000>;
822 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
823
824 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
825 clock-names = "core", "iface";
826 status = "disabled";
827
828 #address-cells = <1>;
829 #size-cells = <0>;
830 };
831 };
832
833 gsbi5: gsbi@1a200000 {
834 compatible = "qcom,gsbi-v1.0.0";
835 cell-index = <5>;
836 reg = <0x1a200000 0x100>;
837 clocks = <&gcc GSBI5_H_CLK>;
838 clock-names = "iface";
839 #address-cells = <1>;
840 #size-cells = <1>;
841 ranges;
842 status = "disabled";
843
844 syscon-tcsr = <&tcsr>;
845
846 uart5: serial@1a240000 {
847 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
848 reg = <0x1a240000 0x1000>,
849 <0x1a200000 0x1000>;
850 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
852 clock-names = "core", "iface";
853 status = "disabled";
854 };
855
856 i2c@1a280000 {
857 compatible = "qcom,i2c-qup-v1.1.1";
858 reg = <0x1a280000 0x1000>;
859 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
860
861 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
862 clock-names = "core", "iface";
863 status = "disabled";
864
865 #address-cells = <1>;
866 #size-cells = <0>;
867 };
868
869 spi@1a280000 {
870 compatible = "qcom,spi-qup-v1.1.1";
871 reg = <0x1a280000 0x1000>;
872 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
873
874 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
875 clock-names = "core", "iface";
876 status = "disabled";
877
878 #address-cells = <1>;
879 #size-cells = <0>;
880 };
881 };
882
883 gsbi7: gsbi@16600000 {
884 status = "disabled";
885 compatible = "qcom,gsbi-v1.0.0";
886 cell-index = <7>;
887 reg = <0x16600000 0x100>;
888 clocks = <&gcc GSBI7_H_CLK>;
889 clock-names = "iface";
890 #address-cells = <1>;
891 #size-cells = <1>;
892 ranges;
893 syscon-tcsr = <&tcsr>;
894
895 gsbi7_serial: serial@16640000 {
896 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
897 reg = <0x16640000 0x1000>,
898 <0x16600000 0x1000>;
899 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
901 clock-names = "core", "iface";
902 status = "disabled";
903 };
904 };
905
906 sata_phy: sata-phy@1b400000 {
907 compatible = "qcom,ipq806x-sata-phy";
908 reg = <0x1b400000 0x200>;
909
910 clocks = <&gcc SATA_PHY_CFG_CLK>;
911 clock-names = "cfg";
912
913 #phy-cells = <0>;
914 status = "disabled";
915 };
916
917 sata@29000000 {
918 compatible = "qcom,ipq806x-ahci", "generic-ahci";
919 reg = <0x29000000 0x180>;
920
921 ports-implemented = <0x1>;
922
923 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
924
925 clocks = <&gcc SFAB_SATA_S_H_CLK>,
926 <&gcc SATA_H_CLK>,
927 <&gcc SATA_A_CLK>,
928 <&gcc SATA_RXOOB_CLK>,
929 <&gcc SATA_PMALIVE_CLK>;
930 clock-names = "slave_face", "iface", "core",
931 "rxoob", "pmalive";
932
933 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
934 assigned-clock-rates = <100000000>, <100000000>;
935
936 phys = <&sata_phy>;
937 phy-names = "sata-phy";
938 status = "disabled";
939 };
940
941 qcom,ssbi@500000 {
942 compatible = "qcom,ssbi";
943 reg = <0x00500000 0x1000>;
944 qcom,controller-type = "pmic-arbiter";
945 };
946
947 gcc: clock-controller@900000 {
948 compatible = "qcom,gcc-ipq8064";
949 reg = <0x00900000 0x4000>;
950 #clock-cells = <1>;
951 #reset-cells = <1>;
952 #power-domain-cells = <1>;
953 };
954
955 tsens: thermal-sensor@900000 {
956 compatible = "qcom,ipq8064-tsens";
957 reg = <0x900000 0x3680>;
958 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
959 nvmem-cell-names = "calib", "calib_backup";
960 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
961 #thermal-sensor-cells = <1>;
962 };
963
964 tcsr: syscon@1a400000 {
965 compatible = "qcom,tcsr-ipq8064", "syscon";
966 reg = <0x1a400000 0x100>;
967 };
968
969 lcc: clock-controller@28000000 {
970 compatible = "qcom,lcc-ipq8064";
971 reg = <0x28000000 0x1000>;
972 #clock-cells = <1>;
973 #reset-cells = <1>;
974 };
975
976 sfpb_mutex_block: syscon@1200600 {
977 compatible = "syscon";
978 reg = <0x01200600 0x100>;
979 };
980
981 hs_phy_0: hs_phy_0 {
982 compatible = "qcom,dwc3-hs-usb-phy";
983 regmap = <&usb3_0>;
984 clocks = <&gcc USB30_0_UTMI_CLK>;
985 clock-names = "ref";
986 #phy-cells = <0>;
987 };
988
989 ss_phy_0: ss_phy_0 {
990 compatible = "qcom,dwc3-ss-usb-phy";
991 regmap = <&usb3_0>;
992 clocks = <&gcc USB30_0_MASTER_CLK>;
993 clock-names = "ref";
994 #phy-cells = <0>;
995 };
996
997 usb3_0: usb3@110f8800 {
998 compatible = "qcom,dwc3", "syscon";
999 #address-cells = <1>;
1000 #size-cells = <1>;
1001 reg = <0x110f8800 0x8000>;
1002 clocks = <&gcc USB30_0_MASTER_CLK>;
1003 clock-names = "core";
1004
1005 ranges;
1006
1007 resets = <&gcc USB30_0_MASTER_RESET>;
1008 reset-names = "master";
1009
1010 status = "disabled";
1011
1012 dwc3_0: dwc3@11000000 {
1013 compatible = "snps,dwc3";
1014 reg = <0x11000000 0xcd00>;
1015 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1016 phys = <&hs_phy_0>, <&ss_phy_0>;
1017 phy-names = "usb2-phy", "usb3-phy";
1018 dr_mode = "host";
1019 snps,dis_u3_susphy_quirk;
1020 };
1021 };
1022
1023 hs_phy_1: hs_phy_1 {
1024 compatible = "qcom,dwc3-hs-usb-phy";
1025 regmap = <&usb3_1>;
1026 clocks = <&gcc USB30_1_UTMI_CLK>;
1027 clock-names = "ref";
1028 #phy-cells = <0>;
1029 };
1030
1031 ss_phy_1: ss_phy_1 {
1032 compatible = "qcom,dwc3-ss-usb-phy";
1033 regmap = <&usb3_1>;
1034 clocks = <&gcc USB30_1_MASTER_CLK>;
1035 clock-names = "ref";
1036 #phy-cells = <0>;
1037 };
1038
1039 usb3_1: usb3@100f8800 {
1040 compatible = "qcom,dwc3", "syscon";
1041 #address-cells = <1>;
1042 #size-cells = <1>;
1043 reg = <0x100f8800 0x8000>;
1044 clocks = <&gcc USB30_1_MASTER_CLK>;
1045 clock-names = "core";
1046
1047 ranges;
1048
1049 resets = <&gcc USB30_1_MASTER_RESET>;
1050 reset-names = "master";
1051
1052 status = "disabled";
1053
1054 dwc3_1: dwc3@10000000 {
1055 compatible = "snps,dwc3";
1056 reg = <0x10000000 0xcd00>;
1057 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1058 phys = <&hs_phy_1>, <&ss_phy_1>;
1059 phy-names = "usb2-phy", "usb3-phy";
1060 dr_mode = "host";
1061 snps,dis_u3_susphy_quirk;
1062 };
1063 };
1064
1065 pcie0: pci@1b500000 {
1066 compatible = "qcom,pcie-ipq8064";
1067 reg = <0x1b500000 0x1000
1068 0x1b502000 0x80
1069 0x1b600000 0x100
1070 0x0ff00000 0x100000>;
1071 reg-names = "dbi", "elbi", "parf", "config";
1072 device_type = "pci";
1073 linux,pci-domain = <0>;
1074 bus-range = <0x00 0xff>;
1075 num-lanes = <1>;
1076 #address-cells = <3>;
1077 #size-cells = <2>;
1078
1079 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1080 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1081
1082 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1083 interrupt-names = "msi";
1084 #interrupt-cells = <1>;
1085 interrupt-map-mask = <0 0 0 0x7>;
1086 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1087 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1088 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1089 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1090
1091 clocks = <&gcc PCIE_A_CLK>,
1092 <&gcc PCIE_H_CLK>,
1093 <&gcc PCIE_PHY_CLK>,
1094 <&gcc PCIE_AUX_CLK>,
1095 <&gcc PCIE_ALT_REF_CLK>;
1096 clock-names = "core", "iface", "phy", "aux", "ref";
1097
1098 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1099 assigned-clock-rates = <100000000>;
1100
1101 resets = <&gcc PCIE_ACLK_RESET>,
1102 <&gcc PCIE_HCLK_RESET>,
1103 <&gcc PCIE_POR_RESET>,
1104 <&gcc PCIE_PCI_RESET>,
1105 <&gcc PCIE_PHY_RESET>,
1106 <&gcc PCIE_EXT_RESET>;
1107 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1108
1109 pinctrl-0 = <&pcie0_pins>;
1110 pinctrl-names = "default";
1111
1112 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1113
1114 phy-tx0-term-offset = <7>;
1115
1116 status = "disabled";
1117 };
1118
1119 pcie1: pci@1b700000 {
1120 compatible = "qcom,pcie-ipq8064";
1121 reg = <0x1b700000 0x1000
1122 0x1b702000 0x80
1123 0x1b800000 0x100
1124 0x31f00000 0x100000>;
1125 reg-names = "dbi", "elbi", "parf", "config";
1126 device_type = "pci";
1127 linux,pci-domain = <1>;
1128 bus-range = <0x00 0xff>;
1129 num-lanes = <1>;
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1132
1133 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1134 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1135
1136 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1137 interrupt-names = "msi";
1138 #interrupt-cells = <1>;
1139 interrupt-map-mask = <0 0 0 0x7>;
1140 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1141 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1142 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1143 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1144
1145 clocks = <&gcc PCIE_1_A_CLK>,
1146 <&gcc PCIE_1_H_CLK>,
1147 <&gcc PCIE_1_PHY_CLK>,
1148 <&gcc PCIE_1_AUX_CLK>,
1149 <&gcc PCIE_1_ALT_REF_CLK>;
1150 clock-names = "core", "iface", "phy", "aux", "ref";
1151
1152 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1153 assigned-clock-rates = <100000000>;
1154
1155 resets = <&gcc PCIE_1_ACLK_RESET>,
1156 <&gcc PCIE_1_HCLK_RESET>,
1157 <&gcc PCIE_1_POR_RESET>,
1158 <&gcc PCIE_1_PCI_RESET>,
1159 <&gcc PCIE_1_PHY_RESET>,
1160 <&gcc PCIE_1_EXT_RESET>;
1161 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1162
1163 pinctrl-0 = <&pcie1_pins>;
1164 pinctrl-names = "default";
1165
1166 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1167
1168 phy-tx0-term-offset = <7>;
1169
1170 status = "disabled";
1171 };
1172
1173 pcie2: pci@1b900000 {
1174 compatible = "qcom,pcie-ipq8064";
1175 reg = <0x1b900000 0x1000
1176 0x1b902000 0x80
1177 0x1ba00000 0x100
1178 0x35f00000 0x100000>;
1179 reg-names = "dbi", "elbi", "parf", "config";
1180 device_type = "pci";
1181 linux,pci-domain = <2>;
1182 bus-range = <0x00 0xff>;
1183 num-lanes = <1>;
1184 #address-cells = <3>;
1185 #size-cells = <2>;
1186
1187 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1188 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1189
1190 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1191 interrupt-names = "msi";
1192 #interrupt-cells = <1>;
1193 interrupt-map-mask = <0 0 0 0x7>;
1194 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1195 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1196 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1197 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1198
1199 clocks = <&gcc PCIE_2_A_CLK>,
1200 <&gcc PCIE_2_H_CLK>,
1201 <&gcc PCIE_2_PHY_CLK>,
1202 <&gcc PCIE_2_AUX_CLK>,
1203 <&gcc PCIE_2_ALT_REF_CLK>;
1204 clock-names = "core", "iface", "phy", "aux", "ref";
1205
1206 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1207 assigned-clock-rates = <100000000>;
1208
1209 resets = <&gcc PCIE_2_ACLK_RESET>,
1210 <&gcc PCIE_2_HCLK_RESET>,
1211 <&gcc PCIE_2_POR_RESET>,
1212 <&gcc PCIE_2_PCI_RESET>,
1213 <&gcc PCIE_2_PHY_RESET>,
1214 <&gcc PCIE_2_EXT_RESET>;
1215 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1216
1217 pinctrl-0 = <&pcie2_pins>;
1218 pinctrl-names = "default";
1219
1220 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1221
1222 phy-tx0-term-offset = <7>;
1223
1224 status = "disabled";
1225 };
1226
1227 adm_dma: dma@18300000 {
1228 compatible = "qcom,adm";
1229 reg = <0x18300000 0x100000>;
1230 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1231 #dma-cells = <1>;
1232
1233 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1234 clock-names = "core", "iface";
1235
1236 resets = <&gcc ADM0_RESET>,
1237 <&gcc ADM0_PBUS_RESET>,
1238 <&gcc ADM0_C0_RESET>,
1239 <&gcc ADM0_C1_RESET>,
1240 <&gcc ADM0_C2_RESET>;
1241 reset-names = "clk", "pbus", "c0", "c1", "c2";
1242 qcom,ee = <0>;
1243
1244 status = "disabled";
1245 };
1246
1247 nand@1ac00000 {
1248 compatible = "qcom,ipq806x-nand";
1249 reg = <0x1ac00000 0x800>;
1250
1251 clocks = <&gcc EBI2_CLK>,
1252 <&gcc EBI2_AON_CLK>;
1253 clock-names = "core", "aon";
1254
1255 dmas = <&adm_dma 3>;
1256 dma-names = "rxtx";
1257 qcom,cmd-crci = <15>;
1258 qcom,data-crci = <3>;
1259
1260 status = "disabled";
1261
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1264 };
1265
1266 nss_common: syscon@03000000 {
1267 compatible = "syscon";
1268 reg = <0x03000000 0x0000FFFF>;
1269 };
1270
1271 qsgmii_csr: syscon@1bb00000 {
1272 compatible = "syscon";
1273 reg = <0x1bb00000 0x000001FF>;
1274 };
1275
1276 stmmac_axi_setup: stmmac-axi-config {
1277 snps,wr_osr_lmt = <7>;
1278 snps,rd_osr_lmt = <7>;
1279 snps,blen = <16 0 0 0 0 0 0>;
1280 };
1281
1282 gmac0: ethernet@37000000 {
1283 device_type = "network";
1284 compatible = "qcom,ipq806x-gmac";
1285 reg = <0x37000000 0x200000>;
1286 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1287 interrupt-names = "macirq";
1288
1289 snps,axi-config = <&stmmac_axi_setup>;
1290 snps,pbl = <32>;
1291 snps,aal = <1>;
1292
1293 qcom,nss-common = <&nss_common>;
1294 qcom,qsgmii-csr = <&qsgmii_csr>;
1295
1296 clocks = <&gcc GMAC_CORE1_CLK>;
1297 clock-names = "stmmaceth";
1298
1299 resets = <&gcc GMAC_CORE1_RESET>;
1300 reset-names = "stmmaceth";
1301
1302 status = "disabled";
1303 };
1304
1305 gmac1: ethernet@37200000 {
1306 device_type = "network";
1307 compatible = "qcom,ipq806x-gmac";
1308 reg = <0x37200000 0x200000>;
1309 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1310 interrupt-names = "macirq";
1311
1312 snps,axi-config = <&stmmac_axi_setup>;
1313 snps,pbl = <32>;
1314 snps,aal = <1>;
1315
1316 qcom,nss-common = <&nss_common>;
1317 qcom,qsgmii-csr = <&qsgmii_csr>;
1318
1319 clocks = <&gcc GMAC_CORE2_CLK>;
1320 clock-names = "stmmaceth";
1321
1322 resets = <&gcc GMAC_CORE2_RESET>;
1323 reset-names = "stmmaceth";
1324
1325 status = "disabled";
1326 };
1327
1328 gmac2: ethernet@37400000 {
1329 device_type = "network";
1330 compatible = "qcom,ipq806x-gmac";
1331 reg = <0x37400000 0x200000>;
1332 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1333 interrupt-names = "macirq";
1334
1335 snps,axi-config = <&stmmac_axi_setup>;
1336 snps,pbl = <32>;
1337 snps,aal = <1>;
1338
1339 qcom,nss-common = <&nss_common>;
1340 qcom,qsgmii-csr = <&qsgmii_csr>;
1341
1342 clocks = <&gcc GMAC_CORE3_CLK>;
1343 clock-names = "stmmaceth";
1344
1345 resets = <&gcc GMAC_CORE3_RESET>;
1346 reset-names = "stmmaceth";
1347
1348 status = "disabled";
1349 };
1350
1351 gmac3: ethernet@37600000 {
1352 device_type = "network";
1353 compatible = "qcom,ipq806x-gmac";
1354 reg = <0x37600000 0x200000>;
1355 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1356 interrupt-names = "macirq";
1357
1358 snps,axi-config = <&stmmac_axi_setup>;
1359 snps,pbl = <32>;
1360 snps,aal = <1>;
1361
1362 qcom,nss-common = <&nss_common>;
1363 qcom,qsgmii-csr = <&qsgmii_csr>;
1364
1365 clocks = <&gcc GMAC_CORE4_CLK>;
1366 clock-names = "stmmaceth";
1367
1368 resets = <&gcc GMAC_CORE4_RESET>;
1369 reset-names = "stmmaceth";
1370
1371 status = "disabled";
1372 };
1373
1374 /* Temporary fixed regulator */
1375 vsdcc_fixed: vsdcc-regulator {
1376 compatible = "regulator-fixed";
1377 regulator-name = "SDCC Power";
1378 regulator-min-microvolt = <3300000>;
1379 regulator-max-microvolt = <3300000>;
1380 regulator-always-on;
1381 };
1382
1383 sdcc1bam:dma@12402000 {
1384 compatible = "qcom,bam-v1.3.0";
1385 reg = <0x12402000 0x8000>;
1386 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1387 clocks = <&gcc SDC1_H_CLK>;
1388 clock-names = "bam_clk";
1389 #dma-cells = <1>;
1390 qcom,ee = <0>;
1391 };
1392
1393 sdcc3bam:dma@12182000 {
1394 compatible = "qcom,bam-v1.3.0";
1395 reg = <0x12182000 0x8000>;
1396 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&gcc SDC3_H_CLK>;
1398 clock-names = "bam_clk";
1399 #dma-cells = <1>;
1400 qcom,ee = <0>;
1401 };
1402
1403 amba {
1404 compatible = "arm,amba-bus";
1405 #address-cells = <1>;
1406 #size-cells = <1>;
1407 ranges;
1408 sdcc1: sdcc@12400000 {
1409 status = "disabled";
1410 compatible = "arm,pl18x", "arm,primecell";
1411 arm,primecell-periphid = <0x00051180>;
1412 reg = <0x12400000 0x2000>;
1413 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1414 interrupt-names = "cmd_irq";
1415 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1416 clock-names = "mclk", "apb_pclk";
1417 bus-width = <8>;
1418 max-frequency = <96000000>;
1419 non-removable;
1420 cap-sd-highspeed;
1421 cap-mmc-highspeed;
1422 vmmc-supply = <&vsdcc_fixed>;
1423 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1424 dma-names = "tx", "rx";
1425 };
1426
1427 sdcc3: sdcc@12180000 {
1428 compatible = "arm,pl18x", "arm,primecell";
1429 arm,primecell-periphid = <0x00051180>;
1430 status = "disabled";
1431 reg = <0x12180000 0x2000>;
1432 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1433 interrupt-names = "cmd_irq";
1434 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1435 clock-names = "mclk", "apb_pclk";
1436 bus-width = <8>;
1437 cap-sd-highspeed;
1438 cap-mmc-highspeed;
1439 max-frequency = <192000000>;
1440 #mmc-ddr-1_8v;
1441 sd-uhs-sdr104;
1442 sd-uhs-ddr50;
1443 vqmmc-supply = <&vsdcc_fixed>;
1444 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1445 dma-names = "tx", "rx";
1446 };
1447 };
1448 };
1449
1450 sfpb_mutex: sfpb-mutex {
1451 compatible = "qcom,sfpb-mutex";
1452 syscon = <&sfpb_mutex_block 4 4>;
1453
1454 #hwlock-cells = <1>;
1455 };
1456
1457 smem {
1458 compatible = "qcom,smem";
1459 memory-region = <&smem>;
1460 hwlocks = <&sfpb_mutex 3>;
1461 };
1462 };
OpenWrt Source Repository